Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

1 files changed, 31 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/arch/powerpc/include/asm/ppc460sx.h b/qemu/roms/u-boot/arch/powerpc/include/asm/ppc460sx.h
new file mode 100644
index 000000000..b692d07f3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/powerpc/include/asm/ppc460sx.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PPC460SX_H_
+#define _PPC460SX_H_
+
+#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
+
+/* Memory mapped registers */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xa0000000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+
+#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+
+#define SDR0_SRST0_DMC			0x00200000
+
+#define PLLSYS0_FWD_DIV_A_MASK	0x000000f0	/* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK	0x0000000f	/* Fwd Div B */
+#define PLLSYS0_FB_DIV_MASK	0x0000ff00	/* Feedback divisor */
+#define PLLSYS0_OPB_DIV_MASK	0x0c000000	/* OPB Divisor */
+#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000	/* PLB Early Clock Divisor */
+#define PLLSYS0_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
+#define PLLSYS0_SEL_MASK	0x18000000	/* 0 = PLL, 1 = PerClk */
+
+#endif /* _PPC460SX_H_ */