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authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/arch/avr32/lib/interrupts.c
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/arch/avr32/lib/interrupts.c')
-rw-r--r--qemu/roms/u-boot/arch/avr32/lib/interrupts.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/arch/avr32/lib/interrupts.c b/qemu/roms/u-boot/arch/avr32/lib/interrupts.c
new file mode 100644
index 000000000..bacb2d186
--- /dev/null
+++ b/qemu/roms/u-boot/arch/avr32/lib/interrupts.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+
+#include <asm/sysreg.h>
+
+void enable_interrupts(void)
+{
+ asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET));
+}
+
+int disable_interrupts(void)
+{
+ unsigned long sr;
+
+ sr = sysreg_read(SR);
+ asm volatile("ssrf %0" : : "n"(SYSREG_GM_OFFSET));
+
+#ifdef CONFIG_AT32UC3A0xxx
+ /* Two NOPs are required after masking interrupts on the
+ * AT32UC3A0512ES. See errata 41.4.5.5. */
+ asm("nop");
+ asm("nop");
+#endif
+
+ return !SYSREG_BFEXT(GM, sr);
+}