Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

1 files changed, 0 insertions, 38 deletions

diff --git a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h b/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h
deleted file mode 100644
index d7903c243..000000000
--- a/qemu/roms/u-boot/arch/arm/include/asm/arch-lpc32xx/wdt.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _LPC32XX_WDT_H
-#define _LPC32XX_WDT_H
-
-#include <asm/types.h>
-
-/* Watchdog Timer Registers */
-struct wdt_regs {
-	u32 isr;		/* Interrupt Status Register		*/
-	u32 ctrl;		/* Control Register			*/
-	u32 counter;		/* Counter Value Register		*/
-	u32 mctrl;		/* Match Control Register		*/
-	u32 match0;		/* Match 0 Register			*/
-	u32 emr;		/* External Match Control Register	*/
-	u32 pulse;		/* Reset Pulse Length Register		*/
-	u32 res;		/* Reset Source Register		*/
-};
-
-/* Watchdog Timer Control Register bits */
-#define WDTIM_CTRL_PAUSE_EN		(1 << 2)
-#define WDTIM_CTRL_RESET_COUNT		(1 << 1)
-#define WDTIM_CTRL_COUNT_ENAB		(1 << 0)
-
-/* Watchdog Timer Match Control Register bits */
-#define WDTIM_MCTRL_RESFRC2		(1 << 6)
-#define WDTIM_MCTRL_RESFRC1		(1 << 5)
-#define WDTIM_MCTRL_M_RES2		(1 << 4)
-#define WDTIM_MCTRL_M_RES1		(1 << 3)
-#define WDTIM_MCTRL_STOP_COUNT0		(1 << 2)
-#define WDTIM_MCTRL_RESET_COUNT0	(1 << 1)
-#define WDTIM_MCTRL_MR0_INT		(1 << 0)
-
-#endif /* _LPC32XX_WDT_H */