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authorRajithaY <rajithax.yerrumsetty@intel.com>2017-04-25 03:31:15 -0700
committerRajitha Yerrumchetty <rajithax.yerrumsetty@intel.com>2017-05-22 06:48:08 +0000
commitbb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch)
treeca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/soc.c
parenta14b48d18a9ed03ec191cf16b162206998a895ce (diff)
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to kvmfornfv repo and make use of the updated latest qemu for the execution of all testcase Change-Id: I1280af507a857675c7f81d30c95255635667bdd7 Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/soc.c')
-rw-r--r--qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/soc.c58
1 files changed, 0 insertions, 58 deletions
diff --git a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/soc.c b/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/soc.c
deleted file mode 100644
index 8c7d7d893..000000000
--- a/qemu/roms/u-boot/arch/arm/cpu/armv7/exynos/soc.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2010 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/system.h>
-
-enum l2_cache_params {
- CACHE_TAG_RAM_SETUP = (1 << 9),
- CACHE_DATA_RAM_SETUP = (1 << 5),
- CACHE_TAG_RAM_LATENCY = (2 << 6),
- CACHE_DATA_RAM_LATENCY = (2 << 0)
-};
-
-void reset_cpu(ulong addr)
-{
- writel(0x1, samsung_get_base_swreset());
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-/*
- * Set L2 cache parameters
- */
-static void exynos5_set_l2cache_params(void)
-{
- unsigned int val = 0;
-
- asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
-
- val |= CACHE_TAG_RAM_SETUP |
- CACHE_DATA_RAM_SETUP |
- CACHE_TAG_RAM_LATENCY |
- CACHE_DATA_RAM_LATENCY;
-
- asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
-}
-
-/*
- * Sets L2 cache related parameters before enabling data cache
- */
-void v7_outer_cache_enable(void)
-{
- if (cpu_is_exynos5())
- exynos5_set_l2cache_params();
-}
-#endif