diff options
| author |   RajithaY <rajithax.yerrumsetty@intel.com> | 2017-04-25 03:31:15 -0700 |
|---|---|---|
| committer | Rajitha Yerrumchetty <rajithax.yerrumsetty@intel.com> | 2017-05-22 06:48:08 +0000 |
| commit | bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (patch) | |
| tree | ca11e03542edf2d8f631efeca5e1626d211107e3 /qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs | |
| parent | a14b48d18a9ed03ec191cf16b162206998a895ce (diff) | |
Adding qemu as a submodule of KVMFORNFV
This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs')
17 files changed, 0 insertions, 3140 deletions
diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/Makefile b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/Makefile deleted file mode 100644 index 6c5949455..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/Makefile +++ /dev/null @@ -1,85 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-$(CONFIG_SPL_BUILD) := start.o - -obj-y = clock.o mxs.o iomux.o timer.o - -ifdef CONFIG_SPL_BUILD -obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o -endif - -# Specify the target for use in elftosb call -MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg -MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg - -# Generate HAB-capable IVT -# -# Note on computing the post-IVT size field value for the U-Boot binary. -# The value is the result of adding the following: -# -> The size of U-Boot binary aligned to 64B (u-boot.bin) -# -> The size of IVT block aligned to 64B (u-boot.ivt) -# -> The size of U-Boot signature (u-boot.sig), 3904 B -# -> The 64B hole in front of U-Boot binary for 'struct mxs_spl_data' passing -# -quiet_cmd_mkivt_mxs = MXSIVT $@ -cmd_mkivt_mxs = \ - sz=`expr \`stat -c "%s" $^\` + 64 + 3904 + 128` ; \ - echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" | \ - tr -s " " | xargs -d " " -i printf "%08x\n" "{}" | rev | \ - sed "s/\(.\)\(.\)/\\\\\\\\x\2\1\n/g" | xargs -i printf "{}" >$@ - -# Align binary to 64B -quiet_cmd_mkalign_mxs = MXSALGN $@ -cmd_mkalign_mxs = \ - dd if=$^ of=$@ ibs=64 conv=sync 2>/dev/null && \ - mv $@ $^ - -# Assemble the CSF file -quiet_cmd_mkcsfreq_mxs = MXSCSFR $@ -cmd_mkcsfreq_mxs = \ - ivt=$(word 1,$^) ; \ - bin=$(word 2,$^) ; \ - csf=$(word 3,$^) ; \ - sed "s@VENDOR@$(VENDOR)@g;s@BOARD@$(BOARD)@g" "$$csf" | \ - sed '/^\#\#Blocks/ d' > $@ ; \ - echo " Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \ - echo " $3 0x0 0x40 \"$$ivt\"" >> $@ - -# Sign files -quiet_cmd_mkcst_mxs = MXSCST $@ -cmd_mkcst_mxs = cst -o $@ < $^ \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) - -spl/u-boot-spl.ivt: spl/u-boot-spl.bin - $(call if_changed,mkalign_mxs) - $(call if_changed,mkivt_mxs,$(CONFIG_SPL_TEXT_BASE),\ - 0x00008000,0x00008040) - -u-boot.ivt: u-boot.bin - $(call if_changed,mkalign_mxs) - $(call if_changed,mkivt_mxs,$(CONFIG_SYS_TEXT_BASE),\ - 0x40001000,0x40001040) - -spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf - $(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000) - -u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf - $(call if_changed,mkcsfreq_mxs,$(CONFIG_SYS_TEXT_BASE),0x40001000) - -%.sig: %.csf - $(call if_changed,mkcst_mxs) - -quiet_cmd_mkimage_mxs = MKIMAGE $@ -cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) - -u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE - $(call if_changed,mkimage_mxs) - -u-boot-signed.sb: $(src)/mxsimage-signed.cfg u-boot.ivt u-boot.sig spl/u-boot-spl.ivt spl/u-boot-spl.sig FORCE - $(call if_changed,mkimage_mxs) diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/clock.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/clock.c deleted file mode 100644 index e9d8800f8..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/clock.c +++ /dev/null @@ -1,436 +0,0 @@ -/* - * Freescale i.MX23/i.MX28 clock setup code - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/errno.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> - -/* - * The PLL frequency is 480MHz and XTAL frequency is 24MHz - * iMX23: datasheet section 4.2 - * iMX28: datasheet section 10.2 - */ -#define PLL_FREQ_KHZ 480000 -#define PLL_FREQ_COEF 18 -#define XTAL_FREQ_KHZ 24000 - -#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000) -#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000) - -#if defined(CONFIG_MX23) -#define MXC_SSPCLK_MAX MXC_SSPCLK0 -#elif defined(CONFIG_MX28) -#define MXC_SSPCLK_MAX MXC_SSPCLK3 -#endif - -static uint32_t mxs_get_pclk(void) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - - uint32_t clkctrl, clkseq, div; - uint8_t clkfrac, frac; - - clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu); - - /* No support of fractional divider calculation */ - if (clkctrl & - (CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) { - return 0; - } - - clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); - - /* XTAL Path */ - if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) { - div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >> - CLKCTRL_CPU_DIV_XTAL_OFFSET; - return XTAL_FREQ_MHZ / div; - } - - /* REF Path */ - clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); - frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; - div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK; - return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; -} - -static uint32_t mxs_get_hclk(void) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - - uint32_t div; - uint32_t clkctrl; - - clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus); - - /* No support of fractional divider calculation */ - if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN) - return 0; - - div = clkctrl & CLKCTRL_HBUS_DIV_MASK; - return mxs_get_pclk() / div; -} - -static uint32_t mxs_get_emiclk(void) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - - uint32_t clkctrl, clkseq, div; - uint8_t clkfrac, frac; - - clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); - clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi); - - /* XTAL Path */ - if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) { - div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >> - CLKCTRL_EMI_DIV_XTAL_OFFSET; - return XTAL_FREQ_MHZ / div; - } - - /* REF Path */ - clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); - frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; - div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK; - return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; -} - -static uint32_t mxs_get_gpmiclk(void) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; -#if defined(CONFIG_MX23) - uint8_t *reg = - &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]; -#elif defined(CONFIG_MX28) - uint8_t *reg = - &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]; -#endif - uint32_t clkctrl, clkseq, div; - uint8_t clkfrac, frac; - - clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); - clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi); - - /* XTAL Path */ - if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) { - div = clkctrl & CLKCTRL_GPMI_DIV_MASK; - return XTAL_FREQ_MHZ / div; - } - - /* REF Path */ - clkfrac = readb(reg); - frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; - div = clkctrl & CLKCTRL_GPMI_DIV_MASK; - return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; -} - -/* - * Set IO clock frequency, in kHz - */ -void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t div; - int io_reg; - - if (freq == 0) - return; - - if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) - return; - - div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq; - - if (div < 18) - div = 18; - - if (div > 35) - div = 35; - - io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */ - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac0_set[io_reg]); - writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK), - &clkctrl_regs->hw_clkctrl_frac0[io_reg]); - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]); -} - -/* - * Get IO clock, returns IO clock in kHz - */ -static uint32_t mxs_get_ioclk(enum mxs_ioclock io) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint8_t ret; - int io_reg; - - if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1)) - return 0; - - io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */ - - ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) & - CLKCTRL_FRAC_FRAC_MASK; - - return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret; -} - -/* - * Configure SSP clock frequency, in kHz - */ -void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t clk, clkreg; - - if (ssp > MXC_SSPCLK_MAX) - return; - - clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mxs_register_32)); - - clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE); - while (readl(clkreg) & CLKCTRL_SSP_CLKGATE) - ; - - if (xtal) - clk = XTAL_FREQ_KHZ; - else - clk = mxs_get_ioclk(ssp >> 1); - - if (freq > clk) - return; - - /* Calculate the divider and cap it if necessary */ - clk /= freq; - if (clk > CLKCTRL_SSP_DIV_MASK) - clk = CLKCTRL_SSP_DIV_MASK; - - clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk); - while (readl(clkreg) & CLKCTRL_SSP_BUSY) - ; - - if (xtal) - writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp, - &clkctrl_regs->hw_clkctrl_clkseq_set); - else - writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp, - &clkctrl_regs->hw_clkctrl_clkseq_clr); -} - -/* - * Return SSP frequency, in kHz - */ -static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t clkreg; - uint32_t clk, tmp; - - if (ssp > MXC_SSPCLK_MAX) - return 0; - - tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq); - if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp)) - return XTAL_FREQ_KHZ; - - clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp * sizeof(struct mxs_register_32)); - - tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK; - - if (tmp == 0) - return 0; - - clk = mxs_get_ioclk(ssp >> 1); - - return clk / tmp; -} - -/* - * Set SSP/MMC bus frequency, in kHz) - */ -void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq) -{ - struct mxs_ssp_regs *ssp_regs; - const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus); - const uint32_t sspclk = mxs_get_sspclk(clk); - uint32_t reg; - uint32_t divide, rate, tgtclk; - - ssp_regs = mxs_ssp_regs_by_bus(bus); - - /* - * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)), - * CLOCK_DIVIDE has to be an even value from 2 to 254, and - * CLOCK_RATE could be any integer from 0 to 255. - */ - for (divide = 2; divide < 254; divide += 2) { - rate = sspclk / freq / divide; - if (rate <= 256) - break; - } - - tgtclk = sspclk / divide / rate; - while (tgtclk > freq) { - rate++; - tgtclk = sspclk / divide / rate; - } - if (rate > 256) - rate = 256; - - /* Always set timeout the maximum */ - reg = SSP_TIMING_TIMEOUT_MASK | - (divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) | - ((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET); - writel(reg, &ssp_regs->hw_ssp_timing); - - debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n", - bus, tgtclk, freq); -} - -void mxs_set_lcdclk(uint32_t freq) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t fp, x, k_rest, k_best, x_best, tk; - int32_t k_best_l = 999, k_best_t = 0, x_best_l = 0xff, x_best_t = 0xff; - - if (freq == 0) - return; - -#if defined(CONFIG_MX23) - writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr); -#elif defined(CONFIG_MX28) - writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr); -#endif - - /* - * / 18 \ 1 1 - * freq kHz = | 480000000 Hz * -- | * --- * ------ - * \ x / k 1000 - * - * 480000000 Hz 18 - * ------------ * -- - * freq kHz x - * k = ------------------- - * 1000 - */ - - fp = ((PLL_FREQ_KHZ * 1000) / freq) * 18; - - for (x = 18; x <= 35; x++) { - tk = fp / x; - if ((tk / 1000 == 0) || (tk / 1000 > 255)) - continue; - - k_rest = tk % 1000; - - if (k_rest < (k_best_l % 1000)) { - k_best_l = tk; - x_best_l = x; - } - - if (k_rest > (k_best_t % 1000)) { - k_best_t = tk; - x_best_t = x; - } - } - - if (1000 - (k_best_t % 1000) > (k_best_l % 1000)) { - k_best = k_best_l; - x_best = x_best_l; - } else { - k_best = k_best_t; - x_best = x_best_t; - } - - k_best /= 1000; - -#if defined(CONFIG_MX23) - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]); - writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK), - &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]); - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]); - - writel(CLKCTRL_PIX_CLKGATE, - &clkctrl_regs->hw_clkctrl_pix_set); - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix, - CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE, - k_best << CLKCTRL_PIX_DIV_OFFSET); - - while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY) - ; -#elif defined(CONFIG_MX28) - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]); - writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK), - &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_PIX]); - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]); - - writel(CLKCTRL_DIS_LCDIF_CLKGATE, - &clkctrl_regs->hw_clkctrl_lcdif_set); - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif, - CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE, - k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET); - - while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY) - ; -#endif -} - -uint32_t mxc_get_clock(enum mxc_clock clk) -{ - switch (clk) { - case MXC_ARM_CLK: - return mxs_get_pclk() * 1000000; - case MXC_GPMI_CLK: - return mxs_get_gpmiclk() * 1000000; - case MXC_AHB_CLK: - case MXC_IPG_CLK: - return mxs_get_hclk() * 1000000; - case MXC_EMI_CLK: - return mxs_get_emiclk(); - case MXC_IO0_CLK: - return mxs_get_ioclk(MXC_IOCLK0); - case MXC_IO1_CLK: - return mxs_get_ioclk(MXC_IOCLK1); - case MXC_XTAL_CLK: - return XTAL_FREQ_KHZ * 1000; - case MXC_SSP0_CLK: - return mxs_get_sspclk(MXC_SSPCLK0); -#ifdef CONFIG_MX28 - case MXC_SSP1_CLK: - return mxs_get_sspclk(MXC_SSPCLK1); - case MXC_SSP2_CLK: - return mxs_get_sspclk(MXC_SSPCLK2); - case MXC_SSP3_CLK: - return mxs_get_sspclk(MXC_SSPCLK3); -#endif - } - - return 0; -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/iomux.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/iomux.c deleted file mode 100644 index 2e6be06fd..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/iomux.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/errno.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/iomux.h> -#include <asm/arch/imx-regs.h> - -#if defined(CONFIG_MX23) -#define DRIVE_OFFSET 0x200 -#define PULL_OFFSET 0x400 -#elif defined(CONFIG_MX28) -#define DRIVE_OFFSET 0x300 -#define PULL_OFFSET 0x600 -#else -#error "Please select CONFIG_MX23 or CONFIG_MX28" -#endif - -/* - * configures a single pad in the iomuxer - */ -int mxs_iomux_setup_pad(iomux_cfg_t pad) -{ - u32 reg, ofs, bp, bm; - void *iomux_base = (void *)MXS_PINCTRL_BASE; - struct mxs_register_32 *mxs_reg; - - /* muxsel */ - ofs = 0x100; - ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10; - bp = PAD_PIN(pad) % 16 * 2; - bm = 0x3 << bp; - reg = readl(iomux_base + ofs); - reg &= ~bm; - reg |= PAD_MUXSEL(pad) << bp; - writel(reg, iomux_base + ofs); - - /* drive */ - ofs = DRIVE_OFFSET; - ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10; - /* mA */ - if (PAD_MA_VALID(pad)) { - bp = PAD_PIN(pad) % 8 * 4; - bm = 0x3 << bp; - reg = readl(iomux_base + ofs); - reg &= ~bm; - reg |= PAD_MA(pad) << bp; - writel(reg, iomux_base + ofs); - } - /* vol */ - if (PAD_VOL_VALID(pad)) { - bp = PAD_PIN(pad) % 8 * 4 + 2; - mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs); - if (PAD_VOL(pad)) - writel(1 << bp, &mxs_reg->reg_set); - else - writel(1 << bp, &mxs_reg->reg_clr); - } - - /* pull */ - if (PAD_PULL_VALID(pad)) { - ofs = PULL_OFFSET; - ofs += PAD_BANK(pad) * 0x10; - bp = PAD_PIN(pad); - mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs); - if (PAD_PULL(pad)) - writel(1 << bp, &mxs_reg->reg_set); - else - writel(1 << bp, &mxs_reg->reg_clr); - } - - return 0; -} - -int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count) -{ - const iomux_cfg_t *p = pad_list; - int i; - int ret; - - for (i = 0; i < count; i++) { - ret = mxs_iomux_setup_pad(*p); - if (ret) - return ret; - p++; - } - - return 0; -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxs.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxs.c deleted file mode 100644 index 365542fe0..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Freescale i.MX23/i.MX28 common code - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/errno.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/imx-common/dma.h> -#include <asm/arch/gpio.h> -#include <asm/arch/iomux.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> -#include <linux/compiler.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* Lowlevel init isn't used on i.MX28, so just have a dummy here */ -inline void lowlevel_init(void) {} - -void reset_cpu(ulong ignored) __attribute__((noreturn)); - -void reset_cpu(ulong ignored) -{ - struct mxs_rtc_regs *rtc_regs = - (struct mxs_rtc_regs *)MXS_RTC_BASE; - struct mxs_lcdif_regs *lcdif_regs = - (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; - - /* - * Shut down the LCD controller as it interferes with BootROM boot mode - * pads sampling. - */ - writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr); - - /* Wait 1 uS before doing the actual watchdog reset */ - writel(1, &rtc_regs->hw_rtc_watchdog); - writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set); - - /* Endless loop, reset will exit from here */ - for (;;) - ; -} - -void enable_caches(void) -{ -#ifndef CONFIG_SYS_ICACHE_OFF - icache_enable(); -#endif -#ifndef CONFIG_SYS_DCACHE_OFF - dcache_enable(); -#endif -} - -/* - * This function will craft a jumptable at 0x0 which will redirect interrupt - * vectoring to proper location of U-Boot in RAM. - * - * The structure of the jumptable will be as follows: - * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times - * <destination address> ... for each previous ldr, thus also repeated 8 times - * - * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at - * offset 0x18 from current value of PC register. Note that PC is already - * incremented by 4 when computing the offset, so the effective offset is - * actually 0x20, this the associated <destination address>. Loading the PC - * register with an address performs a jump to that address. - */ -void mx28_fixup_vt(uint32_t start_addr) -{ - /* ldr pc, [pc, #0x18] */ - const uint32_t ldr_pc = 0xe59ff018; - /* Jumptable location is 0x0 */ - uint32_t *vt = (uint32_t *)0x0; - int i; - - for (i = 0; i < 8; i++) { - vt[i] = ldr_pc; - vt[i + 8] = start_addr + (4 * i); - } -} - -#ifdef CONFIG_ARCH_MISC_INIT -int arch_misc_init(void) -{ - mx28_fixup_vt(gd->relocaddr); - return 0; -} -#endif - -int arch_cpu_init(void) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - extern uint32_t _start; - - mx28_fixup_vt((uint32_t)&_start); - - /* - * Enable NAND clock - */ - /* Clear bypass bit */ - writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, - &clkctrl_regs->hw_clkctrl_clkseq_set); - - /* Set GPMI clock to ref_gpmi / 12 */ - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, - CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1); - - udelay(1000); - - /* - * Configure GPIO unit - */ - mxs_gpio_init(); - -#ifdef CONFIG_APBH_DMA - /* Start APBH DMA */ - mxs_dma_init(); -#endif - - return 0; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -static const char *get_cpu_type(void) -{ - struct mxs_digctl_regs *digctl_regs = - (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; - - switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) { - case HW_DIGCTL_CHIPID_MX23: - return "23"; - case HW_DIGCTL_CHIPID_MX28: - return "28"; - default: - return "??"; - } -} - -static const char *get_cpu_rev(void) -{ - struct mxs_digctl_regs *digctl_regs = - (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; - uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF; - - switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) { - case HW_DIGCTL_CHIPID_MX23: - switch (rev) { - case 0x0: - return "1.0"; - case 0x1: - return "1.1"; - case 0x2: - return "1.2"; - case 0x3: - return "1.3"; - case 0x4: - return "1.4"; - default: - return "??"; - } - case HW_DIGCTL_CHIPID_MX28: - switch (rev) { - case 0x1: - return "1.2"; - default: - return "??"; - } - default: - return "??"; - } -} - -int print_cpuinfo(void) -{ - struct mxs_spl_data *data = (struct mxs_spl_data *) - ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); - - printf("CPU: Freescale i.MX%s rev%s at %d MHz\n", - get_cpu_type(), - get_cpu_rev(), - mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode); - return 0; -} -#endif - -int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -{ - printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); - printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000); - printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK)); - printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000); - return 0; -} - -/* - * Initializes on-chip ethernet controllers. - */ -#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET) -int cpu_eth_init(bd_t *bis) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - - /* Turn on ENET clocks */ - clrbits_le32(&clkctrl_regs->hw_clkctrl_enet, - CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE); - - /* Set up ENET PLL for 50 MHz */ - /* Power on ENET PLL */ - writel(CLKCTRL_PLL2CTRL0_POWER, - &clkctrl_regs->hw_clkctrl_pll2ctrl0_set); - - udelay(10); - - /* Gate on ENET PLL */ - writel(CLKCTRL_PLL2CTRL0_CLKGATE, - &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr); - - /* Enable pad output */ - setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN); - - return 0; -} -#endif - -__weak void mx28_adjust_mac(int dev_id, unsigned char *mac) -{ - mac[0] = 0x00; - mac[1] = 0x04; /* Use FSL vendor MAC address by default */ - - if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */ - mac[5] += 1; -} - -#ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP - -#define MXS_OCOTP_MAX_TIMEOUT 1000000 -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) -{ - struct mxs_ocotp_regs *ocotp_regs = - (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; - uint32_t data; - - memset(mac, 0, 6); - - writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); - - if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, - MXS_OCOTP_MAX_TIMEOUT)) { - printf("MXS FEC: Can't get MAC from OCOTP\n"); - return; - } - - data = readl(&ocotp_regs->hw_ocotp_cust0); - - mac[2] = (data >> 24) & 0xff; - mac[3] = (data >> 16) & 0xff; - mac[4] = (data >> 8) & 0xff; - mac[5] = data & 0xff; - mx28_adjust_mac(dev_id, mac); -} -#else -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) -{ - memset(mac, 0, 6); -} -#endif - -int mxs_dram_init(void) -{ - struct mxs_spl_data *data = (struct mxs_spl_data *) - ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); - - if (data->mem_dram_size == 0) { - printf("MXS:\n" - "Error, the RAM size passed up from SPL is 0!\n"); - hang(); - } - - gd->ram_size = data->mem_dram_size; - return 0; -} - -U_BOOT_CMD( - clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks, - "display clocks", - "" -); diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxs_init.h b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxs_init.h deleted file mode 100644 index 1200ae1ad..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxs_init.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Freescale i.MX28 SPL functions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __M28_INIT_H__ -#define __M28_INIT_H__ - -void early_delay(int delay); - -void mxs_power_init(void); - -#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT -void mxs_power_wait_pswitch(void); -#else -static inline void mxs_power_wait_pswitch(void) { } -#endif - -void mxs_mem_init(void); -uint32_t mxs_mem_get_size(void); - -void mxs_lradc_init(void); -void mxs_lradc_enable_batt_measurement(void); - -#endif /* __M28_INIT_H__ */ diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg deleted file mode 100644 index 1520bba3f..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg +++ /dev/null @@ -1,10 +0,0 @@ -SECTION 0x0 BOOTABLE - TAG LAST - LOAD 0x1000 spl/u-boot-spl.bin - LOAD 0x8000 spl/u-boot-spl.ivt - LOAD 0x8040 spl/u-boot-spl.sig - CALL HAB 0x8000 0x0 - LOAD 0x40002000 u-boot.bin - LOAD 0x40001000 u-boot.ivt - LOAD 0x40001040 u-boot.sig - CALL HAB 0x40001000 0x0 diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg deleted file mode 100644 index 55510e9cd..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ /dev/null @@ -1,6 +0,0 @@ -SECTION 0x0 BOOTABLE - TAG LAST - LOAD 0x1000 spl/u-boot-spl.bin - CALL 0x1000 0x0 - LOAD 0x40002000 u-boot.bin - CALL 0x40002000 0x0 diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg deleted file mode 100644 index bb78cb0c8..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg +++ /dev/null @@ -1,8 +0,0 @@ -SECTION 0x0 BOOTABLE - TAG LAST - LOAD 0x1000 spl/u-boot-spl.bin - LOAD IVT 0x8000 0x1000 - CALL HAB 0x8000 0x0 - LOAD 0x40002000 u-boot.bin - LOAD IVT 0x8000 0x40002000 - CALL HAB 0x8000 0x0 diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_boot.c deleted file mode 100644 index d3e136991..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Freescale i.MX28 Boot setup - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <linux/compiler.h> - -#include "mxs_init.h" - -DECLARE_GLOBAL_DATA_PTR; -static gd_t gdata __section(".data"); -#ifdef CONFIG_SPL_SERIAL_SUPPORT -static bd_t bdata __section(".data"); -#endif - -/* - * This delay function is intended to be used only in early stage of boot, where - * clock are not set up yet. The timer used here is reset on every boot and - * takes a few seconds to roll. The boot doesn't take that long, so to keep the - * code simple, it doesn't take rolling into consideration. - */ -void early_delay(int delay) -{ - struct mxs_digctl_regs *digctl_regs = - (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; - - uint32_t st = readl(&digctl_regs->hw_digctl_microseconds); - st += delay; - while (st > readl(&digctl_regs->hw_digctl_microseconds)) - ; -} - -#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -static const iomux_cfg_t iomux_boot[] = { -#if defined(CONFIG_MX23) - MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, - MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, - MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, - MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, - MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, - MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, -#elif defined(CONFIG_MX28) - MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, -#endif -}; - -static uint8_t mxs_get_bootmode_index(void) -{ - uint8_t bootmode = 0; - int i; - uint8_t masked; - - /* Setup IOMUX of bootmode pads to GPIO */ - mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot)); - -#if defined(CONFIG_MX23) - /* Setup bootmode pins as GPIO input */ - gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0); - gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1); - gpio_direction_input(MX23_PAD_LCD_D02__GPIO_1_2); - gpio_direction_input(MX23_PAD_LCD_D03__GPIO_1_3); - gpio_direction_input(MX23_PAD_LCD_D05__GPIO_1_5); - - /* Read bootmode pads */ - bootmode |= (gpio_get_value(MX23_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0; - bootmode |= (gpio_get_value(MX23_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1; - bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2; - bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; - bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; -#elif defined(CONFIG_MX28) - /* Setup bootmode pins as GPIO input */ - gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0); - gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1); - gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2); - gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3); - gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4); - gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5); - - /* Read bootmode pads */ - bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; -#endif - - for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) { - masked = bootmode & mxs_boot_modes[i].boot_mask; - if (masked == mxs_boot_modes[i].boot_pads) - break; - } - - return i; -} - -static void mxs_spl_fixup_vectors(void) -{ - /* - * Copy our vector table to 0x0, since due to HAB, we cannot - * be loaded to 0x0. We want to have working vectoring though, - * thus this fixup. Our vectoring table is PIC, so copying is - * fine. - */ - extern uint32_t _start; - memcpy(0x0, &_start, 0x60); -} - -static void mxs_spl_console_init(void) -{ -#ifdef CONFIG_SPL_SERIAL_SUPPORT - gd->bd = &bdata; - gd->baudrate = CONFIG_BAUDRATE; - serial_init(); - gd->have_console = 1; -#endif -} - -void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, - const iomux_cfg_t *iomux_setup, - const unsigned int iomux_size) -{ - struct mxs_spl_data *data = (struct mxs_spl_data *) - ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); - uint8_t bootmode = mxs_get_bootmode_index(); - gd = &gdata; - - mxs_spl_fixup_vectors(); - - mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); - - mxs_spl_console_init(); - - mxs_power_init(); - - mxs_mem_init(); - data->mem_dram_size = mxs_mem_get_size(); - - data->boot_mode_idx = bootmode; - - mxs_power_wait_pswitch(); -} - -/* Support aparatus */ -inline void board_init_f(unsigned long bootflag) -{ - for (;;) - ; -} - -inline void board_init_r(gd_t *id, ulong dest_addr) -{ - for (;;) - ; -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c deleted file mode 100644 index cdfcddd82..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Freescale i.MX28 Battery measurement init - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> - -#include "mxs_init.h" - -void mxs_lradc_init(void) -{ - struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE; - - writel(LRADC_CTRL0_SFTRST, ®s->hw_lradc_ctrl0_clr); - writel(LRADC_CTRL0_CLKGATE, ®s->hw_lradc_ctrl0_clr); - writel(LRADC_CTRL0_ONCHIP_GROUNDREF, ®s->hw_lradc_ctrl0_clr); - - clrsetbits_le32(®s->hw_lradc_ctrl3, - LRADC_CTRL3_CYCLE_TIME_MASK, - LRADC_CTRL3_CYCLE_TIME_6MHZ); - - clrsetbits_le32(®s->hw_lradc_ctrl4, - LRADC_CTRL4_LRADC7SELECT_MASK | - LRADC_CTRL4_LRADC6SELECT_MASK, - LRADC_CTRL4_LRADC7SELECT_CHANNEL7 | - LRADC_CTRL4_LRADC6SELECT_CHANNEL10); -} - -void mxs_lradc_enable_batt_measurement(void) -{ - struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE; - - /* Check if the channel is present at all. */ - if (!(readl(®s->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) - return; - - writel(LRADC_CTRL1_LRADC7_IRQ_EN, ®s->hw_lradc_ctrl1_clr); - writel(LRADC_CTRL1_LRADC7_IRQ, ®s->hw_lradc_ctrl1_clr); - - clrsetbits_le32(®s->hw_lradc_conversion, - LRADC_CONVERSION_SCALE_FACTOR_MASK, - LRADC_CONVERSION_SCALE_FACTOR_LI_ION); - writel(LRADC_CONVERSION_AUTOMATIC, ®s->hw_lradc_conversion_set); - - /* Configure the channel. */ - writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, - ®s->hw_lradc_ctrl2_clr); - writel(0xffffffff, ®s->hw_lradc_ch7_clr); - clrbits_le32(®s->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK); - writel(LRADC_CH_ACCUMULATE, ®s->hw_lradc_ch7_clr); - - /* Schedule the channel. */ - writel(1 << 7, ®s->hw_lradc_ctrl0_set); - - /* Start the channel sampling. */ - writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) | - ((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) | - 100, ®s->hw_lradc_delay3); - - writel(0xffffffff, ®s->hw_lradc_ch7_clr); - - writel(LRADC_DELAY_KICK, ®s->hw_lradc_delay3_set); -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c deleted file mode 100644 index 3baf4ddef..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Freescale i.MX28 RAM init - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> -#include <linux/compiler.h> - -#include "mxs_init.h" - -static uint32_t dram_vals[] = { -/* - * i.MX28 DDR2 at 200MHz - */ -#if defined(CONFIG_MX28) - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000100, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00010101, 0x01010101, - 0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101, - 0x00000100, 0x00000100, 0x00000000, 0x00000002, - 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8, - 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612, - 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, - 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, - 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, - 0x00000003, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000612, 0x01000F02, - 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, - 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07000300, - 0x07000300, 0x07400300, 0x07400300, 0x00000005, - 0x00000000, 0x00000000, 0x01000000, 0x01020408, - 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, - 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, - 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00010000, 0x00030404, - 0x00000003, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x01010000, - 0x01000000, 0x03030000, 0x00010303, 0x01020202, - 0x00000000, 0x02040303, 0x21002103, 0x00061200, - 0x06120612, 0x04420442, 0x04420442, 0x00040004, - 0x00040004, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0xffffffff - -/* - * i.MX23 DDR at 133MHz - */ -#elif defined(CONFIG_MX23) - 0x01010001, 0x00010100, 0x01000101, 0x00000001, - 0x00000101, 0x00000000, 0x00010000, 0x01000001, - 0x00000000, 0x00000001, 0x07000200, 0x00070202, - 0x02020000, 0x04040a01, 0x00000201, 0x02040000, - 0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313, - 0x02061521, 0x0000000a, 0x00080008, 0x00200020, - 0x00200020, 0x00200020, 0x000003f7, 0x00000000, - 0x00000000, 0x00000020, 0x00000020, 0x00c80000, - 0x000a23cd, 0x000000c8, 0x00006665, 0x00000000, - 0x00000101, 0x00040001, 0x00000000, 0x00000000, - 0x00010000 -#else -#error Unsupported memory initialization -#endif -}; - -__weak void mxs_adjust_memory_params(uint32_t *dram_vals) -{ -} - -#ifdef CONFIG_MX28 -static void initialize_dram_values(void) -{ - int i; - - mxs_adjust_memory_params(dram_vals); - - for (i = 0; i < ARRAY_SIZE(dram_vals); i++) - writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); -} -#else -static void initialize_dram_values(void) -{ - int i; - - mxs_adjust_memory_params(dram_vals); - - /* - * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as - * per FSL bootlets code. - * - * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as - * "reserved". - * HW_DRAM_CTL8 is setup as the last element. - * So skip the initialization of these HW_DRAM_CTL registers. - */ - for (i = 0; i < ARRAY_SIZE(dram_vals); i++) { - if (i == 8 || i == 27 || i == 28 || i == 35) - continue; - writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); - } - - /* - * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last - * element to be set - */ - writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); -} -#endif - -static void mxs_mem_init_clock(void) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; -#if defined(CONFIG_MX23) - /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */ - const unsigned char divider = 33; -#elif defined(CONFIG_MX28) - /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */ - const unsigned char divider = 21; -#endif - - /* Gate EMI clock */ - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]); - - /* Set fractional divider for ref_emi */ - writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), - &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); - - /* Ungate EMI clock */ - writeb(CLKCTRL_FRAC_CLKGATE, - &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); - - early_delay(11000); - - /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ - writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | - (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), - &clkctrl_regs->hw_clkctrl_emi); - - /* Unbypass EMI */ - writel(CLKCTRL_CLKSEQ_BYPASS_EMI, - &clkctrl_regs->hw_clkctrl_clkseq_clr); - - early_delay(10000); -} - -static void mxs_mem_setup_cpu_and_hbus(void) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - - /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz - * and ungate CPU clock */ - writeb(19 & CLKCTRL_FRAC_FRAC_MASK, - (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); - - /* Set CPU bypass */ - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_set); - - /* HBUS = 151MHz */ - writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); - writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, - &clkctrl_regs->hw_clkctrl_hbus_clr); - - early_delay(10000); - - /* CPU clock divider = 1 */ - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, - CLKCTRL_CPU_DIV_CPU_MASK, 1); - - /* Disable CPU bypass */ - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_clr); - - early_delay(15000); -} - -static void mxs_mem_setup_vdda(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | - (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | - POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, - &power_regs->hw_power_vddactrl); -} - -uint32_t mxs_mem_get_size(void) -{ - uint32_t sz, da; - uint32_t *vt = (uint32_t *)0x20; - /* The following is "subs pc, r14, #4", used as return from DABT. */ - const uint32_t data_abort_memdetect_handler = 0xe25ef004; - - /* Replace the DABT handler. */ - da = vt[4]; - vt[4] = data_abort_memdetect_handler; - - sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - - /* Restore the old DABT handler. */ - vt[4] = da; - - return sz; -} - -#ifdef CONFIG_MX23 -static void mx23_mem_setup_vddmem(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - clrbits_le32(&power_regs->hw_power_vddmemctrl, - POWER_VDDMEMCTRL_ENABLE_ILIMIT); - -} - -static void mx23_mem_init(void) -{ - /* - * Reset/ungate the EMI block. This is essential, otherwise the system - * suffers from memory instability. This thing is mx23 specific and is - * no longer present on mx28. - */ - mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE); - - mx23_mem_setup_vddmem(); - - /* - * Configure the DRAM registers - */ - - /* Clear START and SREFRESH bit from DRAM_CTL8 */ - clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); - - initialize_dram_values(); - - /* Set START bit in DRAM_CTL8 */ - setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); - - clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); - early_delay(20000); - - /* Adjust EMI port priority. */ - clrsetbits_le32(0x80020000, 0x1f << 16, 0x2); - early_delay(20000); - - setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); - setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); -} -#endif - -#ifdef CONFIG_MX28 -static void mx28_mem_init(void) -{ - struct mxs_pinctrl_regs *pinctrl_regs = - (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; - - /* Set DDR2 mode */ - writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, - &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); - - /* - * Configure the DRAM registers - */ - - /* Clear START bit from DRAM_CTL16 */ - clrbits_le32(MXS_DRAM_BASE + 0x40, 1); - - initialize_dram_values(); - - /* Clear SREFRESH bit from DRAM_CTL17 */ - clrbits_le32(MXS_DRAM_BASE + 0x44, 1); - - /* Set START bit in DRAM_CTL16 */ - setbits_le32(MXS_DRAM_BASE + 0x40, 1); - - /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ - while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) - ; -} -#endif - -void mxs_mem_init(void) -{ - early_delay(11000); - - mxs_mem_init_clock(); - - mxs_mem_setup_vdda(); - -#if defined(CONFIG_MX23) - mx23_mem_init(); -#elif defined(CONFIG_MX28) - mx28_mem_init(); -#endif - - early_delay(10000); - - mxs_mem_setup_cpu_and_hbus(); -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c deleted file mode 100644 index d25019a51..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ /dev/null @@ -1,1155 +0,0 @@ -/* - * Freescale i.MX28 Boot PMIC init - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> - -#include "mxs_init.h" - -/** - * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL - * - * This function switches the CPU core clock from PLL to 24MHz XTAL - * oscilator. This is necessary if the PLL is being reconfigured to - * prevent crash of the CPU core. - */ -static void mxs_power_clock2xtal(void) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - - /* Set XTAL as CPU reference clock */ - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_set); -} - -/** - * mxs_power_clock2pll() - Switch CPU core clock source to PLL - * - * This function switches the CPU core clock from 24MHz XTAL oscilator - * to PLL. This can only be called once the PLL has re-locked and once - * the PLL is stable after reconfiguration. - */ -static void mxs_power_clock2pll(void) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - - setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0, - CLKCTRL_PLL0CTRL0_POWER); - early_delay(100); - setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, - CLKCTRL_CLKSEQ_BYPASS_CPU); -} - -/** - * mxs_power_set_auto_restart() - Set the auto-restart bit - * - * This function ungates the RTC block and sets the AUTO_RESTART - * bit to work around a design bug on MX28EVK Rev. A . - */ - -static void mxs_power_set_auto_restart(void) -{ - struct mxs_rtc_regs *rtc_regs = - (struct mxs_rtc_regs *)MXS_RTC_BASE; - - writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr); - while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST) - ; - - writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr); - while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE) - ; - - /* Do nothing if flag already set */ - if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) - return; - - while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) - ; - - setbits_le32(&rtc_regs->hw_rtc_persistent0, - RTC_PERSISTENT0_AUTO_RESTART); - writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set); - writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr); - while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) - ; - while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK) - ; -} - -/** - * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter - * - * This function configures the VDDIO, VDDA and VDDD linear regulators output - * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching - * converter. This is the recommended setting for the case where we use both - * linear regulators and DC-DC converter to power the VDDIO rail. - */ -static void mxs_power_set_linreg(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - /* Set linear regulator 25mV below switching converter */ - clrsetbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_LINREG_OFFSET_MASK, - POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); - - clrsetbits_le32(&power_regs->hw_power_vddactrl, - POWER_VDDACTRL_LINREG_OFFSET_MASK, - POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW); - - clrsetbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_LINREG_OFFSET_MASK, - POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); -} - -/** - * mxs_get_batt_volt() - Measure battery input voltage - * - * This function retrieves the battery input voltage and returns it. - */ -static int mxs_get_batt_volt(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - uint32_t volt = readl(&power_regs->hw_power_battmonitor); - volt &= POWER_BATTMONITOR_BATT_VAL_MASK; - volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; - volt *= 8; - return volt; -} - -/** - * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot - * - * This function checks if the battery input voltage is higher than 3.6V and - * therefore allows the system to successfully boot using this power source. - */ -static int mxs_is_batt_ready(void) -{ - return (mxs_get_batt_volt() >= 3600); -} - -/** - * mxs_is_batt_good() - Test if battery is operational at all - * - * This function starts recharging the battery and tests if the input current - * provided by the 5V input recharging the battery is also sufficient to power - * the DC-DC converter. - */ -static int mxs_is_batt_good(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - uint32_t volt = mxs_get_batt_volt(); - - if ((volt >= 2400) && (volt <= 4300)) - return 1; - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, - 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, - &power_regs->hw_power_5vctrl_clr); - - clrsetbits_le32(&power_regs->hw_power_charge, - POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, - POWER_CHARGE_STOP_ILIMIT_10MA | 0x3); - - writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr); - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, - &power_regs->hw_power_5vctrl_clr); - - early_delay(500000); - - volt = mxs_get_batt_volt(); - - if (volt >= 3500) - return 0; - - if (volt >= 2400) - return 1; - - writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, - &power_regs->hw_power_charge_clr); - writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); - - return 0; -} - -/** - * mxs_power_setup_5v_detect() - Start the 5V input detection comparator - * - * This function enables the 5V detection comparator and sets the 5V valid - * threshold to 4.4V . We use 4.4V threshold here to make sure that even - * under high load, the voltage drop on the 5V input won't be so critical - * to cause undervolt on the 4P2 linear regulator supplying the DC-DC - * converter and thus making the system crash. - */ -static void mxs_power_setup_5v_detect(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - /* Start 5V detection */ - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_VBUSVALID_TRSH_MASK, - POWER_5VCTRL_VBUSVALID_TRSH_4V4 | - POWER_5VCTRL_PWRUP_VBUS_CMPS); -} - -/** - * mxs_src_power_init() - Preconfigure the power block - * - * This function configures reasonable values for the DC-DC control loop - * and battery monitor. - */ -static void mxs_src_power_init(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - /* Improve efficieny and reduce transient ripple */ - writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST | - POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set); - - clrsetbits_le32(&power_regs->hw_power_dclimits, - POWER_DCLIMITS_POSLIMIT_BUCK_MASK, - 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET); - - setbits_le32(&power_regs->hw_power_battmonitor, - POWER_BATTMONITOR_EN_BATADJ); - - /* Increase the RCSCALE level for quick DCDC response to dynamic load */ - clrsetbits_le32(&power_regs->hw_power_loopctrl, - POWER_LOOPCTRL_EN_RCSCALE_MASK, - POWER_LOOPCTRL_RCSCALE_THRESH | - POWER_LOOPCTRL_EN_RCSCALE_8X); - - clrsetbits_le32(&power_regs->hw_power_minpwr, - POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); - - /* 5V to battery handoff ... FIXME */ - setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); - early_delay(30); - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); -} - -/** - * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator - * - * This function configures the necessary parameters for the 4P2 linear - * regulator to supply the DC-DC converter from 5V input. - */ -static void mxs_power_init_4p2_params(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - /* Setup 4P2 parameters */ - clrsetbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK, - POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET)); - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_HEADROOM_ADJ_MASK, - 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET); - - clrsetbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_DROPOUT_CTRL_MASK, - POWER_DCDC4P2_DROPOUT_CTRL_100MV | - POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL); - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, - 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); -} - -/** - * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2 - * @xfer: Select if the input shall be enabled or disabled - * - * This function enables or disables the 4P2 input into the DC-DC converter. - */ -static void mxs_enable_4p2_dcdc_input(int xfer) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo; - uint32_t prev_5v_brnout, prev_5v_droop; - - prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_PWDN_5VBRNOUT; - prev_5v_droop = readl(&power_regs->hw_power_ctrl) & - POWER_CTRL_ENIRQ_VDD5V_DROOP; - - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); - writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, - &power_regs->hw_power_reset); - - clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); - - if (xfer && (readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_ENABLE_DCDC)) { - return; - } - - /* - * Recording orignal values that will be modified temporarlily - * to handle a chip bug. See chip errata for CQ ENGR00115837 - */ - tmp = readl(&power_regs->hw_power_5vctrl); - vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK; - vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT; - - pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO; - - /* - * Disable mechanisms that get erroneously tripped by when setting - * the DCDC4P2 EN_DCDC - */ - clrbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_VBUSVALID_5VDETECT | - POWER_5VCTRL_VBUSVALID_TRSH_MASK); - - writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set); - - if (xfer) { - setbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_DCDC_XFER); - early_delay(20); - clrbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_DCDC_XFER); - - setbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_ENABLE_DCDC); - } else { - setbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_ENABLE_DCDC); - } - - early_delay(25); - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh); - - if (vbus_5vdetect) - writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set); - - if (!pwd_bo) - clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO); - - while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) - writel(POWER_CTRL_VBUS_VALID_IRQ, - &power_regs->hw_power_ctrl_clr); - - if (prev_5v_brnout) { - writel(POWER_5VCTRL_PWDN_5VBRNOUT, - &power_regs->hw_power_5vctrl_set); - writel(POWER_RESET_UNLOCK_KEY, - &power_regs->hw_power_reset); - } else { - writel(POWER_5VCTRL_PWDN_5VBRNOUT, - &power_regs->hw_power_5vctrl_clr); - writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, - &power_regs->hw_power_reset); - } - - while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ) - writel(POWER_CTRL_VDD5V_DROOP_IRQ, - &power_regs->hw_power_ctrl_clr); - - if (prev_5v_droop) - clrbits_le32(&power_regs->hw_power_ctrl, - POWER_CTRL_ENIRQ_VDD5V_DROOP); - else - setbits_le32(&power_regs->hw_power_ctrl, - POWER_CTRL_ENIRQ_VDD5V_DROOP); -} - -/** - * mxs_power_init_4p2_regulator() - Start the 4P2 regulator - * - * This function enables the 4P2 regulator and switches the DC-DC converter - * to use the 4P2 input. - */ -static void mxs_power_init_4p2_regulator(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - uint32_t tmp, tmp2; - - setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2); - - writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set); - - writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, - &power_regs->hw_power_5vctrl_clr); - clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK); - - /* Power up the 4p2 rail and logic/control */ - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, - &power_regs->hw_power_5vctrl_clr); - - /* - * Start charging up the 4p2 capacitor. We ramp of this charge - * gradually to avoid large inrush current from the 5V cable which can - * cause transients/problems - */ - mxs_enable_4p2_dcdc_input(0); - - if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { - /* - * If we arrived here, we were unable to recover from mx23 chip - * errata 5837. 4P2 is disabled and sufficient battery power is - * not present. Exiting to not enable DCDC power during 5V - * connected state. - */ - clrbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_ENABLE_DCDC); - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, - &power_regs->hw_power_5vctrl_set); - hang(); - } - - /* - * Here we set the 4p2 brownout level to something very close to 4.2V. - * We then check the brownout status. If the brownout status is false, - * the voltage is already close to the target voltage of 4.2V so we - * can go ahead and set the 4P2 current limit to our max target limit. - * If the brownout status is true, we need to ramp us the current limit - * so that we don't cause large inrush current issues. We step up the - * current limit until the brownout status is false or until we've - * reached our maximum defined 4p2 current limit. - */ - clrsetbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_BO_MASK, - 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */ - - if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) { - setbits_le32(&power_regs->hw_power_5vctrl, - 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); - } else { - tmp = (readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >> - POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; - while (tmp < 0x3f) { - if (!(readl(&power_regs->hw_power_sts) & - POWER_STS_DCDC_4P2_BO)) { - tmp = readl(&power_regs->hw_power_5vctrl); - tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; - early_delay(100); - writel(tmp, &power_regs->hw_power_5vctrl); - break; - } else { - tmp++; - tmp2 = readl(&power_regs->hw_power_5vctrl); - tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; - tmp2 |= tmp << - POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; - writel(tmp2, &power_regs->hw_power_5vctrl); - early_delay(100); - } - } - } - - clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); - writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); -} - -/** - * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source - * - * This function configures the DC-DC converter to be supplied from the 4P2 - * linear regulator. - */ -static void mxs_power_init_dcdc_4p2_source(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - if (!(readl(&power_regs->hw_power_dcdc4p2) & - POWER_DCDC4P2_ENABLE_DCDC)) { - hang(); - } - - mxs_enable_4p2_dcdc_input(1); - - if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { - clrbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_ENABLE_DCDC); - writel(POWER_5VCTRL_ENABLE_DCDC, - &power_regs->hw_power_5vctrl_clr); - writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, - &power_regs->hw_power_5vctrl_set); - } -} - -/** - * mxs_power_enable_4p2() - Power up the 4P2 regulator - * - * This function drives the process of powering up the 4P2 linear regulator - * and switching the DC-DC converter input over to the 4P2 linear regulator. - */ -static void mxs_power_enable_4p2(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - uint32_t vdddctrl, vddactrl, vddioctrl; - uint32_t tmp; - - vdddctrl = readl(&power_regs->hw_power_vdddctrl); - vddactrl = readl(&power_regs->hw_power_vddactrl); - vddioctrl = readl(&power_regs->hw_power_vddioctrl); - - setbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | - POWER_VDDDCTRL_PWDN_BRNOUT); - - setbits_le32(&power_regs->hw_power_vddactrl, - POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG | - POWER_VDDACTRL_PWDN_BRNOUT); - - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); - - mxs_power_init_4p2_params(); - mxs_power_init_4p2_regulator(); - - /* Shutdown battery (none present) */ - if (!mxs_is_batt_ready()) { - clrbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_BO_MASK); - writel(POWER_CTRL_DCDC4P2_BO_IRQ, - &power_regs->hw_power_ctrl_clr); - writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, - &power_regs->hw_power_ctrl_clr); - } - - mxs_power_init_dcdc_4p2_source(); - - writel(vdddctrl, &power_regs->hw_power_vdddctrl); - early_delay(20); - writel(vddactrl, &power_regs->hw_power_vddactrl); - early_delay(20); - writel(vddioctrl, &power_regs->hw_power_vddioctrl); - - /* - * Check if FET is enabled on either powerout and if so, - * disable load. - */ - tmp = 0; - tmp |= !(readl(&power_regs->hw_power_vdddctrl) & - POWER_VDDDCTRL_DISABLE_FET); - tmp |= !(readl(&power_regs->hw_power_vddactrl) & - POWER_VDDACTRL_DISABLE_FET); - tmp |= !(readl(&power_regs->hw_power_vddioctrl) & - POWER_VDDIOCTRL_DISABLE_FET); - if (tmp) - writel(POWER_CHARGE_ENABLE_LOAD, - &power_regs->hw_power_charge_clr); -} - -/** - * mxs_boot_valid_5v() - Boot from 5V supply - * - * This function configures the power block to boot from valid 5V input. - * This is called only if the 5V is reliable and can properly supply the - * CPU. This function proceeds to configure the 4P2 converter to be supplied - * from the 5V input. - */ -static void mxs_boot_valid_5v(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - /* - * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V - * disconnect event. FIXME - */ - writel(POWER_5VCTRL_VBUSVALID_5VDETECT, - &power_regs->hw_power_5vctrl_set); - - /* Configure polarity to check for 5V disconnection. */ - writel(POWER_CTRL_POLARITY_VBUSVALID | - POWER_CTRL_POLARITY_VDD5V_GT_VDDIO, - &power_regs->hw_power_ctrl_clr); - - writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ, - &power_regs->hw_power_ctrl_clr); - - mxs_power_enable_4p2(); -} - -/** - * mxs_powerdown() - Shut down the system - * - * This function powers down the CPU completely. - */ -static void mxs_powerdown(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset); - writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, - &power_regs->hw_power_reset); -} - -/** - * mxs_batt_boot() - Configure the power block to boot from battery input - * - * This function configures the power block to boot from the battery voltage - * supply. - */ -static void mxs_batt_boot(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC); - - clrbits_le32(&power_regs->hw_power_dcdc4p2, - POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2); - writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr); - - /* 5V to battery handoff. */ - setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); - early_delay(30); - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); - - writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr); - - clrsetbits_le32(&power_regs->hw_power_minpwr, - POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); - - mxs_power_set_linreg(); - - clrbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG); - - clrbits_le32(&power_regs->hw_power_vddactrl, - POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG); - - clrbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_DISABLE_FET); - - setbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_PWD_CHARGE_4P2_MASK); - - setbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_ENABLE_DCDC); - - clrsetbits_le32(&power_regs->hw_power_5vctrl, - POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, - 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); - - mxs_power_enable_4p2(); -} - -/** - * mxs_handle_5v_conflict() - Test if the 5V input is reliable - * - * This function tests if the 5V input can reliably supply the system. If it - * can, then proceed to configuring the system to boot from 5V source, otherwise - * try booting from battery supply. If we can not boot from battery supply - * either, shut down the system. - */ -static void mxs_handle_5v_conflict(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - uint32_t tmp; - - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_BO_OFFSET_MASK); - - for (;;) { - tmp = readl(&power_regs->hw_power_sts); - - if (tmp & POWER_STS_VDDIO_BO) { - /* - * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes - * unreliable - */ - mxs_powerdown(); - break; - } - - if (tmp & POWER_STS_VDD5V_GT_VDDIO) { - mxs_boot_valid_5v(); - break; - } else { - mxs_powerdown(); - break; - } - - if (tmp & POWER_STS_PSWITCH_MASK) { - mxs_batt_boot(); - break; - } - } -} - -/** - * mxs_5v_boot() - Configure the power block to boot from 5V input - * - * This function handles configuration of the power block when supplied by - * a 5V input. - */ -static void mxs_5v_boot(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - /* - * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID, - * but their implementation always returns 1 so we omit it here. - */ - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - mxs_boot_valid_5v(); - return; - } - - early_delay(1000); - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - mxs_boot_valid_5v(); - return; - } - - mxs_handle_5v_conflict(); -} - -/** - * mxs_init_batt_bo() - Configure battery brownout threshold - * - * This function configures the battery input brownout threshold. The value - * at which the battery brownout happens is configured to 3.0V in the code. - */ -static void mxs_init_batt_bo(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - /* Brownout at 3V */ - clrsetbits_le32(&power_regs->hw_power_battmonitor, - POWER_BATTMONITOR_BRWNOUT_LVL_MASK, - 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET); - - writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr); - writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); -} - -/** - * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter - * - * This function turns off the VDDD linear regulator and therefore makes - * the VDDD rail be supplied only by the DC-DC converter. - */ -static void mxs_switch_vddd_to_dcdc_source(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - clrsetbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_LINREG_OFFSET_MASK, - POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); - - clrbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | - POWER_VDDDCTRL_DISABLE_STEPPING); -} - -/** - * mxs_power_configure_power_source() - Configure power block source - * - * This function is the core of the power configuration logic. The function - * selects the power block input source and configures the whole power block - * accordingly. After the configuration is complete and the system is stable - * again, the function switches the CPU clock source back to PLL. Finally, - * the function switches the voltage rails to DC-DC converter. - */ -static void mxs_power_configure_power_source(void) -{ - int batt_ready, batt_good; - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - struct mxs_lradc_regs *lradc_regs = - (struct mxs_lradc_regs *)MXS_LRADC_BASE; - - mxs_src_power_init(); - - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - batt_ready = mxs_is_batt_ready(); - if (batt_ready) { - /* 5V source detected, good battery detected. */ - mxs_batt_boot(); - } else { - batt_good = mxs_is_batt_good(); - if (!batt_good) { - /* 5V source detected, bad battery detected. */ - writel(LRADC_CONVERSION_AUTOMATIC, - &lradc_regs->hw_lradc_conversion_clr); - clrbits_le32(&power_regs->hw_power_battmonitor, - POWER_BATTMONITOR_BATT_VAL_MASK); - } - mxs_5v_boot(); - } - } else { - /* 5V not detected, booting from battery. */ - mxs_batt_boot(); - } - - mxs_power_clock2pll(); - - mxs_init_batt_bo(); - - mxs_switch_vddd_to_dcdc_source(); - -#ifdef CONFIG_MX23 - /* Fire up the VDDMEM LinReg now that we're all set. */ - writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT, - &power_regs->hw_power_vddmemctrl); -#endif -} - -/** - * mxs_enable_output_rail_protection() - Enable power rail protection - * - * This function enables overload protection on the power rails. This is - * triggered if the power rails' voltage drops rapidly due to overload and - * in such case, the supply to the powerrail is cut-off, protecting the - * CPU from damage. Note that under such condition, the system will likely - * crash or misbehave. - */ -static void mxs_enable_output_rail_protection(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | - POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr); - - setbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_PWDN_BRNOUT); - - setbits_le32(&power_regs->hw_power_vddactrl, - POWER_VDDACTRL_PWDN_BRNOUT); - - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_PWDN_BRNOUT); -} - -/** - * mxs_get_vddio_power_source_off() - Get VDDIO rail power source - * - * This function tests if the VDDIO rail is supplied by linear regulator - * or by the DC-DC converter. Returns 1 if powered by linear regulator, - * returns 0 if powered by the DC-DC converter. - */ -static int mxs_get_vddio_power_source_off(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - uint32_t tmp; - - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - tmp = readl(&power_regs->hw_power_vddioctrl); - if (tmp & POWER_VDDIOCTRL_DISABLE_FET) { - if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == - POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) { - return 1; - } - } - - if (!(readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_ENABLE_DCDC)) { - if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == - POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) { - return 1; - } - } - } - - return 0; - -} - -/** - * mxs_get_vddd_power_source_off() - Get VDDD rail power source - * - * This function tests if the VDDD rail is supplied by linear regulator - * or by the DC-DC converter. Returns 1 if powered by linear regulator, - * returns 0 if powered by the DC-DC converter. - */ -static int mxs_get_vddd_power_source_off(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - uint32_t tmp; - - tmp = readl(&power_regs->hw_power_vdddctrl); - if (tmp & POWER_VDDDCTRL_DISABLE_FET) { - if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) == - POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { - return 1; - } - } - - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - if (!(readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_ENABLE_DCDC)) { - return 1; - } - } - - if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) { - if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) == - POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) { - return 1; - } - } - - return 0; -} - -struct mxs_vddx_cfg { - uint32_t *reg; - uint8_t step_mV; - uint16_t lowest_mV; - int (*powered_by_linreg)(void); - uint32_t trg_mask; - uint32_t bo_irq; - uint32_t bo_enirq; - uint32_t bo_offset_mask; - uint32_t bo_offset_offset; -}; - -static const struct mxs_vddx_cfg mxs_vddio_cfg = { - .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> - hw_power_vddioctrl), -#if defined(CONFIG_MX23) - .step_mV = 25, -#else - .step_mV = 50, -#endif - .lowest_mV = 2800, - .powered_by_linreg = mxs_get_vddio_power_source_off, - .trg_mask = POWER_VDDIOCTRL_TRG_MASK, - .bo_irq = POWER_CTRL_VDDIO_BO_IRQ, - .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO, - .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK, - .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET, -}; - -static const struct mxs_vddx_cfg mxs_vddd_cfg = { - .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> - hw_power_vdddctrl), - .step_mV = 25, - .lowest_mV = 800, - .powered_by_linreg = mxs_get_vddd_power_source_off, - .trg_mask = POWER_VDDDCTRL_TRG_MASK, - .bo_irq = POWER_CTRL_VDDD_BO_IRQ, - .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO, - .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK, - .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET, -}; - -#ifdef CONFIG_MX23 -static const struct mxs_vddx_cfg mxs_vddmem_cfg = { - .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> - hw_power_vddmemctrl), - .step_mV = 50, - .lowest_mV = 1700, - .powered_by_linreg = NULL, - .trg_mask = POWER_VDDMEMCTRL_TRG_MASK, - .bo_irq = 0, - .bo_enirq = 0, - .bo_offset_mask = 0, - .bo_offset_offset = 0, -}; -#endif - -/** - * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail - * @cfg: Configuration data of the DC-DC converter rail - * @new_target: New target voltage of the DC-DC converter rail - * @new_brownout: New brownout trigger voltage - * - * This function configures the output voltage on the DC-DC converter rail. - * The rail is selected by the @cfg argument. The new voltage target is - * selected by the @new_target and the voltage is specified in mV. The - * new brownout value is selected by the @new_brownout argument and the - * value is also in mV. - */ -static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, - uint32_t new_target, uint32_t new_brownout) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - uint32_t cur_target, diff, bo_int = 0; - uint32_t powered_by_linreg = 0; - int adjust_up, tmp; - - new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV); - - cur_target = readl(cfg->reg); - cur_target &= cfg->trg_mask; - cur_target *= cfg->step_mV; - cur_target += cfg->lowest_mV; - - adjust_up = new_target > cur_target; - if (cfg->powered_by_linreg) - powered_by_linreg = cfg->powered_by_linreg(); - - if (adjust_up && cfg->bo_irq) { - if (powered_by_linreg) { - bo_int = readl(cfg->reg); - clrbits_le32(cfg->reg, cfg->bo_enirq); - } - setbits_le32(cfg->reg, cfg->bo_offset_mask); - } - - do { - if (abs(new_target - cur_target) > 100) { - if (adjust_up) - diff = cur_target + 100; - else - diff = cur_target - 100; - } else { - diff = new_target; - } - - diff -= cfg->lowest_mV; - diff /= cfg->step_mV; - - clrsetbits_le32(cfg->reg, cfg->trg_mask, diff); - - if (powered_by_linreg || - (readl(&power_regs->hw_power_sts) & - POWER_STS_VDD5V_GT_VDDIO)) - early_delay(500); - else { - for (;;) { - tmp = readl(&power_regs->hw_power_sts); - if (tmp & POWER_STS_DC_OK) - break; - } - } - - cur_target = readl(cfg->reg); - cur_target &= cfg->trg_mask; - cur_target *= cfg->step_mV; - cur_target += cfg->lowest_mV; - } while (new_target > cur_target); - - if (cfg->bo_irq) { - if (adjust_up && powered_by_linreg) { - writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr); - if (bo_int & cfg->bo_enirq) - setbits_le32(cfg->reg, cfg->bo_enirq); - } - - clrsetbits_le32(cfg->reg, cfg->bo_offset_mask, - new_brownout << cfg->bo_offset_offset); - } -} - -/** - * mxs_setup_batt_detect() - Start the battery voltage measurement logic - * - * This function starts and configures the LRADC block. This allows the - * power initialization code to measure battery voltage and based on this - * knowledge, decide whether to boot at all, boot from battery or boot - * from 5V input. - */ -static void mxs_setup_batt_detect(void) -{ - mxs_lradc_init(); - mxs_lradc_enable_batt_measurement(); - early_delay(10); -} - -/** - * mxs_ungate_power() - Ungate the POWER block - * - * This function ungates clock to the power block. In case the power block - * was still gated at this point, it will not be possible to configure the - * block and therefore the power initialization would fail. This function - * is only needed on i.MX233, on i.MX28 the power block is always ungated. - */ -static void mxs_ungate_power(void) -{ -#ifdef CONFIG_MX23 - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr); -#endif -} - -/** - * mxs_power_init() - The power block init main function - * - * This function calls all the power block initialization functions in - * proper sequence to start the power block. - */ -void mxs_power_init(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - mxs_ungate_power(); - - mxs_power_clock2xtal(); - mxs_power_set_auto_restart(); - mxs_power_set_linreg(); - mxs_power_setup_5v_detect(); - - mxs_setup_batt_detect(); - - mxs_power_configure_power_source(); - mxs_enable_output_rail_protection(); - - mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150); - mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000); -#ifdef CONFIG_MX23 - mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700); -#endif - writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | - POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | - POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | - POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); - - writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); - - early_delay(1000); -} - -#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT -/** - * mxs_power_wait_pswitch() - Wait for power switch to be pressed - * - * This function waits until the power-switch was pressed to start booting - * the board. - */ -void mxs_power_wait_pswitch(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK)) - ; -} -#endif diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/start.S b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/start.S deleted file mode 100644 index 34a0fcb46..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/start.S +++ /dev/null @@ -1,185 +0,0 @@ -/* - * armboot - Startup Code for ARM926EJS CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ - * - * Copyright (c) 2001 Marius Groger <mag@sysgo.de> - * Copyright (c) 2002 Alex Zupke <azu@sysgo.de> - * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> - * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> - * Copyright (c) 2003 Kshitij <kshitij@ti.com> - * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> - * - * Change to support call back into iMX28 bootrom - * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> -#include <common.h> -#include <version.h> - -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: - b reset - b undefined_instruction - b software_interrupt - b prefetch_abort - b data_abort - b not_used - b irq - b fiq - -/* - * Vector table, located at address 0x20. - * This table allows the code running AFTER SPL, the U-Boot, to install it's - * interrupt handlers here. The problem is that the U-Boot is loaded into RAM, - * including it's interrupt vectoring table and the table at 0x0 is still the - * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table - * is still used. - */ -_vt_reset: - .word _reset -_vt_undefined_instruction: - .word _hang -_vt_software_interrupt: - .word _hang -_vt_prefetch_abort: - .word _hang -_vt_data_abort: - .word _hang -_vt_not_used: - .word _reset -_vt_irq: - .word _hang -_vt_fiq: - .word _hang - -reset: - ldr pc, _vt_reset -undefined_instruction: - ldr pc, _vt_undefined_instruction -software_interrupt: - ldr pc, _vt_software_interrupt -prefetch_abort: - ldr pc, _vt_prefetch_abort -data_abort: - ldr pc, _vt_data_abort -not_used: - ldr pc, _vt_not_used -irq: - ldr pc, _vt_irq -fiq: - ldr pc, _vt_fiq - - .balignl 16,0xdeadbeef - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -_reset: - /* - * If the CPU is configured in "Wait JTAG connection mode", the stack - * pointer is not configured and is zero. This will cause crash when - * trying to push data onto stack right below here. Load the SP and make - * it point to the end of OCRAM if the SP is zero. - */ - cmp sp, #0x00000000 - ldreq sp, =CONFIG_SYS_INIT_SP_ADDR - - /* - * Store all registers on old stack pointer, this will allow us later to - * return to the BootROM and let the BootROM load U-Boot into RAM. - * - * WARNING: Register r0 and r1 are used by the BootROM to pass data - * to the called code. Register r0 will contain arbitrary - * data that are set in the BootStream. In case this code - * was started with CALL instruction, register r1 will contain - * pointer to the return value this function can then set. - * The code below MUST NOT CHANGE register r0 and r1 ! - */ - push {r0-r12,r14} - - /* Save control register c1 */ - mrc p15, 0, r2, c1, c0, 0 - push {r2} - - /* Set the cpu to SVC32 mode and store old CPSR register content. */ - mrs r2, cpsr - push {r2} - bic r2, r2, #0x1f - orr r2, r2, #0xd3 - msr cpsr, r2 - - bl board_init_ll - - /* Restore BootROM's CPU mode (especially FIQ). */ - pop {r2} - msr cpsr,r2 - - /* - * Restore c1 register. Especially set exception vector location - * back to BootROM space which is required by bootrom for USB boot. - */ - pop {r2} - mcr p15, 0, r2, c1, c0, 0 - - pop {r0-r12,r14} - - /* - * In case this code was started by the CALL instruction, the register - * r0 is examined by the BootROM after this code returns. The value in - * r0 must be set to 0 to indicate successful return. - */ - mov r0, #0 - - bx lr - -_hang: -1: - bl 1b /* hang and never return */ diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/timer.c b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/timer.c deleted file mode 100644 index 99d3fb873..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/timer.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Freescale i.MX28 timer driver - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -/* Maximum fixed count */ -#if defined(CONFIG_MX23) -#define TIMER_LOAD_VAL 0xffff -#elif defined(CONFIG_MX28) -#define TIMER_LOAD_VAL 0xffffffff -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp (gd->arch.tbl) -#define lastdec (gd->arch.lastinc) - -/* - * This driver uses 1kHz clock source. - */ -#define MXS_INCREMENTER_HZ 1000 - -static inline unsigned long tick_to_time(unsigned long tick) -{ - return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ); -} - -static inline unsigned long time_to_tick(unsigned long time) -{ - return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ); -} - -/* Calculate how many ticks happen in "us" microseconds */ -static inline unsigned long us_to_tick(unsigned long us) -{ - return (us * MXS_INCREMENTER_HZ) / 1000000; -} - -int timer_init(void) -{ - struct mxs_timrot_regs *timrot_regs = - (struct mxs_timrot_regs *)MXS_TIMROT_BASE; - - /* Reset Timers and Rotary Encoder module */ - mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg); - - /* Set fixed_count to 0 */ -#if defined(CONFIG_MX23) - writel(0, &timrot_regs->hw_timrot_timcount0); -#elif defined(CONFIG_MX28) - writel(0, &timrot_regs->hw_timrot_fixed_count0); -#endif - - /* Set UPDATE bit and 1Khz frequency */ - writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD | - TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL, - &timrot_regs->hw_timrot_timctrl0); - - /* Set fixed_count to maximal value */ -#if defined(CONFIG_MX23) - writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0); -#elif defined(CONFIG_MX28) - writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); -#endif - - return 0; -} - -unsigned long long get_ticks(void) -{ - struct mxs_timrot_regs *timrot_regs = - (struct mxs_timrot_regs *)MXS_TIMROT_BASE; - uint32_t now; - - /* Current tick value */ -#if defined(CONFIG_MX23) - /* Upper bits are the valid ones. */ - now = readl(&timrot_regs->hw_timrot_timcount0) >> - TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET; -#elif defined(CONFIG_MX28) - now = readl(&timrot_regs->hw_timrot_running_count0); -#endif - - if (lastdec >= now) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (lastdec - now); - } else { - /* we have rollover of decrementer */ - timestamp += (TIMER_LOAD_VAL - now) + lastdec; - - } - lastdec = now; - - return timestamp; -} - -ulong get_timer_masked(void) -{ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */ -#define MXS_HW_DIGCTL_MICROSECONDS 0x8001c0c0 - -void __udelay(unsigned long usec) -{ - uint32_t old, new, incr; - uint32_t counter = 0; - - old = readl(MXS_HW_DIGCTL_MICROSECONDS); - - while (counter < usec) { - new = readl(MXS_HW_DIGCTL_MICROSECONDS); - - /* Check if the timer wrapped. */ - if (new < old) { - incr = 0xffffffff - old; - incr += new; - } else { - incr = new - old; - } - - /* - * Check if we are close to the maximum time and the counter - * would wrap if incremented. If that's the case, break out - * from the loop as the requested delay time passed. - */ - if (counter + incr < counter) - break; - - counter += incr; - old = new; - } -} - -ulong get_tbclk(void) -{ - return MXS_INCREMENTER_HZ; -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd deleted file mode 100644 index 3a51879d5..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd +++ /dev/null @@ -1,18 +0,0 @@ -options { - driveTag = 0x00; - flags = 0x01; -} - -sources { - u_boot_spl="spl/u-boot-spl.bin"; - u_boot="u-boot.bin"; -} - -section (0) { - load u_boot_spl > 0x0000; - load ivt (entry = 0x0014) > 0x8000; - call 0x8000; - - load u_boot > 0x40000100; - call 0x40000100; -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd deleted file mode 100644 index c60615a45..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd +++ /dev/null @@ -1,14 +0,0 @@ -sources { - u_boot_spl="spl/u-boot-spl.bin"; - u_boot="u-boot.bin"; -} - -section (0) { - load u_boot_spl > 0x0000; - load ivt (entry = 0x0014) > 0x8000; - hab call 0x8000; - - load u_boot > 0x40000100; - load ivt (entry = 0x40000100) > 0x8000; - hab call 0x8000; -} diff --git a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds deleted file mode 100644 index f4bf8ac1d..000000000 --- a/qemu/roms/u-boot/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * January 2004 - Changed to support H4 device - * Copyright (c) 2004-2008 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = CONFIG_SPL_TEXT_BASE; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm926ejs/mxs/start.o (.text*) - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .bss : { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } - - .end : - { - *(.__end) - } - - _image_binary_end = .; - - .dynsym _image_binary_end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} |