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authorJosé Pekkarinen <jose.pekkarinen@nokia.com>2016-05-18 13:18:31 +0300
committerJosé Pekkarinen <jose.pekkarinen@nokia.com>2016-05-18 13:42:15 +0300
commit437fd90c0250dee670290f9b714253671a990160 (patch)
treeb871786c360704244a07411c69fb58da9ead4a06 /qemu/roms/seabios/src/x86.h
parent5bbd6fe9b8bab2a93e548c5a53b032d1939eec05 (diff)
These changes are the raw update to qemu-2.6.
Collission happened in the following patches: migration: do cleanup operation after completion(738df5b9) Bug fix.(1750c932f86) kvmclock: add a new function to update env->tsc.(b52baab2) The code provided by the patches was already in the upstreamed version. Change-Id: I3cc11841a6a76ae20887b2e245710199e1ea7f9a Signed-off-by: José Pekkarinen <jose.pekkarinen@nokia.com>
Diffstat (limited to 'qemu/roms/seabios/src/x86.h')
-rw-r--r--qemu/roms/seabios/src/x86.h27
1 files changed, 25 insertions, 2 deletions
diff --git a/qemu/roms/seabios/src/x86.h b/qemu/roms/seabios/src/x86.h
index 7798b1c17..53378e9ed 100644
--- a/qemu/roms/seabios/src/x86.h
+++ b/qemu/roms/seabios/src/x86.h
@@ -75,14 +75,22 @@ static inline void __cpuid(u32 index, u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
: "0" (index));
}
-static inline u32 getcr0(void) {
+static inline u32 cr0_read(void) {
u32 cr0;
asm("movl %%cr0, %0" : "=r"(cr0));
return cr0;
}
-static inline void setcr0(u32 cr0) {
+static inline void cr0_write(u32 cr0) {
asm("movl %0, %%cr0" : : "r"(cr0));
}
+static inline void cr0_mask(u32 off, u32 on) {
+ cr0_write((cr0_read() & ~off) | on);
+}
+static inline u16 cr0_vm86_read(void) {
+ u16 cr0;
+ asm("smsww %0" : "=r"(cr0));
+ return cr0;
+}
static inline u64 rdmsr(u32 index)
{
@@ -124,6 +132,13 @@ static inline u32 getesp(void) {
return esp;
}
+static inline u32 rol(u32 val, u16 rol) {
+ u32 res;
+ asm volatile("roll %%cl, %%eax"
+ : "=a" (res) : "a" (val), "c" (rol));
+ return res;
+}
+
static inline void outb(u8 value, u16 port) {
__asm__ __volatile__("outb %b0, %w1" : : "a"(value), "Nd"(port));
}
@@ -175,6 +190,14 @@ static inline void outsl(u16 port, u32 *data, u32 count) {
: "+c"(count), "+S"(data) : "d"(port) : "memory");
}
+/* Compiler barrier is enough as an x86 CPU does not reorder reads or writes */
+static inline void smp_rmb(void) {
+ barrier();
+}
+static inline void smp_wmb(void) {
+ barrier();
+}
+
static inline void writel(void *addr, u32 val) {
barrier();
*(volatile u32 *)addr = val;