Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

7 files changed, 0 insertions, 686 deletions

diff --git a/qemu/roms/openbios/include/arch/sparc64/a.out.h b/qemu/roms/openbios/include/arch/sparc64/a.out.h
deleted file mode 100644
index 35cb5c9e0..000000000
--- a/qemu/roms/openbios/include/arch/sparc64/a.out.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* $Id: a.out.h,v 1.8 2002/02/09 19:49:31 davem Exp $ */
-#ifndef __SPARC64_A_OUT_H__
-#define __SPARC64_A_OUT_H__
-
-#define SPARC_PGSIZE    0x2000        /* Thanks to the sun4 architecture... */
-#define SEGMENT_SIZE    SPARC_PGSIZE  /* whee... */
-
-#ifndef __ASSEMBLY__
-
-struct exec {
-	unsigned char a_dynamic:1;      /* A __DYNAMIC is in this image */
-	unsigned char a_toolversion:7;
-	unsigned char a_machtype;
-	unsigned short a_info;
-	unsigned int a_text;		/* length of text, in bytes */
-	unsigned int a_data;		/* length of data, in bytes */
-	unsigned int a_bss;		/* length of bss, in bytes */
-	unsigned int a_syms;		/* length of symbol table, in bytes */
-	unsigned int a_entry;		/* where program begins */
-	unsigned int a_trsize;
-	unsigned int a_drsize;
-};
-
-#endif /* !__ASSEMBLY__ */
-
-/* Where in the file does the text information begin? */
-#define N_TXTOFF(x)     (N_MAGIC(x) == ZMAGIC ? 0 : sizeof (struct exec))
-
-/* Where do the Symbols start? */
-#define N_SYMOFF(x)     (N_TXTOFF(x) + (x).a_text +   \
-                         (x).a_data + (x).a_trsize +  \
-                         (x).a_drsize)
-
-/* Where does text segment go in memory after being loaded? */
-#define N_TXTADDR(x)    (unsigned long)(((N_MAGIC(x) == ZMAGIC) &&      \
-	                 ((x).a_entry < SPARC_PGSIZE)) ?   		\
-                          0 : SPARC_PGSIZE)
-
-/* And same for the data segment.. */
-#define N_DATADDR(x) (N_MAGIC(x)==OMAGIC ?         \
-                      (N_TXTADDR(x) + (x).a_text)  \
-                       : (unsigned long)(_N_SEGMENT_ROUND (_N_TXTENDADDR(x))))
-
-#define N_TRSIZE(a)	((a).a_trsize)
-#define N_DRSIZE(a)	((a).a_drsize)
-#define N_SYMSIZE(a)	((a).a_syms)
-
-#ifndef __ASSEMBLY__
-
-/*
- * Sparc relocation types
- */
-enum reloc_type
-{
-	RELOC_8,
-	RELOC_16,
-	RELOC_32,	/* simplest relocs */
-	RELOC_DISP8,
-	RELOC_DISP16,
-	RELOC_DISP32,	/* Disp's (pc-rel) */
-	RELOC_WDISP30,
-	RELOC_WDISP22,  /* SR word disp's */
-	RELOC_HI22,
-	RELOC_22,	/* SR 22-bit relocs */
-	RELOC_13,
-	RELOC_LO10,	/* SR 13&10-bit relocs */
-	RELOC_SFA_BASE,
-	RELOC_SFA_OFF13, /* SR S.F.A. relocs */
-	RELOC_BASE10,
-	RELOC_BASE13,
-	RELOC_BASE22,	/* base_relative pic */
-	RELOC_PC10,
-	RELOC_PC22,	/* special pc-rel pic */
-	RELOC_JMP_TBL,	/* jmp_tbl_rel in pic */
-	RELOC_SEGOFF16,	/* ShLib offset-in-seg */
-	RELOC_GLOB_DAT,
-	RELOC_JMP_SLOT,
-	RELOC_RELATIVE 	/* rtld relocs */
-};
-
-/*
- * Format of a relocation datum.
- */
-struct relocation_info /* used when header.a_machtype == M_SPARC */
-{
-        unsigned int    r_address;  /* relocation addr */
-        unsigned int    r_index:24; /* segment index or symbol index */
-        unsigned int    r_extern:1; /* if F, r_index==SEG#; if T, SYM idx */
-        int             r_pad:2;    /* <unused> */
-        enum reloc_type r_type:5;   /* type of relocation to perform */
-        int             r_addend;   /* addend for relocation value */
-};
-
-#define N_RELOCATION_INFO_DECLARED 1
-
-#ifdef __KERNEL__
-
-#define STACK_TOP32	((1UL << 32UL) - PAGE_SIZE)
-#define STACK_TOP64	(0x0000080000000000UL - (1UL << 32UL))
-
-#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
-		   STACK_TOP32 : STACK_TOP64)
-
-#endif
-
-#endif /* !(__ASSEMBLY__) */
-
-#endif /* !(__SPARC64_A_OUT_H__) */
diff --git a/qemu/roms/openbios/include/arch/sparc64/asi.h b/qemu/roms/openbios/include/arch/sparc64/asi.h
deleted file mode 100644
index 534855660..000000000
--- a/qemu/roms/openbios/include/arch/sparc64/asi.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/* $Id: asi.h,v 1.5 2001/03/29 11:47:47 davem Exp $ */
-#ifndef _SPARC64_ASI_H
-#define _SPARC64_ASI_H
-
-/* asi.h:  Address Space Identifier values for the V9.
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- */
-
-/* V9 Architecture mandary ASIs. */
-#define ASI_N			0x04 /* Nucleus				*/
-#define ASI_NL			0x0c /* Nucleus, little endian		*/
-#define ASI_AIUP		0x10 /* Primary, user			*/
-#define ASI_AIUS		0x11 /* Secondary, user			*/
-#define ASI_AIUPL		0x18 /* Primary, user, little endian	*/
-#define ASI_AIUSL		0x19 /* Secondary, user, little endian	*/
-#define ASI_P			0x80 /* Primary, implicit		*/
-#define ASI_S			0x81 /* Secondary, implicit		*/
-#define ASI_PNF			0x82 /* Primary, no fault		*/
-#define ASI_SNF			0x83 /* Secondary, no fault		*/
-#define ASI_PL			0x88 /* Primary, implicit, l-endian	*/
-#define ASI_SL			0x89 /* Secondary, implicit, l-endian	*/
-#define ASI_PNFL		0x8a /* Primary, no fault, l-endian	*/
-#define ASI_SNFL		0x8b /* Secondary, no fault, l-endian	*/
-
-/* SpitFire and later extended ASIs.  The "(III)" marker designates
- * UltraSparc-III and later specific ASIs.  The "(CMT)" marker designates
- * Chip Multi Threading specific ASIs.
- */
-#define ASI_PHYS_USE_EC		0x14 /* PADDR, E-cachable		*/
-#define ASI_PHYS_BYPASS_EC_E	0x15 /* PADDR, E-bit			*/
-#define ASI_PHYS_USE_EC_L	0x1c /* PADDR, E-cachable, little endian*/
-#define ASI_PHYS_BYPASS_EC_E_L	0x1d /* PADDR, E-bit, little endian	*/
-#define ASI_NUCLEUS_QUAD_LDD	0x24 /* Cachable, qword load		*/
-#define ASI_NUCLEUS_QUAD_LDD_L	0x2c /* Cachable, qword load, l-endian 	*/
-#define ASI_PCACHE_DATA_STATUS	0x30 /* (III) PCache data stat RAM diag	*/
-#define ASI_PCACHE_DATA		0x31 /* (III) PCache data RAM diag	*/
-#define ASI_PCACHE_TAG		0x32 /* (III) PCache tag RAM diag	*/
-#define ASI_PCACHE_SNOOP_TAG	0x33 /* (III) PCache snoop tag RAM diag	*/
-#define ASI_QUAD_LDD_PHYS	0x34 /* (III+) PADDR, qword load	*/
-#define ASI_WCACHE_VALID_BITS	0x38 /* (III) WCache Valid Bits diag	*/
-#define ASI_WCACHE_DATA		0x39 /* (III) WCache data RAM diag	*/
-#define ASI_WCACHE_TAG		0x3a /* (III) WCache tag RAM diag	*/
-#define ASI_WCACHE_SNOOP_TAG	0x3b /* (III) WCache snoop tag RAM diag	*/
-#define ASI_QUAD_LDD_PHYS_L	0x3c /* (III+) PADDR, qw-load, l-endian	*/
-#define ASI_SRAM_FAST_INIT	0x40 /* (III+) Fast SRAM init		*/
-#define ASI_CORE_AVAILABLE	0x41 /* (CMT) LP Available		*/
-#define ASI_CORE_ENABLE_STAT	0x41 /* (CMT) LP Enable Status		*/
-#define ASI_CORE_ENABLE		0x41 /* (CMT) LP Enable RW		*/
-#define ASI_XIR_STEERING	0x41 /* (CMT) XIR Steering RW		*/
-#define ASI_CORE_RUNNING_RW	0x41 /* (CMT) LP Running RW		*/
-#define ASI_CORE_RUNNING_W1S	0x41 /* (CMT) LP Running Write-One Set	*/
-#define ASI_CORE_RUNNING_W1C	0x41 /* (CMT) LP Running Write-One Clr	*/
-#define ASI_CORE_RUNNING_STAT	0x41 /* (CMT) LP Running Status		*/
-#define ASI_CMT_ERROR_STEERING	0x41 /* (CMT) Error Steering RW		*/
-#define ASI_DCACHE_INVALIDATE	0x42 /* (III) DCache Invalidate diag	*/
-#define ASI_DCACHE_UTAG		0x43 /* (III) DCache uTag diag		*/
-#define ASI_DCACHE_SNOOP_TAG	0x44 /* (III) DCache snoop tag RAM diag	*/
-#define ASI_LSU_CONTROL		0x45 /* Load-store control unit		*/
-#define ASI_DCU_CONTROL_REG	0x45 /* (III) DCache Unit Control reg	*/
-#define ASI_DCACHE_DATA		0x46 /* DCache data-ram diag access	*/
-#define ASI_DCACHE_TAG		0x47 /* Dcache tag/valid ram diag access*/
-#define ASI_INTR_DISPATCH_STAT	0x48 /* IRQ vector dispatch status	*/
-#define ASI_INTR_RECEIVE	0x49 /* IRQ vector receive status	*/
-#define ASI_UPA_CONFIG		0x4a /* UPA config space		*/
-#define ASI_JBUS_CONFIG		0x4a /* (IIIi) JBUS Config Register	*/
-#define ASI_SAFARI_CONFIG	0x4a /* (III) Safari Config Register	*/
-#define ASI_SAFARI_ADDRESS	0x4a /* (III) Safari Address Register	*/
-#define ASI_ESTATE_ERROR_EN	0x4b /* E-cache error enable space	*/
-#define ASI_AFSR		0x4c /* Async fault status register	*/
-#define ASI_AFAR		0x4d /* Async fault address register	*/
-#define ASI_EC_TAG_DATA		0x4e /* E-cache tag/valid ram diag acc	*/
-#define ASI_IMMU		0x50 /* Insn-MMU main register space	*/
-#define ASI_IMMU_TSB_8KB_PTR	0x51 /* Insn-MMU 8KB TSB pointer reg	*/
-#define ASI_IMMU_TSB_64KB_PTR	0x52 /* Insn-MMU 64KB TSB pointer reg	*/
-#define ASI_ITLB_DATA_IN	0x54 /* Insn-MMU TLB data in reg	*/
-#define ASI_ITLB_DATA_ACCESS	0x55 /* Insn-MMU TLB data access reg	*/
-#define ASI_ITLB_TAG_READ	0x56 /* Insn-MMU TLB tag read reg	*/
-#define ASI_IMMU_DEMAP		0x57 /* Insn-MMU TLB demap		*/
-#define ASI_DMMU		0x58 /* Data-MMU main register space	*/
-#define ASI_DMMU_TSB_8KB_PTR	0x59 /* Data-MMU 8KB TSB pointer reg	*/
-#define ASI_DMMU_TSB_64KB_PTR	0x5a /* Data-MMU 16KB TSB pointer reg	*/
-#define ASI_DMMU_TSB_DIRECT_PTR	0x5b /* Data-MMU TSB direct pointer reg	*/
-#define ASI_DTLB_DATA_IN	0x5c /* Data-MMU TLB data in reg	*/
-#define ASI_DTLB_DATA_ACCESS	0x5d /* Data-MMU TLB data access reg	*/
-#define ASI_DTLB_TAG_READ	0x5e /* Data-MMU TLB tag read reg	*/
-#define ASI_DMMU_DEMAP		0x5f /* Data-MMU TLB demap		*/
-#define ASI_IIU_INST_TRAP	0x60 /* (III) Instruction Breakpoint	*/
-#define ASI_INTR_ID		0x63 /* (CMT) Interrupt ID register	*/
-#define ASI_CORE_ID		0x63 /* (CMT) LP ID register		*/
-#define ASI_CESR_ID		0x63 /* (CMT) CESR ID register		*/
-#define ASI_IC_INSTR		0x66 /* Insn cache instrucion ram diag	*/
-#define ASI_IC_TAG		0x67 /* Insn cache tag/valid ram diag 	*/
-#define ASI_IC_STAG		0x68 /* (III) Insn cache snoop tag ram	*/
-#define ASI_IC_PRE_DECODE	0x6e /* Insn cache pre-decode ram diag	*/
-#define ASI_IC_NEXT_FIELD	0x6f /* Insn cache next-field ram diag	*/
-#define ASI_BRPRED_ARRAY	0x6f /* (III) Branch Prediction RAM diag*/
-#define ASI_BLK_AIUP		0x70 /* Primary, user, block load/store	*/
-#define ASI_BLK_AIUS		0x71 /* Secondary, user, block ld/st	*/
-#define ASI_MCU_CTRL_REG	0x72 /* (III) Memory controller regs	*/
-#define ASI_EC_DATA		0x74 /* (III) E-cache data staging reg	*/
-#define ASI_EC_CTRL		0x75 /* (III) E-cache control reg	*/
-#define ASI_EC_W		0x76 /* E-cache diag write access	*/
-#define ASI_UDB_ERROR_W		0x77 /* External UDB error regs W	*/
-#define ASI_UDB_CONTROL_W	0x77 /* External UDB control regs W	*/
-#define ASI_INTR_W		0x77 /* IRQ vector dispatch write	*/
-#define ASI_INTR_DATAN_W	0x77 /* (III) Out irq vector data reg N	*/
-#define ASI_INTR_DISPATCH_W	0x77 /* (III) Interrupt vector dispatch	*/
-#define ASI_BLK_AIUPL		0x78 /* Primary, user, little, blk ld/st*/
-#define ASI_BLK_AIUSL		0x79 /* Secondary, user, little, blk ld/st*/
-#define ASI_EC_R		0x7e /* E-cache diag read access	*/
-#define ASI_UDBH_ERROR_R	0x7f /* External UDB error regs rd hi	*/
-#define ASI_UDBL_ERROR_R	0x7f /* External UDB error regs rd low	*/
-#define ASI_UDBH_CONTROL_R	0x7f /* External UDB control regs rd hi	*/
-#define ASI_UDBL_CONTROL_R	0x7f /* External UDB control regs rd low*/
-#define ASI_INTR_R		0x7f /* IRQ vector dispatch read	*/
-#define ASI_INTR_DATAN_R	0x7f /* (III) In irq vector data reg N	*/
-#define ASI_PST8_P		0xc0 /* Primary, 8 8-bit, partial	*/
-#define ASI_PST8_S		0xc1 /* Secondary, 8 8-bit, partial	*/
-#define ASI_PST16_P		0xc2 /* Primary, 4 16-bit, partial	*/
-#define ASI_PST16_S		0xc3 /* Secondary, 4 16-bit, partial	*/
-#define ASI_PST32_P		0xc4 /* Primary, 2 32-bit, partial	*/
-#define ASI_PST32_S		0xc5 /* Secondary, 2 32-bit, partial	*/
-#define ASI_PST8_PL		0xc8 /* Primary, 8 8-bit, partial, L	*/
-#define ASI_PST8_SL		0xc9 /* Secondary, 8 8-bit, partial, L	*/
-#define ASI_PST16_PL		0xca /* Primary, 4 16-bit, partial, L	*/
-#define ASI_PST16_SL		0xcb /* Secondary, 4 16-bit, partial, L	*/
-#define ASI_PST32_PL		0xcc /* Primary, 2 32-bit, partial, L	*/
-#define ASI_PST32_SL		0xcd /* Secondary, 2 32-bit, partial, L	*/
-#define ASI_FL8_P		0xd0 /* Primary, 1 8-bit, fpu ld/st	*/
-#define ASI_FL8_S		0xd1 /* Secondary, 1 8-bit, fpu ld/st	*/
-#define ASI_FL16_P		0xd2 /* Primary, 1 16-bit, fpu ld/st	*/
-#define ASI_FL16_S		0xd3 /* Secondary, 1 16-bit, fpu ld/st	*/
-#define ASI_FL8_PL		0xd8 /* Primary, 1 8-bit, fpu ld/st, L	*/
-#define ASI_FL8_SL		0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/
-#define ASI_FL16_PL		0xda /* Primary, 1 16-bit, fpu ld/st, L	*/
-#define ASI_FL16_SL		0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/
-#define ASI_BLK_COMMIT_P	0xe0 /* Primary, blk store commit	*/
-#define ASI_BLK_COMMIT_S	0xe1 /* Secondary, blk store commit	*/
-#define ASI_BLK_P		0xf0 /* Primary, blk ld/st		*/
-#define ASI_BLK_S		0xf1 /* Secondary, blk ld/st		*/
-#define ASI_BLK_PL		0xf8 /* Primary, blk ld/st, little	*/
-#define ASI_BLK_SL		0xf9 /* Secondary, blk ld/st, little	*/
-
-#endif /* _SPARC64_ASI_H */
diff --git a/qemu/roms/openbios/include/arch/sparc64/elf.h b/qemu/roms/openbios/include/arch/sparc64/elf.h
deleted file mode 100644
index 8acad1a47..000000000
--- a/qemu/roms/openbios/include/arch/sparc64/elf.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#define ARCH_ELF_CLASS ELFCLASS64
-#define ARCH_ELF_DATA ELFDATA2MSB
-#define ARCH_ELF_MACHINE_OK(x) ((x)==EM_SPARCV9)
-typedef Elf64_Ehdr Elf_ehdr;
-typedef Elf64_Phdr Elf_phdr;
diff --git a/qemu/roms/openbios/include/arch/sparc64/io.h b/qemu/roms/openbios/include/arch/sparc64/io.h
deleted file mode 100644
index 0f1a73284..000000000
--- a/qemu/roms/openbios/include/arch/sparc64/io.h
+++ /dev/null
@@ -1,209 +0,0 @@
-#ifndef _ASM_IO_H
-#define _ASM_IO_H
-
-#include "asm/types.h"
-#include "asi.h"
-
-#define NO_QEMU_PROTOS
-#include "arch/common/fw_cfg.h"
-
-extern unsigned long va_shift; // Set in entry.S
-// Defined in ldscript
-extern char _start, _data, _stack, _estack, _fcstack, _efcstack, _end, _iomem;
-
-// XXX check use and merge
-#define phys_to_virt(phys) ((void *) ((unsigned long) (phys)))
-#define virt_to_phys(virt) ((unsigned long) (virt))
-
-#ifndef BOOTSTRAP
-
-extern unsigned long isa_io_base;
-
-/*
- * The insw/outsw/insl/outsl macros don't do byte-swapping.
- * They are only used in practice for transferring buffers which
- * are arrays of bytes, and byte-swapping is not appropriate in
- * that case.  - paulus
- */
-#define insw(port, buf, ns)	_insw_ns((uint16_t *)((port)+isa_io_base), (buf), (ns))
-#define outsw(port, buf, ns)	_outsw_ns((uint16_t *)((port)+isa_io_base), (buf), (ns))
-
-#define inb(port)		in_8((uint8_t *)((port)+isa_io_base))
-#define outb(val, port)		out_8((uint8_t *)((port)+isa_io_base), (val))
-#define inw(port)		in_be16((uint16_t *)((port)+isa_io_base))
-#define outw(val, port)		out_be16((uint16_t *)((port)+isa_io_base), (val))
-#define inl(port)		in_be32((uint32_t *)((port)+isa_io_base))
-#define outl(val, port)		out_be32((uint32_t *)((port)+isa_io_base), (val))
-
-/*
- * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
- * On Sparc64, BE versions must swap bytes using LE access ASI.
- */
-static inline int in_8(volatile unsigned char *addr)
-{
-    int ret;
-
-    __asm__ __volatile__("lduba [%1] %2, %0\n\t"
-                         : "=r"(ret)
-                         : "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E)
-                         : "memory");
-
-    return ret;
-}
-
-static inline void out_8(volatile unsigned char *addr, int val)
-{
-    __asm__ __volatile__("stba %0, [%1] %2\n\t"
-                         :
-                         : "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E)
-                         : "memory");
-}
-
-static inline int in_le16(volatile unsigned short *addr)
-{
-    int ret;
-
-    __asm__ __volatile__("lduha [%1] %2, %0\n\t"
-                         : "=r"(ret)
-                         : "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E)
-                         : "memory");
-
-    return ret;
-}
-
-static inline int in_be16(volatile unsigned short *addr)
-{
-    int ret;
-
-    __asm__ __volatile__("lduha [%1] %2, %0\n\t"
-                         : "=r"(ret)
-                         : "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
-                         : "memory");
-
-    return ret;
-}
-
-static inline void out_le16(volatile unsigned short *addr, int val)
-{
-
-    __asm__ __volatile__("stha %0, [%1] %2\n\t"
-                         :
-                         : "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E)
-                         : "memory");
-}
-
-static inline void out_be16(volatile unsigned short *addr, int val)
-{
-    __asm__ __volatile__("stha %0, [%1] %2\n\t"
-                         :
-                         : "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
-                         : "memory");
-}
-
-static inline unsigned in_le32(volatile unsigned *addr)
-{
-    unsigned ret;
-
-    __asm__ __volatile__("lduwa [%1] %2, %0\n\t"
-                         : "=r"(ret)
-                         : "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E)
-                         : "memory");
-
-    return ret;
-}
-
-static inline unsigned in_be32(volatile unsigned *addr)
-{
-    unsigned ret;
-
-    __asm__ __volatile__("lduwa [%1] %2, %0\n\t"
-                         : "=r"(ret)
-                         : "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
-                         : "memory");
-    return ret;
-}
-
-static inline void out_le32(volatile unsigned *addr, int val)
-{
-    __asm__ __volatile__("stwa %0, [%1] %2\n\t"
-                         :
-                         : "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E)
-                         : "memory");
-}
-
-static inline void out_be32(volatile unsigned *addr, int val)
-{
-    __asm__ __volatile__("stwa %0, [%1] %2\n\t"
-                         :
-                         : "r"(val), "r"(addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
-                         : "memory");
-}
-
-static inline void _insw_ns(volatile uint16_t * port, void *buf, int ns)
-{
-	uint16_t *b = (uint16_t *) buf;
-
-	while (ns > 0) {
-		*b++ = in_le16(port);
-		ns--;
-	}
-}
-
-static inline void _outsw_ns(volatile uint16_t * port, const void *buf,
-			     int ns)
-{
-	uint16_t *b = (uint16_t *) buf;
-
-	while (ns > 0) {
-		out_le16(port, *b++);
-		ns--;
-	}
-}
-
-static inline void _insw(volatile uint16_t * port, void *buf, int ns)
-{
-	uint16_t *b = (uint16_t *) buf;
-
-	while (ns > 0) {
-		*b++ = in_be16(port);
-		ns--;
-	}
-}
-
-static inline void _outsw(volatile uint16_t * port, const void *buf,
-			  int ns)
-{
-	uint16_t *b = (uint16_t *) buf;
-
-	while (ns > 0) {
-		out_be16(port, *b++);
-		ns--;
-	}
-}
-#else /* BOOTSTRAP */
-#ifdef FCOMPILER
-#define inb(reg) ((u8)0xff)
-#define inw(reg) ((u16)0xffff)
-#define inl(reg) ((u32)0xffffffff)
-#define outb(reg, val) do{} while(0)
-#define outw(reg, val) do{} while(0)
-#define outl(reg, val) do{} while(0)
-#else
-extern u8 inb(u32 reg);
-extern u16 inw(u32 reg);
-extern u32 inl(u32 reg);
-extern void insw(u32 reg, void *addr, unsigned long count);
-extern void outb(u32 reg, u8 val);
-extern void outw(u32 reg, u16 val);
-extern void outl(u32 reg, u32 val);
-extern void outsw(u32 reg, const void *addr, unsigned long count);
-#endif
-#endif
-
-#if defined(CONFIG_QEMU)
-#define FW_CFG_ARCH_WIDTH        (FW_CFG_ARCH_LOCAL + 0x00)
-#define FW_CFG_ARCH_HEIGHT       (FW_CFG_ARCH_LOCAL + 0x01)
-#define FW_CFG_ARCH_DEPTH        (FW_CFG_ARCH_LOCAL + 0x02)
-#endif
-
-#endif /* _ASM_IO_H */
diff --git a/qemu/roms/openbios/include/arch/sparc64/ofmem_sparc64.h b/qemu/roms/openbios/include/arch/sparc64/ofmem_sparc64.h
deleted file mode 100644
index 7ff24ae3d..000000000
--- a/qemu/roms/openbios/include/arch/sparc64/ofmem_sparc64.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *	<ofmem_sparc64.h>
- *
- *	OF Memory manager
- *
- *   Copyright (C) 1999, 2002 Samuel Rydh (samuel@ibrium.se)
- *
- *   This program is free software; you can redistribute it and/or
- *   modify it under the terms of the GNU General Public License
- *   as published by the Free Software Foundation
- *
- */
-
-#ifndef _H_OFMEM_SPARC64
-#define _H_OFMEM_SPARC64
-
-#include "libopenbios/ofmem.h"
-
-#define PAGE_SIZE_4M   (4 * 1024 * 1024)
-#define PAGE_SIZE_512K (512 * 1024)
-#define PAGE_SIZE_64K  (64 * 1024)
-#define PAGE_SIZE_8K   (8 * 1024)
-#define PAGE_MASK_4M   (4 * 1024 * 1024 - 1)
-#define PAGE_MASK_512K (512 * 1024 - 1)
-#define PAGE_MASK_64K  (64 * 1024 - 1)
-#define PAGE_MASK_8K   (8 * 1024 - 1)
-
-extern ucell *va2ttedata;
-extern unsigned long find_tte(unsigned long va);
-
-void itlb_load2(unsigned long vaddr, unsigned long tte_data);
-void itlb_load3(unsigned long vaddr, unsigned long tte_data, unsigned long tte_index);
-unsigned long itlb_faultva(void);
-void itlb_demap(unsigned long vaddr);
-void dtlb_load2(unsigned long vaddr, unsigned long tte_data);
-void dtlb_load3(unsigned long vaddr, unsigned long tte_data, unsigned long tte_index);
-unsigned long dtlb_faultva(void);
-void dtlb_demap(unsigned long vaddr);
-
-typedef int (*translation_entry_cb)(ucell phys,	ucell virt, ucell size, ucell mode);
-
-extern void ofmem_walk_boot_map(translation_entry_cb cb);
-
-extern translation_t **g_ofmem_translations;
-
-extern void dtlb_miss_handler(void);
-extern void itlb_miss_handler(void);
-extern void bug(void);
-
-#endif   /* _H_OFMEM_SPARC64 */
diff --git a/qemu/roms/openbios/include/arch/sparc64/pci.h b/qemu/roms/openbios/include/arch/sparc64/pci.h
deleted file mode 100644
index c7509afe5..000000000
--- a/qemu/roms/openbios/include/arch/sparc64/pci.h
+++ /dev/null
@@ -1,67 +0,0 @@
-#ifndef SPARC64_PCI_H
-#define SPARC64_PCI_H
-
-#include "asm/io.h"
-
-#if !(defined(PCI_CONFIG_1) || defined(PCI_CONFIG_2))
-#define PCI_CONFIG_1 1 /* default */
-#endif
-
-#ifdef PCI_CONFIG_1
-
-/* PCI Configuration Mechanism #1 */
-
-#define PCI_ADDR(bus, dev, fn) \
-    (((pci_addr) (uint32_t) (bus) << 16  \
-		| (uint32_t) (dev) << 11 \
-		| (uint32_t) (fn) << 8))
-
-#define PCI_BUS(pcidev) ((uint8_t) ((pcidev) >> 16) & 0xff)
-#define PCI_DEV(pcidev) ((uint8_t) ((pcidev) >> 11) & 0x1f)
-#define PCI_FN(pcidev) ((uint8_t) ((pcidev) >> 8) & 7)
-
-#define PCI_CONFIG(dev) (arch->cfg_addr                                 \
-                         + (unsigned long)PCI_ADDR(PCI_BUS(dev),        \
-                                                   PCI_DEV(dev),        \
-                                                   PCI_FN(dev)))
-
-static inline uint8_t pci_config_read8(pci_addr dev, uint8_t reg)
-{
-	uint8_t res;
-        res = in_8((unsigned char*)(PCI_CONFIG(dev) + reg));
-	return res;
-}
-
-static inline uint16_t pci_config_read16(pci_addr dev, uint8_t reg)
-{
-	uint16_t res;
-        res = in_be16((uint16_t *)(PCI_CONFIG(dev) + reg));
-	return res;
-}
-
-static inline uint32_t pci_config_read32(pci_addr dev, uint8_t reg)
-{
-	uint32_t res;
-        res = in_be32((uint32_t *)(PCI_CONFIG(dev) + reg));
-	return res;
-}
-
-static inline void pci_config_write8(pci_addr dev, uint8_t reg, uint8_t val)
-{
-        out_8((unsigned char*)(PCI_CONFIG(dev) + reg), val);
-}
-
-static inline void pci_config_write16(pci_addr dev, uint8_t reg, uint16_t val)
-{
-        out_be16((uint16_t *)(PCI_CONFIG(dev) + reg), val);
-}
-
-static inline void pci_config_write32(pci_addr dev, uint8_t reg, uint32_t val)
-{
-        out_be32((uint32_t *)(PCI_CONFIG(dev) + reg), val);
-}
-#else /* !PCI_CONFIG_1 */
-#error PCI Configuration Mechanism is not specified or implemented
-#endif
-
-#endif /* SPARC64_PCI_H */
diff --git a/qemu/roms/openbios/include/arch/sparc64/types.h b/qemu/roms/openbios/include/arch/sparc64/types.h
deleted file mode 100644
index a26fccb2c..000000000
--- a/qemu/roms/openbios/include/arch/sparc64/types.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* tag: data types for forth engine
- *
- * Copyright (C) 2003-2005 Patrick Mauritz, Stefan Reinauer
- *
- * See the file "COPYING" for further information about
- * the copyright and warranty status of this work.
- */
-
-#ifndef __TYPES_H
-#define __TYPES_H
-
-#include "mconfig.h"
-
-#ifdef BOOTSTRAP
-#include <inttypes.h>
-#else
-typedef unsigned char   uint8_t;
-typedef unsigned short  uint16_t;
-typedef unsigned int    uint32_t;
-typedef unsigned long long uint64_t;
-typedef unsigned long   uintptr_t;
-
-typedef signed char     int8_t;
-typedef short           int16_t;
-typedef int             int32_t;
-typedef long long       int64_t;
-typedef long            intptr_t;
-
-#define PRId32 "d"
-#define PRIu32 "u"
-#define PRIx32 "x"
-#define PRIX32 "X"
-#define PRId64 "lld"
-#define PRIu64 "llu"
-#define PRIx64 "llx"
-#define PRIX64 "llX"
-#endif
-
-/* endianess */
-#include "autoconf.h"
-
-/* physical address */
-typedef uint64_t phys_addr_t;
-
-#define FMT_plx "%016" PRIx64
-
-/* cell based types */
-typedef int64_t     cell;
-typedef uint64_t    ucell;
-
-#define FMT_cell    "%" PRId64
-#define FMT_ucell   "%" PRIu64
-#define FMT_ucellx  "%016" PRIx64
-#define FMT_ucellX  "%016" PRIX64
-
-typedef int64_t         prom_arg_t;
-typedef uint64_t        prom_uarg_t;
-
-#define PRIdPROMARG     PRId64
-#define PRIuPROMARG     PRIu64
-#define PRIxPROMARG     PRIx64
-#define FMT_prom_arg    "%" PRIdPROMARG
-#define FMT_prom_uarg   "%" PRIuPROMARG
-#define FMT_prom_uargx  "%016" PRIxPROMARG
-
-#define FMT_elf	    "%#llx"
-#define FMT_sizet   "%lx"
-#define FMT_aout_ehdr  "%x"
-
-#ifdef NEED_FAKE_INT128_T
-typedef struct {
-    uint64_t hi;
-    uint64_t lo;
-} blob_128_t;
-
-typedef blob_128_t      dcell;
-typedef blob_128_t     ducell;
-#else
-typedef __int128_t	dcell;
-typedef __uint128_t    ducell;
-#endif
-
-#define bitspercell	(sizeof(cell)<<3)
-#define bitsperdcell	(sizeof(dcell)<<3)
-
-#define BITS		64
-
-#define PAGE_SHIFT	13
-
-/* size named types */
-
-typedef unsigned char   u8;
-typedef unsigned short u16;
-typedef unsigned int   u32;
-typedef unsigned long long u64;
-
-typedef signed char	s8;
-typedef short		s16;
-typedef int		s32;
-typedef long long	s64;
-
-#endif