Adding qemu as a submodule of KVMFORNFV

This Patch includes the changes to add qemu as a submodule to
kvmfornfv repo and make use of the updated latest qemu for the
execution of all testcase
Change-Id: I1280af507a857675c7f81d30c95255635667bdd7
Signed-off-by:RajithaY<rajithax.yerrumsetty@intel.com>

8 files changed, 0 insertions, 766 deletions

diff --git a/qemu/roms/openbios/include/arch/sparc32/a.out.h b/qemu/roms/openbios/include/arch/sparc32/a.out.h
deleted file mode 100644
index e4e83eb01..000000000
--- a/qemu/roms/openbios/include/arch/sparc32/a.out.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* $Id: a.out.h,v 1.13 2000/01/09 10:46:53 anton Exp $ */
-#ifndef __SPARC_A_OUT_H__
-#define __SPARC_A_OUT_H__
-
-#define SPARC_PGSIZE    0x2000        /* Thanks to the sun4 architecture... */
-#define SEGMENT_SIZE    SPARC_PGSIZE  /* whee... */
-
-struct exec {
-	unsigned char a_dynamic:1;      /* A __DYNAMIC is in this image */
-	unsigned char a_toolversion:7;
-	unsigned char a_machtype;
-	unsigned short a_info;
-	unsigned long a_text;		/* length of text, in bytes */
-	unsigned long a_data;		/* length of data, in bytes */
-	unsigned long a_bss;		/* length of bss, in bytes */
-	unsigned long a_syms;		/* length of symbol table, in bytes */
-	unsigned long a_entry;		/* where program begins */
-	unsigned long a_trsize;
-	unsigned long a_drsize;
-};
-
-/* Where in the file does the text information begin? */
-#define N_TXTOFF(x)     (N_MAGIC(x) == ZMAGIC ? 0 : sizeof (struct exec))
-
-/* Where do the Symbols start? */
-#define N_SYMOFF(x)     (N_TXTOFF(x) + (x).a_text +   \
-                         (x).a_data + (x).a_trsize +  \
-                         (x).a_drsize)
-
-/* Where does text segment go in memory after being loaded? */
-#define N_TXTADDR(x)    (((N_MAGIC(x) == ZMAGIC) &&        \
-	                 ((x).a_entry < SPARC_PGSIZE)) ?   \
-                          0 : SPARC_PGSIZE)
-
-/* And same for the data segment.. */
-#define N_DATADDR(x) (N_MAGIC(x)==OMAGIC ?         \
-                      (N_TXTADDR(x) + (x).a_text)  \
-                       : (_N_SEGMENT_ROUND (_N_TXTENDADDR(x))))
-
-#define N_TRSIZE(a)	((a).a_trsize)
-#define N_DRSIZE(a)	((a).a_drsize)
-#define N_SYMSIZE(a)	((a).a_syms)
-
-/*
- * Sparc relocation types
- */
-enum reloc_type
-{
-	RELOC_8,
-	RELOC_16,
-	RELOC_32,	/* simplest relocs */
-	RELOC_DISP8,
-	RELOC_DISP16,
-	RELOC_DISP32,	/* Disp's (pc-rel) */
-	RELOC_WDISP30,
-	RELOC_WDISP22,  /* SR word disp's */
-	RELOC_HI22,
-	RELOC_22,	/* SR 22-bit relocs */
-	RELOC_13,
-	RELOC_LO10,	/* SR 13&10-bit relocs */
-	RELOC_SFA_BASE,
-	RELOC_SFA_OFF13, /* SR S.F.A. relocs */
-	RELOC_BASE10,
-	RELOC_BASE13,
-	RELOC_BASE22,	/* base_relative pic */
-	RELOC_PC10,
-	RELOC_PC22,	/* special pc-rel pic */
-	RELOC_JMP_TBL,	/* jmp_tbl_rel in pic */
-	RELOC_SEGOFF16,	/* ShLib offset-in-seg */
-	RELOC_GLOB_DAT,
-	RELOC_JMP_SLOT,
-	RELOC_RELATIVE 	/* rtld relocs */
-};
-
-/*
- * Format of a relocation datum.
- */
-struct relocation_info /* used when header.a_machtype == M_SPARC */
-{
-        unsigned long   r_address;  /* relocation addr */
-        unsigned int    r_index:24; /* segment index or symbol index */
-        unsigned int    r_extern:1; /* if F, r_index==SEG#; if T, SYM idx */
-        int             r_pad:2;    /* <unused> */
-        enum reloc_type r_type:5;   /* type of relocation to perform */
-        long            r_addend;   /* addend for relocation value */
-};
-
-#define N_RELOCATION_INFO_DECLARED 1
-
-#ifdef __KERNEL__
-
-#include <asm/page.h>
-
-#define STACK_TOP	(PAGE_OFFSET - PAGE_SIZE)
-
-#endif /* __KERNEL__ */
-
-#endif /* __SPARC_A_OUT_H__ */
diff --git a/qemu/roms/openbios/include/arch/sparc32/asi.h b/qemu/roms/openbios/include/arch/sparc32/asi.h
deleted file mode 100644
index af3d69c13..000000000
--- a/qemu/roms/openbios/include/arch/sparc32/asi.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* $Id: asi.h,v 1.1 2002/07/12 17:06:36 zaitcev Exp $ */
-#ifndef _SPARC_ASI_H
-#define _SPARC_ASI_H
-
-/* asi.h:  Address Space Identifier values for the sparc.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- *
- * Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au)
- * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su>
- */
-
-/* The first batch are for the sun4c. */
-
-#define ASI_NULL1           0x00
-#define ASI_NULL2           0x01
-
-/* sun4c and sun4 control registers and mmu/vac ops */
-#define ASI_CONTROL         0x02
-#define ASI_SEGMAP          0x03
-#define ASI_PTE             0x04
-#define ASI_HWFLUSHSEG      0x05
-#define ASI_HWFLUSHPAGE     0x06
-#define ASI_REGMAP          0x06
-#define ASI_HWFLUSHCONTEXT  0x07
-
-#define ASI_USERTXT         0x08
-#define ASI_KERNELTXT       0x09
-#define ASI_USERDATA        0x0a
-#define ASI_KERNELDATA      0x0b
-
-/* VAC Cache flushing on sun4c and sun4 */
-#define ASI_FLUSHSEG        0x0c
-#define ASI_FLUSHPG         0x0d
-#define ASI_FLUSHCTX        0x0e
-
-/* SPARCstation-5: only 6 bits are decoded. */
-/* wo = Write Only, rw = Read Write;        */
-/* ss = Single Size, as = All Sizes;        */
-#define ASI_M_RES00         0x00   /* Don't touch... */
-#define ASI_M_UNA01         0x01   /* Same here... */
-#define ASI_M_MXCC          0x02   /* Access to TI VIKING MXCC registers */
-#define ASI_M_FLUSH_PROBE   0x03   /* Reference MMU Flush/Probe; rw, ss */
-#define ASI_M_MMUREGS       0x04   /* MMU Registers; rw, ss */
-#define ASI_M_TLBDIAG       0x05   /* MMU TLB only Diagnostics */
-#define ASI_M_DIAGS         0x06   /* Reference MMU Diagnostics */
-#define ASI_M_IODIAG        0x07   /* MMU I/O TLB only Diagnostics */
-#define ASI_M_USERTXT       0x08   /* Same as ASI_USERTXT; rw, as */
-#define ASI_M_KERNELTXT     0x09   /* Same as ASI_KERNELTXT; rw, as */
-#define ASI_M_USERDATA      0x0A   /* Same as ASI_USERDATA; rw, as */
-#define ASI_M_KERNELDATA    0x0B   /* Same as ASI_KERNELDATA; rw, as */
-#define ASI_M_TXTC_TAG      0x0C   /* Instruction Cache Tag; rw, ss */
-#define ASI_M_TXTC_DATA     0x0D   /* Instruction Cache Data; rw, ss */
-#define ASI_M_DATAC_TAG     0x0E   /* Data Cache Tag; rw, ss */
-#define ASI_M_DATAC_DATA    0x0F   /* Data Cache Data; rw, ss */
-
-/* The following cache flushing ASIs work only with the 'sta'
- * instruction. Results are unpredictable for 'swap' and 'ldstuba',
- * so don't do it.
- */
-
-/* These ASI flushes affect external caches too. */
-#define ASI_M_FLUSH_PAGE    0x10   /* Flush I&D Cache Line (page); wo, ss */
-#define ASI_M_FLUSH_SEG     0x11   /* Flush I&D Cache Line (seg); wo, ss */
-#define ASI_M_FLUSH_REGION  0x12   /* Flush I&D Cache Line (region); wo, ss */
-#define ASI_M_FLUSH_CTX     0x13   /* Flush I&D Cache Line (context); wo, ss */
-#define ASI_M_FLUSH_USER    0x14   /* Flush I&D Cache Line (user); wo, ss */
-
-/* Block-copy operations are available only on certain V8 cpus. */
-#define ASI_M_BCOPY         0x17   /* Block copy */
-
-/* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */
-#define ASI_M_IFLUSH_PAGE   0x18   /* Flush I Cache Line (page); wo, ss */
-#define ASI_M_IFLUSH_SEG    0x19   /* Flush I Cache Line (seg); wo, ss */
-#define ASI_M_IFLUSH_REGION 0x1A   /* Flush I Cache Line (region); wo, ss */
-#define ASI_M_IFLUSH_CTX    0x1B   /* Flush I Cache Line (context); wo, ss */
-#define ASI_M_IFLUSH_USER   0x1C   /* Flush I Cache Line (user); wo, ss */
-
-/* Block-fill operations are available on certain V8 cpus */
-#define ASI_M_BFILL         0x1F
-
-/* This allows direct access to main memory, actually 0x20 to 0x2f are
- * the available ASI's for physical ram pass-through, but I don't have
- * any idea what the other ones do....
- */
-
-#define ASI_M_BYPASS       0x20   /* Reference MMU bypass; rw, as */
-#define ASI_M_FBMEM        0x29   /* Graphics card frame buffer access */
-#define ASI_M_VMEUS        0x2A   /* VME user 16-bit access */
-#define ASI_M_VMEPS        0x2B   /* VME priv 16-bit access */
-#define ASI_M_VMEUT        0x2C   /* VME user 32-bit access */
-#define ASI_M_VMEPT        0x2D   /* VME priv 32-bit access */
-#define ASI_M_SBUS         0x2E   /* Direct SBus access */
-#define ASI_M_CTL          0x2F   /* Control Space (ECC and MXCC are here) */
-
-
-/* This is ROSS HyperSparc only. */
-#define ASI_M_FLUSH_IWHOLE 0x31   /* Flush entire ICACHE; wo, ss */
-
-/* Tsunami/Viking/TurboSparc i/d cache flash clear. */
-#define ASI_M_IC_FLCLEAR   0x36
-#define ASI_M_DC_FLCLEAR   0x37
-
-#define ASI_M_DCDR         0x39   /* Data Cache Diagnostics Register rw, ss */
-
-#define ASI_M_VIKING_TMP1  0x40	  /* Emulation temporary 1 on Viking */
-#define ASI_M_VIKING_TMP2  0x41	  /* Emulation temporary 2 on Viking */
-
-#define ASI_M_ACTION       0x4c   /* Breakpoint Action Register (GNU/Viking) */
-
-#endif /* _SPARC_ASI_H */
diff --git a/qemu/roms/openbios/include/arch/sparc32/crs.h b/qemu/roms/openbios/include/arch/sparc32/crs.h
deleted file mode 100644
index 7b4559372..000000000
--- a/qemu/roms/openbios/include/arch/sparc32/crs.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Parts of asm-sparc/contregs.h
- *
- * contregs.h:  Addresses of registers in the ASI_CONTROL alternate address
- *              space. These are for the mmu's context register, etc.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress        */
-#define AC_M_PCR      0x0000        /* shv Processor Control Reg             */
-#define AC_M_CTPR     0x0100        /* shv Context Table Pointer Reg         */
-#define AC_M_CXR      0x0200        /* shv Context Register                  */
-#define AC_M_SFSR     0x0300        /* shv Synchronous Fault Status Reg      */
-#define AC_M_SFAR     0x0400        /* shv Synchronous Fault Address Reg     */
diff --git a/qemu/roms/openbios/include/arch/sparc32/dma.h b/qemu/roms/openbios/include/arch/sparc32/dma.h
deleted file mode 100644
index e1310557b..000000000
--- a/qemu/roms/openbios/include/arch/sparc32/dma.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Local copy of include/asm-sparc/dma.h
- *
- * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
- */
-
-#ifndef _ASM_SPARC_DMA_H
-#define _ASM_SPARC_DMA_H
-
-/* #include <linux/kernel.h> */
-/* #include <linux/types.h> */
-typedef unsigned int __u32;
-
-/* These are irrelevant for Sparc DMA, but we leave it in so that
- * things can compile.
- */
-#define MAX_DMA_CHANNELS 8
-#define MAX_DMA_ADDRESS  (~0UL)
-#define DMA_MODE_READ    1
-#define DMA_MODE_WRITE   2
-
-/* Useful constants */
-#define SIZE_16MB      (16*1024*1024)
-#define SIZE_64K       (64*1024)
-
-/* Structure to describe the current status of DMA registers on the Sparc */
-struct sparc_dma_registers {
-  __volatile__ __u32 cond_reg;	/* DMA condition register */
-  __volatile__ __u32 st_addr;	/* Start address of this transfer */
-  __volatile__ __u32 cnt;	/* How many bytes to transfer */
-  __volatile__ __u32 dma_test;	/* DMA test register */
-};
-
-/* DVMA chip revisions */
-enum dvma_rev {
-	dvmarev0,
-	dvmaesc1,
-	dvmarev1,
-	dvmarev2,
-	dvmarev3,
-	dvmarevplus,
-	dvmahme
-};
-
-#define DMA_HASCOUNT(rev)  ((rev)==dvmaesc1)
-
-#if 0
-/* Linux DMA information structure, filled during probe. */
-struct Linux_SBus_DMA {
-	struct Linux_SBus_DMA *next;
-	struct linux_sbus_device *SBus_dev;
-	struct sparc_dma_registers *regs;
-
-	/* Status, misc info */
-	int node;                /* Prom node for this DMA device */
-	int running;             /* Are we doing DMA now? */
-	int allocated;           /* Are we "owned" by anyone yet? */
-
-	/* Transfer information. */
-	unsigned long addr;      /* Start address of current transfer */
-	int nbytes;              /* Size of current transfer */
-	int realbytes;           /* For splitting up large transfers, etc. */
-
-	/* DMA revision */
-	enum dvma_rev revision;
-};
-
-extern struct Linux_SBus_DMA *dma_chain;
-#endif
-
-/* Broken hardware... */
-/* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken?
- * Or is rev0 present only on sun4 boxes? -jj */
-#define DMA_ISBROKEN(dma)    ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1)
-#define DMA_ISESC1(dma)      ((dma)->revision == dvmaesc1)
-
-/* Fields in the cond_reg register */
-/* First, the version identification bits */
-#define DMA_DEVICE_ID    0xf0000000        /* Device identification bits */
-#define DMA_VERS0        0x00000000        /* Sunray DMA version */
-#define DMA_ESCV1        0x40000000        /* DMA ESC Version 1 */
-#define DMA_VERS1        0x80000000        /* DMA rev 1 */
-#define DMA_VERS2        0xa0000000        /* DMA rev 2 */
-#define DMA_VERHME       0xb0000000        /* DMA hme gate array */
-#define DMA_VERSPLUS     0x90000000        /* DMA rev 1 PLUS */
-
-#define DMA_HNDL_INTR    0x00000001        /* An IRQ needs to be handled */
-#define DMA_HNDL_ERROR   0x00000002        /* We need to take an error */
-#define DMA_FIFO_ISDRAIN 0x0000000c        /* The DMA FIFO is draining */
-#define DMA_INT_ENAB     0x00000010        /* Turn on interrupts */
-#define DMA_FIFO_INV     0x00000020        /* Invalidate the FIFO */
-#define DMA_ACC_SZ_ERR   0x00000040        /* The access size was bad */
-#define DMA_FIFO_STDRAIN 0x00000040        /* DMA_VERS1 Drain the FIFO */
-#define DMA_RST_SCSI     0x00000080        /* Reset the SCSI controller */
-#define DMA_RST_ENET     DMA_RST_SCSI      /* Reset the ENET controller */
-#define DMA_ST_WRITE     0x00000100        /* write from device to memory */
-#define DMA_ENABLE       0x00000200        /* Fire up DMA, handle requests */
-#define DMA_PEND_READ    0x00000400        /* DMA_VERS1/0/PLUS Pending Read */
-#define DMA_ESC_BURST    0x00000800        /* 1=16byte 0=32byte */
-#define DMA_READ_AHEAD   0x00001800        /* DMA read ahead partial longword */
-#define DMA_DSBL_RD_DRN  0x00001000        /* No EC drain on slave reads */
-#define DMA_BCNT_ENAB    0x00002000        /* If on, use the byte counter */
-#define DMA_TERM_CNTR    0x00004000        /* Terminal counter */
-#define DMA_SCSI_SBUS64  0x00008000        /* HME: Enable 64-bit SBUS mode. */
-#define DMA_CSR_DISAB    0x00010000        /* No FIFO drains during csr */
-#define DMA_SCSI_DISAB   0x00020000        /* No FIFO drains during reg */
-#define DMA_DSBL_WR_INV  0x00020000        /* No EC inval. on slave writes */
-#define DMA_ADD_ENABLE   0x00040000        /* Special ESC DVMA optimization */
-#define DMA_E_BURST8	 0x00040000	   /* ENET: SBUS r/w burst size */
-#define DMA_BRST_SZ      0x000c0000        /* SCSI: SBUS r/w burst size */
-#define DMA_BRST64       0x00080000        /* SCSI: 64byte bursts (HME on UltraSparc only) */
-#define DMA_BRST32       0x00040000        /* SCSI: 32byte bursts */
-#define DMA_BRST16       0x00000000        /* SCSI: 16byte bursts */
-#define DMA_BRST0        0x00080000        /* SCSI: no bursts (non-HME gate arrays) */
-#define DMA_ADDR_DISAB   0x00100000        /* No FIFO drains during addr */
-#define DMA_2CLKS        0x00200000        /* Each transfer = 2 clock ticks */
-#define DMA_3CLKS        0x00400000        /* Each transfer = 3 clock ticks */
-#define DMA_EN_ENETAUI   DMA_3CLKS         /* Put lance into AUI-cable mode */
-#define DMA_CNTR_DISAB   0x00800000        /* No IRQ when DMA_TERM_CNTR set */
-#define DMA_AUTO_NADDR   0x01000000        /* Use "auto nxt addr" feature */
-#define DMA_SCSI_ON      0x02000000        /* Enable SCSI dma */
-#define DMA_PARITY_OFF   0x02000000        /* HME: disable parity checking */
-#define DMA_LOADED_ADDR  0x04000000        /* Address has been loaded */
-#define DMA_LOADED_NADDR 0x08000000        /* Next address has been loaded */
-#define DMA_RESET_FAS366 0x08000000        /* HME: Assert RESET to FAS366 */
-
-/* Values describing the burst-size property from the PROM */
-#define DMA_BURST1       0x01
-#define DMA_BURST2       0x02
-#define DMA_BURST4       0x04
-#define DMA_BURST8       0x08
-#define DMA_BURST16      0x10
-#define DMA_BURST32      0x20
-#define DMA_BURST64      0x40
-#define DMA_BURSTBITS    0x7f
-
-/* Determine highest possible final transfer address given a base */
-#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
-
-/* Yes, I hack a lot of elisp in my spare time... */
-#define DMA_ERROR_P(regs)  ((((regs)->cond_reg) & DMA_HNDL_ERROR))
-#define DMA_IRQ_P(regs)    ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
-#define DMA_WRITE_P(regs)  ((((regs)->cond_reg) & DMA_ST_WRITE))
-#define DMA_OFF(regs)      ((((regs)->cond_reg) &= (~DMA_ENABLE)))
-#define DMA_INTSOFF(regs)  ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
-#define DMA_INTSON(regs)   ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
-#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
-#define DMA_SETSTART(regs, addr)  ((((regs)->st_addr) = (char *) addr))
-#define DMA_BEGINDMA_W(regs) \
-        ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
-#define DMA_BEGINDMA_R(regs) \
-        ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
-
-#if 0
-
-/* For certain DMA chips, we need to disable ints upon irq entry
- * and turn them back on when we are done.  So in any ESP interrupt
- * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
- * when leaving the handler.  You have been warned...
- */
-#define DMA_IRQ_ENTRY(dma, dregs) do { \
-        if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
-   } while (0)
-
-#define DMA_IRQ_EXIT(dma, dregs) do { \
-	if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
-   } while(0)
-
-
-/* Pause until counter runs out or BIT isn't set in the DMA condition
- * register.
- */
-extern __inline__ void sparc_dma_pause(struct sparc_dma_registers *regs,
-				       unsigned long bit)
-{
-	int ctr = 50000;   /* Let's find some bugs ;) */
-
-	/* Busy wait until the bit is not set any more */
-	while((regs->cond_reg&bit) && (ctr>0)) {
-		ctr--;
-		__delay(5);
-	}
-
-	/* Check for bogus outcome. */
-	if(!ctr)
-		panic("DMA timeout");
-}
-
-/* Reset the friggin' thing... */
-#define DMA_RESET(dma) do { \
-	struct sparc_dma_registers *regs = dma->regs;                      \
-	/* Let the current FIFO drain itself */                            \
-	sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN));                         \
-	/* Reset the logic */                                              \
-	regs->cond_reg |= (DMA_RST_SCSI);     /* assert */                 \
-	__delay(400);                         /* let the bits set ;) */    \
-	regs->cond_reg &= ~(DMA_RST_SCSI);    /* de-assert */              \
-	sparc_dma_enable_interrupts(regs);    /* Re-enable interrupts */   \
-	/* Enable FAST transfers if available */                           \
-	if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS;            \
-	dma->running = 0;                                                  \
-} while(0)
-
-#define for_each_dvma(dma) \
-        for((dma) = dma_chain; (dma); (dma) = (dma)->next)
-
-extern int get_dma_list(char *);
-extern int request_dma(unsigned int, __const__ char *);
-extern void free_dma(unsigned int);
-
-#endif
-
-#endif /* !(_ASM_SPARC_DMA_H) */
diff --git a/qemu/roms/openbios/include/arch/sparc32/elf.h b/qemu/roms/openbios/include/arch/sparc32/elf.h
deleted file mode 100644
index 8d429d7aa..000000000
--- a/qemu/roms/openbios/include/arch/sparc32/elf.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#define ARCH_ELF_CLASS ELFCLASS32
-#define ARCH_ELF_DATA ELFDATA2MSB
-#define ARCH_ELF_MACHINE_OK(x) ((x)==EM_SPARC || (x)==EM_SPARC32PLUS)
-typedef Elf32_Ehdr Elf_ehdr;
-typedef Elf32_Phdr Elf_phdr;
diff --git a/qemu/roms/openbios/include/arch/sparc32/io.h b/qemu/roms/openbios/include/arch/sparc32/io.h
deleted file mode 100644
index 011770ad1..000000000
--- a/qemu/roms/openbios/include/arch/sparc32/io.h
+++ /dev/null
@@ -1,201 +0,0 @@
-#ifndef _ASM_IO_H
-#define _ASM_IO_H
-
-#include "asm/types.h"
-
-extern unsigned int va_shift; // Set in entry.S
-
-// Defined in ldscript
-extern char _start, _data, _stack, _estack, _end, _vmem, _evmem, _iomem;
-
-// XXX check use and merge
-#define phys_to_virt(phys) ((void *) ((unsigned long) (phys)))
-#define virt_to_phys(virt) ((unsigned long) (virt))
-
-#ifndef BOOTSTRAP
-
-#ifndef _IO_BASE
-#define _IO_BASE	0
-#endif
-
-/*
- * The insw/outsw/insl/outsl macros don't do byte-swapping.
- * They are only used in practice for transferring buffers which
- * are arrays of bytes, and byte-swapping is not appropriate in
- * that case.  - paulus
- */
-#define insw(port, buf, ns)	_insw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns))
-#define outsw(port, buf, ns)	_outsw_ns((uint16_t *)((port)+_IO_BASE), (buf), (ns))
-
-#define inb(port)		in_8((uint8_t *)((port)+_IO_BASE))
-#define outb(val, port)		out_8((uint8_t *)((port)+_IO_BASE), (val))
-#define inw(port)		in_le16((uint16_t *)((port)+_IO_BASE))
-#define outw(val, port)		out_le16((uint16_t *)((port)+_IO_BASE), (val))
-#define inl(port)		in_le32((uint32_t *)((port)+_IO_BASE))
-#define outl(val, port)		out_le32((uint32_t *)((port)+_IO_BASE), (val))
-
-/*
- * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
- */
-static inline int in_8(volatile unsigned char *addr)
-{
-    int ret;
-
-    __asm__ __volatile__("ldub [%1], %0\n\t"
-                         "stbar\n\t"
-                         :"=r"(ret):"r"(addr):"memory");
-
-    return ret;
-}
-
-static inline void out_8(volatile unsigned char *addr, int val)
-{
-    __asm__ __volatile__("stb %0, [%1]\n\t"
-                         "stbar\n\t"
-                         : : "r"(val), "r"(addr):"memory");
-}
-
-static inline int in_le16(volatile unsigned short *addr)
-{
-    int ret;
-
-    // XXX
-    __asm__ __volatile__("lduh [%1], %0\n\t"
-                         "stbar\n\t"
-                         :"=r"(ret):"r"(addr):"memory");
-
-    return ret;
-}
-
-static inline int in_be16(volatile unsigned short *addr)
-{
-    int ret;
-
-    __asm__ __volatile__("lduh [%1], %0\n\t"
-                         "stbar\n\t"
-                         :"=r"(ret):"r"(addr):"memory");
-
-    return ret;
-}
-
-static inline void out_le16(volatile unsigned short *addr, int val)
-{
-    // XXX
-    __asm__ __volatile__("sth %0, [%1]\n\t"
-                         "stbar\n\t"
-                         : : "r"(val), "r"(addr):"memory");
-}
-
-static inline void out_be16(volatile unsigned short *addr, int val)
-{
-    __asm__ __volatile__("sth %0, [%1]\n\t"
-                         "stbar\n\t"
-                         : : "r"(val), "r"(addr):"memory");
-}
-
-static inline unsigned in_le32(volatile unsigned *addr)
-{
-    unsigned ret;
-
-    // XXX
-    __asm__ __volatile__("ld [%1], %0\n\t"
-                         "stbar\n\t"
-                         :"=r"(ret):"r"(addr):"memory");
-
-    return ret;
-}
-
-static inline unsigned in_be32(volatile unsigned *addr)
-{
-    unsigned ret;
-
-    __asm__ __volatile__("ld [%1], %0\n\t"
-                         "stbar\n\t"
-                         :"=r"(ret):"r"(addr):"memory");
-
-    return ret;
-}
-
-static inline void out_le32(volatile unsigned *addr, int val)
-{
-    // XXX
-    __asm__ __volatile__("st %0, [%1]\n\t"
-                         "stbar\n\t"
-                         : : "r"(val), "r"(addr):"memory");
-}
-
-static inline void out_be32(volatile unsigned *addr, int val)
-{
-    __asm__ __volatile__("st %0, [%1]\n\t"
-                         "stbar\n\t"
-                         : : "r"(val), "r"(addr):"memory");
-}
-
-static inline void _insw_ns(volatile uint16_t * port, void *buf, int ns)
-{
-	uint16_t *b = (uint16_t *) buf;
-
-	while (ns > 0) {
-		*b++ = in_le16(port);
-		ns--;
-	}
-}
-
-static inline void _outsw_ns(volatile uint16_t * port, const void *buf,
-			     int ns)
-{
-	uint16_t *b = (uint16_t *) buf;
-
-	while (ns > 0) {
-		out_le16(port, *b++);
-		ns--;
-	}
-}
-
-static inline void _insw(volatile uint16_t * port, void *buf, int ns)
-{
-	uint16_t *b = (uint16_t *) buf;
-
-	while (ns > 0) {
-		*b++ = in_be16(port);
-		ns--;
-	}
-}
-
-static inline void _outsw(volatile uint16_t * port, const void *buf,
-			  int ns)
-{
-	uint16_t *b = (uint16_t *) buf;
-
-	while (ns > 0) {
-		out_be16(port, *b++);
-		ns--;
-	}
-}
-#else /* BOOTSTRAP */
-#ifdef FCOMPILER
-#define inb(reg) ((u8)0xff)
-#define inw(reg) ((u16)0xffff)
-#define inl(reg) ((u32)0xffffffff)
-#define outb(reg, val) do{} while(0)
-#define outw(reg, val) do{} while(0)
-#define outl(reg, val) do{} while(0)
-#else
-extern u8 inb(u32 reg);
-extern u16 inw(u32 reg);
-extern u32 inl(u32 reg);
-extern void insw(u32 reg, void *addr, unsigned long count);
-extern void outb(u32 reg, u8 val);
-extern void outw(u32 reg, u16 val);
-extern void outl(u32 reg, u32 val);
-extern void outsw(u32 reg, const void *addr, unsigned long count);
-#endif
-#endif
-
-#if defined(CONFIG_QEMU)
-#define FW_CFG_ARCH_DEPTH        (FW_CFG_ARCH_LOCAL + 0x00)
-#define FW_CFG_ARCH_WIDTH        (FW_CFG_ARCH_LOCAL + 0x01)
-#define FW_CFG_ARCH_HEIGHT       (FW_CFG_ARCH_LOCAL + 0x02)
-#endif
-
-#endif /* _ASM_IO_H */
diff --git a/qemu/roms/openbios/include/arch/sparc32/ofmem_sparc32.h b/qemu/roms/openbios/include/arch/sparc32/ofmem_sparc32.h
deleted file mode 100644
index efc21b498..000000000
--- a/qemu/roms/openbios/include/arch/sparc32/ofmem_sparc32.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *	<ofmem_sparc32.h>
- *
- *	OF Memory manager
- *
- *   Copyright (C) 1999, 2002 Samuel Rydh (samuel@ibrium.se)
- *
- *   This program is free software; you can redistribute it and/or
- *   modify it under the terms of the GNU General Public License
- *   as published by the Free Software Foundation
- *
- */
-
-#ifndef _H_OFMEM_SPARC32
-#define _H_OFMEM_SPARC32
-
-#include "libopenbios/ofmem.h"
-
-#define OF_CODE_START 0xffd00000
-#define OFMEM_VIRT_TOP 0xfe000000
-
-struct mem;
-extern struct mem cdvmem;
-
-extern unsigned long *l1;
-extern unsigned long find_pte(unsigned long va, int alloc);
-
-void mem_init(struct mem *t, char *begin, char *limit);
-void *mem_alloc(struct mem *t, int size, int align);
-
-#endif   /* _H_OFMEM_SPARC32 */
\ No newline at end of file
diff --git a/qemu/roms/openbios/include/arch/sparc32/types.h b/qemu/roms/openbios/include/arch/sparc32/types.h
deleted file mode 100644
index 3f37d4e03..000000000
--- a/qemu/roms/openbios/include/arch/sparc32/types.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* tag: data types for forth engine
- *
- * Copyright (C) 2003-2005 Patrick Mauritz, Stefan Reinauer
- *
- * See the file "COPYING" for further information about
- * the copyright and warranty status of this work.
- */
-
-#ifndef __TYPES_H
-#define __TYPES_H
-
-#include "mconfig.h"
-
-#ifdef BOOTSTRAP
-#include <inttypes.h>
-#else
-typedef unsigned char   uint8_t;
-typedef unsigned short  uint16_t;
-typedef unsigned int    uint32_t;
-typedef unsigned long long uint64_t;
-typedef unsigned long   uintptr_t;
-
-typedef signed char     int8_t;
-typedef short           int16_t;
-typedef int             int32_t;
-typedef long long       int64_t;
-typedef long            intptr_t;
-
-#define PRId32 "d"
-#define PRIu32 "u"
-#define PRIx32 "x"
-#define PRIX32 "X"
-#define PRId64 "lld"
-#define PRIu64 "llu"
-#define PRIx64 "llx"
-#define PRIX64 "llX"
-#endif
-
-/* endianess */
-#include "autoconf.h"
-
-/* physical address: 36 bits */
-
-typedef uint64_t phys_addr_t;
-
-#define FMT_plx "%09" PRIx64
-
-/* cell based types */
-
-typedef int32_t		cell;
-typedef uint32_t	ucell;
-typedef long long       dcell;
-typedef unsigned long long ducell;
-
-#define FMT_cell    "%" PRId32
-#define FMT_ucell   "%" PRIu32
-#define FMT_ucellx  "%08" PRIx32
-#define FMT_ucellX  "%08" PRIX32
-
-typedef int32_t         prom_arg_t;
-typedef uint32_t        prom_uarg_t;
-
-#define PRIdPROMARG     PRId32
-#define PRIuPROMARG     PRIu32
-#define PRIxPROMARG     PRIx32
-#define FMT_prom_arg    "%" PRIdPROMARG
-#define FMT_prom_uarg   "%" PRIuPROMARG
-#define FMT_prom_uargx  "%08" PRIxPROMARG
-
-#define FMT_elf     "%#x"
-#define FMT_sizet   "%lx"
-#define FMT_aout_ehdr  "%lx"
-
-#define bitspercell	(sizeof(cell)<<3)
-#define bitsperdcell	(sizeof(dcell)<<3)
-
-#define BITS		32
-
-#define PAGE_SHIFT	12
-
-/* size named types */
-
-typedef unsigned char   u8;
-typedef unsigned short u16;
-typedef unsigned int   u32;
-typedef unsigned long long u64;
-
-typedef signed char	s8;
-typedef short		s16;
-typedef int		s32;
-typedef long long	s64;
-
-#endif