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authorDon Dugger <n0ano@n0ano.com>2016-06-03 03:33:22 +0000
committerGerrit Code Review <gerrit@172.30.200.206>2016-06-03 03:33:23 +0000
commitda27230f80795d0028333713f036d44c53cb0e68 (patch)
treeb3d379eaf000adf72b36cb01cdf4d79c3e3f064c /qemu/hw/dma
parent0e68cb048bb8aadb14675f5d4286d8ab2fc35449 (diff)
parent437fd90c0250dee670290f9b714253671a990160 (diff)
Merge "These changes are the raw update to qemu-2.6."
Diffstat (limited to 'qemu/hw/dma')
-rw-r--r--qemu/hw/dma/Makefile.objs1
-rw-r--r--qemu/hw/dma/bcm2835_dma.c409
-rw-r--r--qemu/hw/dma/etraxfs_dma.c16
-rw-r--r--qemu/hw/dma/i82374.c62
-rw-r--r--qemu/hw/dma/i8257.c415
-rw-r--r--qemu/hw/dma/omap_dma.c7
-rw-r--r--qemu/hw/dma/pl080.c1
-rw-r--r--qemu/hw/dma/pl330.c2
-rw-r--r--qemu/hw/dma/puv3_dma.c1
-rw-r--r--qemu/hw/dma/pxa2xx_dma.c4
-rw-r--r--qemu/hw/dma/rc4030.c3
-rw-r--r--qemu/hw/dma/soc_dma.c40
-rw-r--r--qemu/hw/dma/sparc32_dma.c1
-rw-r--r--qemu/hw/dma/sun4m_iommu.c1
-rw-r--r--qemu/hw/dma/xilinx_axidma.c14
15 files changed, 703 insertions, 274 deletions
diff --git a/qemu/hw/dma/Makefile.objs b/qemu/hw/dma/Makefile.objs
index 0e65ed0d7..a1abbcf74 100644
--- a/qemu/hw/dma/Makefile.objs
+++ b/qemu/hw/dma/Makefile.objs
@@ -11,3 +11,4 @@ common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o
obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o
+obj-$(CONFIG_RASPI) += bcm2835_dma.o
diff --git a/qemu/hw/dma/bcm2835_dma.c b/qemu/hw/dma/bcm2835_dma.c
new file mode 100644
index 000000000..542117599
--- /dev/null
+++ b/qemu/hw/dma/bcm2835_dma.c
@@ -0,0 +1,409 @@
+/*
+ * Raspberry Pi emulation (c) 2012 Gregory Estrade
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/dma/bcm2835_dma.h"
+
+/* DMA CS Control and Status bits */
+#define BCM2708_DMA_ACTIVE (1 << 0)
+#define BCM2708_DMA_END (1 << 1) /* GE */
+#define BCM2708_DMA_INT (1 << 2)
+#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
+#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
+#define BCM2708_DMA_ERR (1 << 8)
+#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
+#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
+
+/* DMA control block "info" field bits */
+#define BCM2708_DMA_INT_EN (1 << 0)
+#define BCM2708_DMA_TDMODE (1 << 1)
+#define BCM2708_DMA_WAIT_RESP (1 << 3)
+#define BCM2708_DMA_D_INC (1 << 4)
+#define BCM2708_DMA_D_WIDTH (1 << 5)
+#define BCM2708_DMA_D_DREQ (1 << 6)
+#define BCM2708_DMA_D_IGNORE (1 << 7)
+#define BCM2708_DMA_S_INC (1 << 8)
+#define BCM2708_DMA_S_WIDTH (1 << 9)
+#define BCM2708_DMA_S_DREQ (1 << 10)
+#define BCM2708_DMA_S_IGNORE (1 << 11)
+
+/* Register offsets */
+#define BCM2708_DMA_CS 0x00 /* Control and Status */
+#define BCM2708_DMA_ADDR 0x04 /* Control block address */
+/* the current control block appears in the following registers - read only */
+#define BCM2708_DMA_INFO 0x08
+#define BCM2708_DMA_SOURCE_AD 0x0c
+#define BCM2708_DMA_DEST_AD 0x10
+#define BCM2708_DMA_TXFR_LEN 0x14
+#define BCM2708_DMA_STRIDE 0x18
+#define BCM2708_DMA_NEXTCB 0x1C
+#define BCM2708_DMA_DEBUG 0x20
+
+#define BCM2708_DMA_INT_STATUS 0xfe0 /* Interrupt status of each channel */
+#define BCM2708_DMA_ENABLE 0xff0 /* Global enable bits for each channel */
+
+#define BCM2708_DMA_CS_RW_MASK 0x30ff0001 /* All RW bits in DMA_CS */
+
+static void bcm2835_dma_update(BCM2835DMAState *s, unsigned c)
+{
+ BCM2835DMAChan *ch = &s->chan[c];
+ uint32_t data, xlen, ylen;
+ int16_t dst_stride, src_stride;
+
+ if (!(s->enable & (1 << c))) {
+ return;
+ }
+
+ while ((s->enable & (1 << c)) && (ch->conblk_ad != 0)) {
+ /* CB fetch */
+ ch->ti = ldl_le_phys(&s->dma_as, ch->conblk_ad);
+ ch->source_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 4);
+ ch->dest_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 8);
+ ch->txfr_len = ldl_le_phys(&s->dma_as, ch->conblk_ad + 12);
+ ch->stride = ldl_le_phys(&s->dma_as, ch->conblk_ad + 16);
+ ch->nextconbk = ldl_le_phys(&s->dma_as, ch->conblk_ad + 20);
+
+ if (ch->ti & BCM2708_DMA_TDMODE) {
+ /* 2D transfer mode */
+ ylen = (ch->txfr_len >> 16) & 0x3fff;
+ xlen = ch->txfr_len & 0xffff;
+ dst_stride = ch->stride >> 16;
+ src_stride = ch->stride & 0xffff;
+ } else {
+ ylen = 1;
+ xlen = ch->txfr_len;
+ dst_stride = 0;
+ src_stride = 0;
+ }
+
+ while (ylen != 0) {
+ /* Normal transfer mode */
+ while (xlen != 0) {
+ if (ch->ti & BCM2708_DMA_S_IGNORE) {
+ /* Ignore reads */
+ data = 0;
+ } else {
+ data = ldl_le_phys(&s->dma_as, ch->source_ad);
+ }
+ if (ch->ti & BCM2708_DMA_S_INC) {
+ ch->source_ad += 4;
+ }
+
+ if (ch->ti & BCM2708_DMA_D_IGNORE) {
+ /* Ignore writes */
+ } else {
+ stl_le_phys(&s->dma_as, ch->dest_ad, data);
+ }
+ if (ch->ti & BCM2708_DMA_D_INC) {
+ ch->dest_ad += 4;
+ }
+
+ /* update remaining transfer length */
+ xlen -= 4;
+ if (ch->ti & BCM2708_DMA_TDMODE) {
+ ch->txfr_len = (ylen << 16) | xlen;
+ } else {
+ ch->txfr_len = xlen;
+ }
+ }
+
+ if (--ylen != 0) {
+ ch->source_ad += src_stride;
+ ch->dest_ad += dst_stride;
+ }
+ }
+ ch->cs |= BCM2708_DMA_END;
+ if (ch->ti & BCM2708_DMA_INT_EN) {
+ ch->cs |= BCM2708_DMA_INT;
+ s->int_status |= (1 << c);
+ qemu_set_irq(ch->irq, 1);
+ }
+
+ /* Process next CB */
+ ch->conblk_ad = ch->nextconbk;
+ }
+
+ ch->cs &= ~BCM2708_DMA_ACTIVE;
+ ch->cs |= BCM2708_DMA_ISPAUSED;
+}
+
+static void bcm2835_dma_chan_reset(BCM2835DMAChan *ch)
+{
+ ch->cs = 0;
+ ch->conblk_ad = 0;
+}
+
+static uint64_t bcm2835_dma_read(BCM2835DMAState *s, hwaddr offset,
+ unsigned size, unsigned c)
+{
+ BCM2835DMAChan *ch;
+ uint32_t res = 0;
+
+ assert(size == 4);
+ assert(c < BCM2835_DMA_NCHANS);
+
+ ch = &s->chan[c];
+
+ switch (offset) {
+ case BCM2708_DMA_CS:
+ res = ch->cs;
+ break;
+ case BCM2708_DMA_ADDR:
+ res = ch->conblk_ad;
+ break;
+ case BCM2708_DMA_INFO:
+ res = ch->ti;
+ break;
+ case BCM2708_DMA_SOURCE_AD:
+ res = ch->source_ad;
+ break;
+ case BCM2708_DMA_DEST_AD:
+ res = ch->dest_ad;
+ break;
+ case BCM2708_DMA_TXFR_LEN:
+ res = ch->txfr_len;
+ break;
+ case BCM2708_DMA_STRIDE:
+ res = ch->stride;
+ break;
+ case BCM2708_DMA_NEXTCB:
+ res = ch->nextconbk;
+ break;
+ case BCM2708_DMA_DEBUG:
+ res = ch->debug;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
+ __func__, offset);
+ break;
+ }
+ return res;
+}
+
+static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset,
+ uint64_t value, unsigned size, unsigned c)
+{
+ BCM2835DMAChan *ch;
+ uint32_t oldcs;
+
+ assert(size == 4);
+ assert(c < BCM2835_DMA_NCHANS);
+
+ ch = &s->chan[c];
+
+ switch (offset) {
+ case BCM2708_DMA_CS:
+ oldcs = ch->cs;
+ if (value & BCM2708_DMA_RESET) {
+ bcm2835_dma_chan_reset(ch);
+ }
+ if (value & BCM2708_DMA_ABORT) {
+ /* abort is a no-op, since we always run to completion */
+ }
+ if (value & BCM2708_DMA_END) {
+ ch->cs &= ~BCM2708_DMA_END;
+ }
+ if (value & BCM2708_DMA_INT) {
+ ch->cs &= ~BCM2708_DMA_INT;
+ s->int_status &= ~(1 << c);
+ qemu_set_irq(ch->irq, 0);
+ }
+ ch->cs &= ~BCM2708_DMA_CS_RW_MASK;
+ ch->cs |= (value & BCM2708_DMA_CS_RW_MASK);
+ if (!(oldcs & BCM2708_DMA_ACTIVE) && (ch->cs & BCM2708_DMA_ACTIVE)) {
+ bcm2835_dma_update(s, c);
+ }
+ break;
+ case BCM2708_DMA_ADDR:
+ ch->conblk_ad = value;
+ break;
+ case BCM2708_DMA_DEBUG:
+ ch->debug = value;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
+ __func__, offset);
+ break;
+ }
+}
+
+static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size)
+{
+ BCM2835DMAState *s = opaque;
+
+ if (offset < 0xf00) {
+ return bcm2835_dma_read(s, (offset & 0xff), size, (offset >> 8) & 0xf);
+ } else {
+ switch (offset) {
+ case BCM2708_DMA_INT_STATUS:
+ return s->int_status;
+ case BCM2708_DMA_ENABLE:
+ return s->enable;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
+ __func__, offset);
+ return 0;
+ }
+ }
+}
+
+static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset, unsigned size)
+{
+ return bcm2835_dma_read(opaque, (offset & 0xff), size, 15);
+}
+
+static void bcm2835_dma0_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ BCM2835DMAState *s = opaque;
+
+ if (offset < 0xf00) {
+ bcm2835_dma_write(s, (offset & 0xff), value, size, (offset >> 8) & 0xf);
+ } else {
+ switch (offset) {
+ case BCM2708_DMA_INT_STATUS:
+ break;
+ case BCM2708_DMA_ENABLE:
+ s->enable = (value & 0xffff);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
+ __func__, offset);
+ }
+ }
+
+}
+
+static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ bcm2835_dma_write(opaque, (offset & 0xff), value, size, 15);
+}
+
+static const MemoryRegionOps bcm2835_dma0_ops = {
+ .read = bcm2835_dma0_read,
+ .write = bcm2835_dma0_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+};
+
+static const MemoryRegionOps bcm2835_dma15_ops = {
+ .read = bcm2835_dma15_read,
+ .write = bcm2835_dma15_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+};
+
+static const VMStateDescription vmstate_bcm2835_dma_chan = {
+ .name = TYPE_BCM2835_DMA "-chan",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(cs, BCM2835DMAChan),
+ VMSTATE_UINT32(conblk_ad, BCM2835DMAChan),
+ VMSTATE_UINT32(ti, BCM2835DMAChan),
+ VMSTATE_UINT32(source_ad, BCM2835DMAChan),
+ VMSTATE_UINT32(dest_ad, BCM2835DMAChan),
+ VMSTATE_UINT32(txfr_len, BCM2835DMAChan),
+ VMSTATE_UINT32(stride, BCM2835DMAChan),
+ VMSTATE_UINT32(nextconbk, BCM2835DMAChan),
+ VMSTATE_UINT32(debug, BCM2835DMAChan),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_bcm2835_dma = {
+ .name = TYPE_BCM2835_DMA,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(chan, BCM2835DMAState, BCM2835_DMA_NCHANS, 1,
+ vmstate_bcm2835_dma_chan, BCM2835DMAChan),
+ VMSTATE_UINT32(int_status, BCM2835DMAState),
+ VMSTATE_UINT32(enable, BCM2835DMAState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void bcm2835_dma_init(Object *obj)
+{
+ BCM2835DMAState *s = BCM2835_DMA(obj);
+ int n;
+
+ /* DMA channels 0-14 occupy a contiguous block of IO memory, along
+ * with the global enable and interrupt status bits. Channel 15
+ * has the same register map, but is mapped at a discontiguous
+ * address in a separate IO block.
+ */
+ memory_region_init_io(&s->iomem0, OBJECT(s), &bcm2835_dma0_ops, s,
+ TYPE_BCM2835_DMA, 0x1000);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem0);
+
+ memory_region_init_io(&s->iomem15, OBJECT(s), &bcm2835_dma15_ops, s,
+ TYPE_BCM2835_DMA "-chan15", 0x100);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem15);
+
+ for (n = 0; n < 16; n++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(s), &s->chan[n].irq);
+ }
+}
+
+static void bcm2835_dma_reset(DeviceState *dev)
+{
+ BCM2835DMAState *s = BCM2835_DMA(dev);
+ int n;
+
+ s->enable = 0xffff;
+ s->int_status = 0;
+ for (n = 0; n < BCM2835_DMA_NCHANS; n++) {
+ bcm2835_dma_chan_reset(&s->chan[n]);
+ }
+}
+
+static void bcm2835_dma_realize(DeviceState *dev, Error **errp)
+{
+ BCM2835DMAState *s = BCM2835_DMA(dev);
+ Error *err = NULL;
+ Object *obj;
+
+ obj = object_property_get_link(OBJECT(dev), "dma-mr", &err);
+ if (obj == NULL) {
+ error_setg(errp, "%s: required dma-mr link not found: %s",
+ __func__, error_get_pretty(err));
+ return;
+ }
+
+ s->dma_mr = MEMORY_REGION(obj);
+ address_space_init(&s->dma_as, s->dma_mr, NULL);
+
+ bcm2835_dma_reset(dev);
+}
+
+static void bcm2835_dma_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = bcm2835_dma_realize;
+ dc->reset = bcm2835_dma_reset;
+ dc->vmsd = &vmstate_bcm2835_dma;
+}
+
+static TypeInfo bcm2835_dma_info = {
+ .name = TYPE_BCM2835_DMA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(BCM2835DMAState),
+ .class_init = bcm2835_dma_class_init,
+ .instance_init = bcm2835_dma_init,
+};
+
+static void bcm2835_dma_register_types(void)
+{
+ type_register_static(&bcm2835_dma_info);
+}
+
+type_init(bcm2835_dma_register_types)
diff --git a/qemu/hw/dma/etraxfs_dma.c b/qemu/hw/dma/etraxfs_dma.c
index 359951341..d5650eb88 100644
--- a/qemu/hw/dma/etraxfs_dma.c
+++ b/qemu/hw/dma/etraxfs_dma.c
@@ -21,8 +21,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include <stdio.h>
-#include <sys/time.h>
+#include "qemu/osdep.h"
#include "hw/hw.h"
#include "exec/address-spaces.h"
#include "qemu-common.h"
@@ -441,13 +440,16 @@ static int channel_out_run(struct fs_dma_ctrl *ctrl, int c)
D(printf("channel %d pushes %x %u bytes eop=%u\n", c,
saved_data_buf, len, out_eop));
- if (ctrl->channels[c].client->client.push)
- ctrl->channels[c].client->client.push(
- ctrl->channels[c].client->client.opaque,
- buf, len, out_eop);
- else
+ if (ctrl->channels[c].client->client.push) {
+ if (len > 0) {
+ ctrl->channels[c].client->client.push(
+ ctrl->channels[c].client->client.opaque,
+ buf, len, out_eop);
+ }
+ } else {
printf("WARNING: DMA ch%d dataloss,"
" no attached client.\n", c);
+ }
saved_data_buf += len;
diff --git a/qemu/hw/dma/i82374.c b/qemu/hw/dma/i82374.c
index b8ad2e64e..6c0f975df 100644
--- a/qemu/hw/dma/i82374.c
+++ b/qemu/hw/dma/i82374.c
@@ -22,8 +22,12 @@
* THE SOFTWARE.
*/
+#include "qemu/osdep.h"
#include "hw/isa/isa.h"
+#define TYPE_I82374 "i82374"
+#define I82374(obj) OBJECT_CHECK(I82374State, (obj), TYPE_I82374)
+
//#define DEBUG_I82374
#ifdef DEBUG_I82374
@@ -37,8 +41,10 @@ do {} while (0)
do { fprintf(stderr, "i82374 ERROR: " fmt , ## __VA_ARGS__); } while (0)
typedef struct I82374State {
+ ISADevice parent_obj;
+
+ uint32_t iobase;
uint8_t commands[8];
- qemu_irq out;
PortioList port_list;
} I82374State;
@@ -99,32 +105,6 @@ static uint32_t i82374_read_descriptor(void *opaque, uint32_t nport)
return val;
}
-static void i82374_realize(I82374State *s, Error **errp)
-{
- DMA_init(1, &s->out);
- memset(s->commands, 0, sizeof(s->commands));
-}
-
-#define TYPE_I82374 "i82374"
-#define I82374(obj) OBJECT_CHECK(ISAi82374State, (obj), TYPE_I82374)
-
-typedef struct ISAi82374State {
- ISADevice parent_obj;
-
- uint32_t iobase;
- I82374State state;
-} ISAi82374State;
-
-static const VMStateDescription vmstate_isa_i82374 = {
- .name = "isa-i82374",
- .version_id = 0,
- .minimum_version_id = 0,
- .fields = (VMStateField[]) {
- VMSTATE_STRUCT(state, ISAi82374State, 0, vmstate_i82374, I82374State),
- VMSTATE_END_OF_LIST()
- },
-};
-
static const MemoryRegionPortio i82374_portio_list[] = {
{ 0x0A, 1, 1, .read = i82374_read_isr, },
{ 0x10, 8, 1, .write = i82374_write_command, },
@@ -134,23 +114,21 @@ static const MemoryRegionPortio i82374_portio_list[] = {
PORTIO_END_OF_LIST(),
};
-static void i82374_isa_realize(DeviceState *dev, Error **errp)
+static void i82374_realize(DeviceState *dev, Error **errp)
{
- ISAi82374State *isa = I82374(dev);
- I82374State *s = &isa->state;
+ I82374State *s = I82374(dev);
- portio_list_init(&s->port_list, OBJECT(isa), i82374_portio_list, s,
+ portio_list_init(&s->port_list, OBJECT(s), i82374_portio_list, s,
"i82374");
- portio_list_add(&s->port_list, isa_address_space_io(&isa->parent_obj),
- isa->iobase);
-
- i82374_realize(s, errp);
+ portio_list_add(&s->port_list, isa_address_space_io(&s->parent_obj),
+ s->iobase);
- qdev_init_gpio_out(dev, &s->out, 1);
+ DMA_init(isa_bus_from_device(ISA_DEVICE(dev)), 1);
+ memset(s->commands, 0, sizeof(s->commands));
}
static Property i82374_properties[] = {
- DEFINE_PROP_UINT32("iobase", ISAi82374State, iobase, 0x400),
+ DEFINE_PROP_UINT32("iobase", I82374State, iobase, 0x400),
DEFINE_PROP_END_OF_LIST()
};
@@ -158,21 +136,21 @@ static void i82374_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->realize = i82374_isa_realize;
- dc->vmsd = &vmstate_isa_i82374;
+ dc->realize = i82374_realize;
+ dc->vmsd = &vmstate_i82374;
dc->props = i82374_properties;
}
-static const TypeInfo i82374_isa_info = {
+static const TypeInfo i82374_info = {
.name = TYPE_I82374,
.parent = TYPE_ISA_DEVICE,
- .instance_size = sizeof(ISAi82374State),
+ .instance_size = sizeof(I82374State),
.class_init = i82374_class_init,
};
static void i82374_register_types(void)
{
- type_register_static(&i82374_isa_info);
+ type_register_static(&i82374_info);
}
type_init(i82374_register_types)
diff --git a/qemu/hw/dma/i8257.c b/qemu/hw/dma/i8257.c
index a414029be..f345c5476 100644
--- a/qemu/hw/dma/i8257.c
+++ b/qemu/hw/dma/i8257.c
@@ -21,11 +21,16 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
+#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/isa/isa.h"
+#include "hw/isa/i8257.h"
#include "qemu/main-loop.h"
#include "trace.h"
+#define I8257(obj) \
+ OBJECT_CHECK(I8257State, (obj), TYPE_I8257)
+
/* #define DEBUG_DMA */
#define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
@@ -37,33 +42,9 @@
#define ldebug(...)
#endif
-struct dma_regs {
- int now[2];
- uint16_t base[2];
- uint8_t mode;
- uint8_t page;
- uint8_t pageh;
- uint8_t dack;
- uint8_t eop;
- DMA_transfer_handler transfer_handler;
- void *opaque;
-};
-
#define ADDR 0
#define COUNT 1
-static struct dma_cont {
- uint8_t status;
- uint8_t command;
- uint8_t mask;
- uint8_t flip_flop;
- int dshift;
- struct dma_regs regs[4];
- qemu_irq *cpu_request_exit;
- MemoryRegion channel_io;
- MemoryRegion cont_io;
-} dma_controllers[2];
-
enum {
CMD_MEMORY_TO_MEMORY = 0x01,
CMD_FIXED_ADDRESS = 0x02,
@@ -79,13 +60,13 @@ enum {
};
-static void DMA_run (void);
+static void i8257_dma_run(void *opaque);
-static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
+static const int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
-static void write_page (void *opaque, uint32_t nport, uint32_t data)
+static void i8257_write_page(void *opaque, uint32_t nport, uint32_t data)
{
- struct dma_cont *d = opaque;
+ I8257State *d = opaque;
int ichan;
ichan = channels[nport & 7];
@@ -96,9 +77,9 @@ static void write_page (void *opaque, uint32_t nport, uint32_t data)
d->regs[ichan].page = data;
}
-static void write_pageh (void *opaque, uint32_t nport, uint32_t data)
+static void i8257_write_pageh(void *opaque, uint32_t nport, uint32_t data)
{
- struct dma_cont *d = opaque;
+ I8257State *d = opaque;
int ichan;
ichan = channels[nport & 7];
@@ -109,9 +90,9 @@ static void write_pageh (void *opaque, uint32_t nport, uint32_t data)
d->regs[ichan].pageh = data;
}
-static uint32_t read_page (void *opaque, uint32_t nport)
+static uint32_t i8257_read_page(void *opaque, uint32_t nport)
{
- struct dma_cont *d = opaque;
+ I8257State *d = opaque;
int ichan;
ichan = channels[nport & 7];
@@ -122,9 +103,9 @@ static uint32_t read_page (void *opaque, uint32_t nport)
return d->regs[ichan].page;
}
-static uint32_t read_pageh (void *opaque, uint32_t nport)
+static uint32_t i8257_read_pageh(void *opaque, uint32_t nport)
{
- struct dma_cont *d = opaque;
+ I8257State *d = opaque;
int ichan;
ichan = channels[nport & 7];
@@ -135,16 +116,16 @@ static uint32_t read_pageh (void *opaque, uint32_t nport)
return d->regs[ichan].pageh;
}
-static inline void init_chan (struct dma_cont *d, int ichan)
+static inline void i8257_init_chan(I8257State *d, int ichan)
{
- struct dma_regs *r;
+ I8257Regs *r;
r = d->regs + ichan;
r->now[ADDR] = r->base[ADDR] << d->dshift;
r->now[COUNT] = 0;
}
-static inline int getff (struct dma_cont *d)
+static inline int i8257_getff(I8257State *d)
{
int ff;
@@ -153,11 +134,11 @@ static inline int getff (struct dma_cont *d)
return ff;
}
-static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size)
+static uint64_t i8257_read_chan(void *opaque, hwaddr nport, unsigned size)
{
- struct dma_cont *d = opaque;
+ I8257State *d = opaque;
int ichan, nreg, iport, ff, val, dir;
- struct dma_regs *r;
+ I8257Regs *r;
iport = (nport >> d->dshift) & 0x0f;
ichan = iport >> 1;
@@ -165,7 +146,7 @@ static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size)
r = d->regs + ichan;
dir = ((r->mode >> 5) & 1) ? -1 : 1;
- ff = getff (d);
+ ff = i8257_getff(d);
if (nreg)
val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
else
@@ -175,29 +156,29 @@ static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size)
return (val >> (d->dshift + (ff << 3))) & 0xff;
}
-static void write_chan(void *opaque, hwaddr nport, uint64_t data,
- unsigned size)
+static void i8257_write_chan(void *opaque, hwaddr nport, uint64_t data,
+ unsigned int size)
{
- struct dma_cont *d = opaque;
+ I8257State *d = opaque;
int iport, ichan, nreg;
- struct dma_regs *r;
+ I8257Regs *r;
iport = (nport >> d->dshift) & 0x0f;
ichan = iport >> 1;
nreg = iport & 1;
r = d->regs + ichan;
- if (getff (d)) {
+ if (i8257_getff(d)) {
r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
- init_chan (d, ichan);
+ i8257_init_chan(d, ichan);
} else {
r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
}
}
-static void write_cont(void *opaque, hwaddr nport, uint64_t data,
- unsigned size)
+static void i8257_write_cont(void *opaque, hwaddr nport, uint64_t data,
+ unsigned int size)
{
- struct dma_cont *d = opaque;
+ I8257State *d = opaque;
int iport, ichan = 0;
iport = (nport >> d->dshift) & 0x0f;
@@ -219,7 +200,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data,
d->status &= ~(1 << (ichan + 4));
}
d->status &= ~(1 << ichan);
- DMA_run();
+ i8257_dma_run(d);
break;
case 0x02: /* single mask */
@@ -227,7 +208,7 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data,
d->mask |= 1 << (data & 3);
else
d->mask &= ~(1 << (data & 3));
- DMA_run();
+ i8257_dma_run(d);
break;
case 0x03: /* mode */
@@ -262,12 +243,12 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data,
case 0x06: /* clear mask for all channels */
d->mask = 0;
- DMA_run();
+ i8257_dma_run(d);
break;
case 0x07: /* write mask for all channels */
d->mask = data;
- DMA_run();
+ i8257_dma_run(d);
break;
default:
@@ -283,9 +264,9 @@ static void write_cont(void *opaque, hwaddr nport, uint64_t data,
#endif
}
-static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size)
+static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned size)
{
- struct dma_cont *d = opaque;
+ I8257State *d = opaque;
int iport, val;
iport = (nport >> d->dshift) & 0x0f;
@@ -306,37 +287,43 @@ static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size)
return val;
}
-int DMA_get_channel_mode (int nchan)
+static IsaDmaTransferMode i8257_dma_get_transfer_mode(IsaDma *obj, int nchan)
{
- return dma_controllers[nchan > 3].regs[nchan & 3].mode;
+ I8257State *d = I8257(obj);
+ return (d->regs[nchan & 3].mode >> 2) & 3;
}
-void DMA_hold_DREQ (int nchan)
+static bool i8257_dma_has_autoinitialization(IsaDma *obj, int nchan)
{
- int ncont, ichan;
+ I8257State *d = I8257(obj);
+ return (d->regs[nchan & 3].mode >> 4) & 1;
+}
+
+static void i8257_dma_hold_DREQ(IsaDma *obj, int nchan)
+{
+ I8257State *d = I8257(obj);
+ int ichan;
- ncont = nchan > 3;
ichan = nchan & 3;
- linfo ("held cont=%d chan=%d\n", ncont, ichan);
- dma_controllers[ncont].status |= 1 << (ichan + 4);
- DMA_run();
+ d->status |= 1 << (ichan + 4);
+ i8257_dma_run(d);
}
-void DMA_release_DREQ (int nchan)
+static void i8257_dma_release_DREQ(IsaDma *obj, int nchan)
{
- int ncont, ichan;
+ I8257State *d = I8257(obj);
+ int ichan;
- ncont = nchan > 3;
ichan = nchan & 3;
- linfo ("released cont=%d chan=%d\n", ncont, ichan);
- dma_controllers[ncont].status &= ~(1 << (ichan + 4));
- DMA_run();
+ d->status &= ~(1 << (ichan + 4));
+ i8257_dma_run(d);
}
-static void channel_run (int ncont, int ichan)
+static void i8257_channel_run(I8257State *d, int ichan)
{
+ int ncont = d->dshift;
int n;
- struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
+ I8257Regs *r = &d->regs[ichan];
#ifdef DEBUG_DMA
int dir, opmode;
@@ -355,68 +342,64 @@ static void channel_run (int ncont, int ichan)
r->now[COUNT], (r->base[COUNT] + 1) << ncont);
r->now[COUNT] = n;
ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
+ if (n == (r->base[COUNT] + 1) << ncont) {
+ ldebug("transfer done\n");
+ d->status |= (1 << ichan);
+ }
}
-static QEMUBH *dma_bh;
-
-static void DMA_run (void)
+static void i8257_dma_run(void *opaque)
{
- struct dma_cont *d;
- int icont, ichan;
+ I8257State *d = opaque;
+ int ichan;
int rearm = 0;
- static int running = 0;
- if (running) {
+ if (d->running) {
rearm = 1;
goto out;
} else {
- running = 1;
+ d->running = 1;
}
- d = dma_controllers;
+ for (ichan = 0; ichan < 4; ichan++) {
+ int mask;
- for (icont = 0; icont < 2; icont++, d++) {
- for (ichan = 0; ichan < 4; ichan++) {
- int mask;
+ mask = 1 << ichan;
- mask = 1 << ichan;
-
- if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {
- channel_run (icont, ichan);
- rearm = 1;
- }
+ if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {
+ i8257_channel_run(d, ichan);
+ rearm = 1;
}
}
- running = 0;
+ d->running = 0;
out:
- if (rearm)
- qemu_bh_schedule_idle(dma_bh);
-}
-
-static void DMA_run_bh(void *unused)
-{
- DMA_run();
+ if (rearm) {
+ qemu_bh_schedule_idle(d->dma_bh);
+ d->dma_bh_scheduled = true;
+ }
}
-void DMA_register_channel (int nchan,
- DMA_transfer_handler transfer_handler,
- void *opaque)
+static void i8257_dma_register_channel(IsaDma *obj, int nchan,
+ IsaDmaTransferHandler transfer_handler,
+ void *opaque)
{
- struct dma_regs *r;
- int ichan, ncont;
+ I8257State *d = I8257(obj);
+ I8257Regs *r;
+ int ichan;
- ncont = nchan > 3;
ichan = nchan & 3;
- r = dma_controllers[ncont].regs + ichan;
+ r = d->regs + ichan;
r->transfer_handler = transfer_handler;
r->opaque = opaque;
}
-int DMA_read_memory (int nchan, void *buf, int pos, int len)
+static int i8257_dma_read_memory(IsaDma *obj, int nchan, void *buf, int pos,
+ int len)
{
- struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
+ I8257State *d = I8257(obj);
+ I8257Regs *r = &d->regs[nchan & 3];
hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
@@ -436,9 +419,11 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len)
return len;
}
-int DMA_write_memory (int nchan, void *buf, int pos, int len)
+static int i8257_dma_write_memory(IsaDma *obj, int nchan, void *buf, int pos,
+ int len)
{
- struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
+ I8257State *s = I8257(obj);
+ I8257Regs *r = &s->regs[nchan & 3];
hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
@@ -458,21 +443,25 @@ int DMA_write_memory (int nchan, void *buf, int pos, int len)
return len;
}
-/* request the emulator to transfer a new DMA memory block ASAP */
-void DMA_schedule(int nchan)
+/* request the emulator to transfer a new DMA memory block ASAP (even
+ * if the idle bottom half would not have exited the iothread yet).
+ */
+static void i8257_dma_schedule(IsaDma *obj)
{
- struct dma_cont *d = &dma_controllers[nchan > 3];
-
- qemu_irq_pulse(*d->cpu_request_exit);
+ I8257State *d = I8257(obj);
+ if (d->dma_bh_scheduled) {
+ qemu_notify_event();
+ }
}
-static void dma_reset(void *opaque)
+static void i8257_reset(DeviceState *dev)
{
- struct dma_cont *d = opaque;
- write_cont(d, (0x05 << d->dshift), 0, 1);
+ I8257State *d = I8257(dev);
+ i8257_write_cont(d, (0x05 << d->dshift), 0, 1);
}
-static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)
+static int i8257_phony_handler(void *opaque, int nchan, int dma_pos,
+ int dma_len)
{
trace_i8257_unregistered_dma(nchan, dma_pos, dma_len);
return dma_pos;
@@ -480,8 +469,8 @@ static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)
static const MemoryRegionOps channel_io_ops = {
- .read = read_chan,
- .write = write_chan,
+ .read = i8257_read_chan,
+ .write = i8257_write_chan,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 1,
@@ -491,21 +480,21 @@ static const MemoryRegionOps channel_io_ops = {
/* IOport from page_base */
static const MemoryRegionPortio page_portio_list[] = {
- { 0x01, 3, 1, .write = write_page, .read = read_page, },
- { 0x07, 1, 1, .write = write_page, .read = read_page, },
+ { 0x01, 3, 1, .write = i8257_write_page, .read = i8257_read_page, },
+ { 0x07, 1, 1, .write = i8257_write_page, .read = i8257_read_page, },
PORTIO_END_OF_LIST(),
};
/* IOport from pageh_base */
static const MemoryRegionPortio pageh_portio_list[] = {
- { 0x01, 3, 1, .write = write_pageh, .read = read_pageh, },
- { 0x07, 3, 1, .write = write_pageh, .read = read_pageh, },
+ { 0x01, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
+ { 0x07, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
PORTIO_END_OF_LIST(),
};
static const MemoryRegionOps cont_io_ops = {
- .read = read_cont,
- .write = write_cont,
+ .read = i8257_read_cont,
+ .write = i8257_write_cont,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 1,
@@ -513,86 +502,142 @@ static const MemoryRegionOps cont_io_ops = {
},
};
-/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
-static void dma_init2(struct dma_cont *d, int base, int dshift,
- int page_base, int pageh_base,
- qemu_irq *cpu_request_exit)
+static const VMStateDescription vmstate_i8257_regs = {
+ .name = "dma_regs",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_INT32_ARRAY(now, I8257Regs, 2),
+ VMSTATE_UINT16_ARRAY(base, I8257Regs, 2),
+ VMSTATE_UINT8(mode, I8257Regs),
+ VMSTATE_UINT8(page, I8257Regs),
+ VMSTATE_UINT8(pageh, I8257Regs),
+ VMSTATE_UINT8(dack, I8257Regs),
+ VMSTATE_UINT8(eop, I8257Regs),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static int i8257_post_load(void *opaque, int version_id)
{
- int i;
+ I8257State *d = opaque;
+ i8257_dma_run(d);
- d->dshift = dshift;
- d->cpu_request_exit = cpu_request_exit;
+ return 0;
+}
+
+static const VMStateDescription vmstate_i8257 = {
+ .name = "dma",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .post_load = i8257_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(command, I8257State),
+ VMSTATE_UINT8(mask, I8257State),
+ VMSTATE_UINT8(flip_flop, I8257State),
+ VMSTATE_INT32(dshift, I8257State),
+ VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_i8257_regs,
+ I8257Regs),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void i8257_realize(DeviceState *dev, Error **errp)
+{
+ ISADevice *isa = ISA_DEVICE(dev);
+ I8257State *d = I8257(dev);
+ int i;
memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d,
"dma-chan", 8 << d->dshift);
- memory_region_add_subregion(isa_address_space_io(NULL),
- base, &d->channel_io);
+ memory_region_add_subregion(isa_address_space_io(isa),
+ d->base, &d->channel_io);
- isa_register_portio_list(NULL, page_base, page_portio_list, d,
+ isa_register_portio_list(isa, d->page_base, page_portio_list, d,
"dma-page");
- if (pageh_base >= 0) {
- isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d,
+ if (d->pageh_base >= 0) {
+ isa_register_portio_list(isa, d->pageh_base, pageh_portio_list, d,
"dma-pageh");
}
- memory_region_init_io(&d->cont_io, NULL, &cont_io_ops, d, "dma-cont",
- 8 << d->dshift);
- memory_region_add_subregion(isa_address_space_io(NULL),
- base + (8 << d->dshift), &d->cont_io);
+ memory_region_init_io(&d->cont_io, OBJECT(isa), &cont_io_ops, d,
+ "dma-cont", 8 << d->dshift);
+ memory_region_add_subregion(isa_address_space_io(isa),
+ d->base + (8 << d->dshift), &d->cont_io);
- qemu_register_reset(dma_reset, d);
- dma_reset(d);
- for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
- d->regs[i].transfer_handler = dma_phony_handler;
+ for (i = 0; i < ARRAY_SIZE(d->regs); ++i) {
+ d->regs[i].transfer_handler = i8257_phony_handler;
}
+
+ d->dma_bh = qemu_bh_new(i8257_dma_run, d);
}
-static const VMStateDescription vmstate_dma_regs = {
- .name = "dma_regs",
- .version_id = 1,
- .minimum_version_id = 1,
- .fields = (VMStateField[]) {
- VMSTATE_INT32_ARRAY(now, struct dma_regs, 2),
- VMSTATE_UINT16_ARRAY(base, struct dma_regs, 2),
- VMSTATE_UINT8(mode, struct dma_regs),
- VMSTATE_UINT8(page, struct dma_regs),
- VMSTATE_UINT8(pageh, struct dma_regs),
- VMSTATE_UINT8(dack, struct dma_regs),
- VMSTATE_UINT8(eop, struct dma_regs),
- VMSTATE_END_OF_LIST()
- }
+static Property i8257_properties[] = {
+ DEFINE_PROP_INT32("base", I8257State, base, 0x00),
+ DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80),
+ DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480),
+ DEFINE_PROP_INT32("dshift", I8257State, dshift, 0),
+ DEFINE_PROP_END_OF_LIST()
};
-static int dma_post_load(void *opaque, int version_id)
+static void i8257_class_init(ObjectClass *klass, void *data)
{
- DMA_run();
-
- return 0;
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ IsaDmaClass *idc = ISADMA_CLASS(klass);
+
+ dc->realize = i8257_realize;
+ dc->reset = i8257_reset;
+ dc->vmsd = &vmstate_i8257;
+ dc->props = i8257_properties;
+
+ idc->get_transfer_mode = i8257_dma_get_transfer_mode;
+ idc->has_autoinitialization = i8257_dma_has_autoinitialization;
+ idc->read_memory = i8257_dma_read_memory;
+ idc->write_memory = i8257_dma_write_memory;
+ idc->hold_DREQ = i8257_dma_hold_DREQ;
+ idc->release_DREQ = i8257_dma_release_DREQ;
+ idc->schedule = i8257_dma_schedule;
+ idc->register_channel = i8257_dma_register_channel;
}
-static const VMStateDescription vmstate_dma = {
- .name = "dma",
- .version_id = 1,
- .minimum_version_id = 1,
- .post_load = dma_post_load,
- .fields = (VMStateField[]) {
- VMSTATE_UINT8(command, struct dma_cont),
- VMSTATE_UINT8(mask, struct dma_cont),
- VMSTATE_UINT8(flip_flop, struct dma_cont),
- VMSTATE_INT32(dshift, struct dma_cont),
- VMSTATE_STRUCT_ARRAY(regs, struct dma_cont, 4, 1, vmstate_dma_regs, struct dma_regs),
- VMSTATE_END_OF_LIST()
+static const TypeInfo i8257_info = {
+ .name = TYPE_I8257,
+ .parent = TYPE_ISA_DEVICE,
+ .instance_size = sizeof(I8257State),
+ .class_init = i8257_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_ISADMA },
+ { }
}
};
-void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
+static void i8257_register_types(void)
+{
+ type_register_static(&i8257_info);
+}
+
+type_init(i8257_register_types)
+
+void DMA_init(ISABus *bus, int high_page_enable)
{
- dma_init2(&dma_controllers[0], 0x00, 0, 0x80,
- high_page_enable ? 0x480 : -1, cpu_request_exit);
- dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,
- high_page_enable ? 0x488 : -1, cpu_request_exit);
- vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]);
- vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]);
-
- dma_bh = qemu_bh_new(DMA_run_bh, NULL);
+ ISADevice *isa1, *isa2;
+ DeviceState *d;
+
+ isa1 = isa_create(bus, TYPE_I8257);
+ d = DEVICE(isa1);
+ qdev_prop_set_int32(d, "base", 0x00);
+ qdev_prop_set_int32(d, "page-base", 0x80);
+ qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x480 : -1);
+ qdev_prop_set_int32(d, "dshift", 0);
+ qdev_init_nofail(d);
+
+ isa2 = isa_create(bus, TYPE_I8257);
+ d = DEVICE(isa2);
+ qdev_prop_set_int32(d, "base", 0xc0);
+ qdev_prop_set_int32(d, "page-base", 0x88);
+ qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x488 : -1);
+ qdev_prop_set_int32(d, "dshift", 1);
+ qdev_init_nofail(d);
+
+ isa_bus_dma(bus, ISADMA(isa1), ISADMA(isa2));
}
diff --git a/qemu/hw/dma/omap_dma.c b/qemu/hw/dma/omap_dma.c
index 97c57a03c..700cd6b43 100644
--- a/qemu/hw/dma/omap_dma.c
+++ b/qemu/hw/dma/omap_dma.c
@@ -17,6 +17,7 @@
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/timer.h"
#include "hw/arm/omap.h"
@@ -1626,8 +1627,7 @@ struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
enum omap_dma_model model)
{
int num_irqs, memsize, i;
- struct omap_dma_s *s = (struct omap_dma_s *)
- g_malloc0(sizeof(struct omap_dma_s));
+ struct omap_dma_s *s = g_new0(struct omap_dma_s, 1);
if (model <= omap_dma_3_1) {
num_irqs = 6;
@@ -2061,8 +2061,7 @@ struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
int chans, omap_clk iclk, omap_clk fclk)
{
int i;
- struct omap_dma_s *s = (struct omap_dma_s *)
- g_malloc0(sizeof(struct omap_dma_s));
+ struct omap_dma_s *s = g_new0(struct omap_dma_s, 1);
s->model = omap_dma_4;
s->chans = chans;
diff --git a/qemu/hw/dma/pl080.c b/qemu/hw/dma/pl080.c
index b89b4744f..9318108b8 100644
--- a/qemu/hw/dma/pl080.c
+++ b/qemu/hw/dma/pl080.c
@@ -7,6 +7,7 @@
* This code is licensed under the GPL.
*/
+#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
diff --git a/qemu/hw/dma/pl330.c b/qemu/hw/dma/pl330.c
index 5be3df521..ea89ecb00 100644
--- a/qemu/hw/dma/pl330.c
+++ b/qemu/hw/dma/pl330.c
@@ -14,7 +14,9 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "qapi/error.h"
#include "qemu/timer.h"
#include "sysemu/dma.h"
diff --git a/qemu/hw/dma/puv3_dma.c b/qemu/hw/dma/puv3_dma.c
index 101bd7f8a..b97a6c176 100644
--- a/qemu/hw/dma/puv3_dma.c
+++ b/qemu/hw/dma/puv3_dma.c
@@ -8,6 +8,7 @@
* published by the Free Software Foundation, or any later version.
* See the COPYING file in the top-level directory.
*/
+#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
diff --git a/qemu/hw/dma/pxa2xx_dma.c b/qemu/hw/dma/pxa2xx_dma.c
index d4501fb4c..2306abc35 100644
--- a/qemu/hw/dma/pxa2xx_dma.c
+++ b/qemu/hw/dma/pxa2xx_dma.c
@@ -8,6 +8,7 @@
* This code is licensed under the GPL.
*/
+#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"
@@ -459,9 +460,8 @@ static int pxa2xx_dma_init(SysBusDevice *sbd)
return -1;
}
- s->chan = g_malloc0(sizeof(PXA2xxDMAChannel) * s->channels);
+ s->chan = g_new0(PXA2xxDMAChannel, s->channels);
- memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels);
for (i = 0; i < s->channels; i ++)
s->chan[i].state = DCSR_STOPINTR;
diff --git a/qemu/hw/dma/rc4030.c b/qemu/hw/dma/rc4030.c
index 3efa6de35..a06c2359a 100644
--- a/qemu/hw/dma/rc4030.c
+++ b/qemu/hw/dma/rc4030.c
@@ -22,6 +22,7 @@
* THE SOFTWARE.
*/
+#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/mips/mips.h"
#include "hw/sysbus.h"
@@ -111,7 +112,7 @@ static void set_next_tick(rc4030State *s)
tm_hz = 1000 / (s->itr + 1);
timer_mod(s->periodic_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
- get_ticks_per_sec() / tm_hz);
+ NANOSECONDS_PER_SECOND / tm_hz);
}
/* called for accesses to rc4030 */
diff --git a/qemu/hw/dma/soc_dma.c b/qemu/hw/dma/soc_dma.c
index c06aabb40..9bb499bf9 100644
--- a/qemu/hw/dma/soc_dma.c
+++ b/qemu/hw/dma/soc_dma.c
@@ -17,6 +17,7 @@
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/timer.h"
#include "hw/arm/soc_dma.h"
@@ -269,11 +270,10 @@ void soc_dma_port_add_fifo(struct soc_dma_s *soc, hwaddr virt_base,
if (entry->type == soc_dma_port_mem) {
if (entry->addr <= virt_base &&
entry->addr + entry->u.mem.size > virt_base) {
- fprintf(stderr, "%s: FIFO at " TARGET_FMT_lx
- " collides with RAM region at " TARGET_FMT_lx
- "-" TARGET_FMT_lx "\n", __FUNCTION__,
- (target_ulong) virt_base,
- (target_ulong) entry->addr, (target_ulong)
+ fprintf(stderr, "%s: FIFO at %"PRIx64
+ " collides with RAM region at %"PRIx64
+ "-%"PRIx64 "\n", __func__,
+ virt_base, entry->addr,
(entry->addr + entry->u.mem.size));
exit(-1);
}
@@ -284,10 +284,9 @@ void soc_dma_port_add_fifo(struct soc_dma_s *soc, hwaddr virt_base,
while (entry < dma->memmap + dma->memmap_size &&
entry->addr <= virt_base) {
if (entry->addr == virt_base && entry->u.fifo.out == out) {
- fprintf(stderr, "%s: FIFO at " TARGET_FMT_lx
- " collides FIFO at " TARGET_FMT_lx "\n",
- __FUNCTION__, (target_ulong) virt_base,
- (target_ulong) entry->addr);
+ fprintf(stderr, "%s: FIFO at %"PRIx64
+ " collides FIFO at %"PRIx64 "\n",
+ __func__, virt_base, entry->addr);
exit(-1);
}
@@ -322,13 +321,11 @@ void soc_dma_port_add_mem(struct soc_dma_s *soc, uint8_t *phys_base,
if ((entry->addr >= virt_base && entry->addr < virt_base + size) ||
(entry->addr <= virt_base &&
entry->addr + entry->u.mem.size > virt_base)) {
- fprintf(stderr, "%s: RAM at " TARGET_FMT_lx "-" TARGET_FMT_lx
- " collides with RAM region at " TARGET_FMT_lx
- "-" TARGET_FMT_lx "\n", __FUNCTION__,
- (target_ulong) virt_base,
- (target_ulong) (virt_base + size),
- (target_ulong) entry->addr, (target_ulong)
- (entry->addr + entry->u.mem.size));
+ fprintf(stderr, "%s: RAM at %"PRIx64 "-%"PRIx64
+ " collides with RAM region at %"PRIx64
+ "-%"PRIx64 "\n", __func__,
+ virt_base, virt_base + size,
+ entry->addr, entry->addr + entry->u.mem.size);
exit(-1);
}
@@ -337,12 +334,11 @@ void soc_dma_port_add_mem(struct soc_dma_s *soc, uint8_t *phys_base,
} else {
if (entry->addr >= virt_base &&
entry->addr < virt_base + size) {
- fprintf(stderr, "%s: RAM at " TARGET_FMT_lx "-" TARGET_FMT_lx
- " collides with FIFO at " TARGET_FMT_lx
- "\n", __FUNCTION__,
- (target_ulong) virt_base,
- (target_ulong) (virt_base + size),
- (target_ulong) entry->addr);
+ fprintf(stderr, "%s: RAM at %"PRIx64 "-%"PRIx64
+ " collides with FIFO at %"PRIx64
+ "\n", __func__,
+ virt_base, virt_base + size,
+ entry->addr);
exit(-1);
}
diff --git a/qemu/hw/dma/sparc32_dma.c b/qemu/hw/dma/sparc32_dma.c
index e6a453ce5..9d545e412 100644
--- a/qemu/hw/dma/sparc32_dma.c
+++ b/qemu/hw/dma/sparc32_dma.c
@@ -25,6 +25,7 @@
* THE SOFTWARE.
*/
+#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sparc/sparc32_dma.h"
#include "hw/sparc/sun4m.h"
diff --git a/qemu/hw/dma/sun4m_iommu.c b/qemu/hw/dma/sun4m_iommu.c
index 9a488bc9b..b3cbc54c2 100644
--- a/qemu/hw/dma/sun4m_iommu.c
+++ b/qemu/hw/dma/sun4m_iommu.c
@@ -22,6 +22,7 @@
* THE SOFTWARE.
*/
+#include "qemu/osdep.h"
#include "hw/sparc/sun4m.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
diff --git a/qemu/hw/dma/xilinx_axidma.c b/qemu/hw/dma/xilinx_axidma.c
index cf842a3cc..a4753e55a 100644
--- a/qemu/hw/dma/xilinx_axidma.c
+++ b/qemu/hw/dma/xilinx_axidma.c
@@ -22,7 +22,9 @@
* THE SOFTWARE.
*/
+#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "qapi/error.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "qemu/log.h"
@@ -133,7 +135,7 @@ struct XilinxAXIDMA {
};
/*
- * Helper calls to extract info from desriptors and other trivial
+ * Helper calls to extract info from descriptors and other trivial
* state from regs.
*/
static inline int stream_desc_sof(struct SDesc *d)
@@ -177,16 +179,6 @@ static inline int streamid_from_addr(hwaddr addr)
return sid;
}
-#ifdef DEBUG_ENET
-static void stream_desc_show(struct SDesc *d)
-{
- qemu_log("buffer_addr = " PRIx64 "\n", d->buffer_address);
- qemu_log("nxtdesc = " PRIx64 "\n", d->nxtdesc);
- qemu_log("control = %x\n", d->control);
- qemu_log("status = %x\n", d->status);
-}
-#endif
-
static void stream_desc_load(struct Stream *s, hwaddr addr)
{
struct SDesc *d = &s->desc;