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author | 2017-05-23 17:55:06 +0000 | |
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committer | 2017-05-23 17:55:06 +0000 | |
commit | 0f6296e038b5c299654d596026e7bee5aa723e56 (patch) | |
tree | a51b545d58c8128abfd6caa9ca43d32343011f62 /qemu/hw/arm/digic.c | |
parent | c4d68bc45aa6aa8b7fe39bce206cb17c2cb2d365 (diff) | |
parent | bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 (diff) |
Merge "Adding qemu as a submodule of KVMFORNFV"
Diffstat (limited to 'qemu/hw/arm/digic.c')
-rw-r--r-- | qemu/hw/arm/digic.c | 123 |
1 files changed, 0 insertions, 123 deletions
diff --git a/qemu/hw/arm/digic.c b/qemu/hw/arm/digic.c deleted file mode 100644 index e0f973032..000000000 --- a/qemu/hw/arm/digic.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * QEMU model of the Canon DIGIC SoC. - * - * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com> - * - * This model is based on reverse engineering efforts - * made by CHDK (http://chdk.wikia.com) and - * Magic Lantern (http://www.magiclantern.fm) projects - * contributors. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "hw/arm/digic.h" - -#define DIGIC4_TIMER_BASE(n) (0xc0210000 + (n) * 0x100) - -#define DIGIC_UART_BASE 0xc0800000 - -static void digic_init(Object *obj) -{ - DigicState *s = DIGIC(obj); - DeviceState *dev; - int i; - - object_initialize(&s->cpu, sizeof(s->cpu), "arm946-" TYPE_ARM_CPU); - object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL); - - for (i = 0; i < DIGIC4_NB_TIMERS; i++) { -#define DIGIC_TIMER_NAME_MLEN 11 - char name[DIGIC_TIMER_NAME_MLEN]; - - object_initialize(&s->timer[i], sizeof(s->timer[i]), TYPE_DIGIC_TIMER); - dev = DEVICE(&s->timer[i]); - qdev_set_parent_bus(dev, sysbus_get_default()); - snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i); - object_property_add_child(obj, name, OBJECT(&s->timer[i]), NULL); - } - - object_initialize(&s->uart, sizeof(s->uart), TYPE_DIGIC_UART); - dev = DEVICE(&s->uart); - qdev_set_parent_bus(dev, sysbus_get_default()); - object_property_add_child(obj, "uart", OBJECT(&s->uart), NULL); -} - -static void digic_realize(DeviceState *dev, Error **errp) -{ - DigicState *s = DIGIC(dev); - Error *err = NULL; - SysBusDevice *sbd; - int i; - - object_property_set_bool(OBJECT(&s->cpu), true, "reset-hivecs", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - - object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - - for (i = 0; i < DIGIC4_NB_TIMERS; i++) { - object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - - sbd = SYS_BUS_DEVICE(&s->timer[i]); - sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i)); - } - - object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - - sbd = SYS_BUS_DEVICE(&s->uart); - sysbus_mmio_map(sbd, 0, DIGIC_UART_BASE); -} - -static void digic_class_init(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - - dc->realize = digic_realize; - - /* - * Reason: creates an ARM CPU, thus use after free(), see - * arm_cpu_class_init() - */ - dc->cannot_destroy_with_object_finalize_yet = true; -} - -static const TypeInfo digic_type_info = { - .name = TYPE_DIGIC, - .parent = TYPE_DEVICE, - .instance_size = sizeof(DigicState), - .instance_init = digic_init, - .class_init = digic_class_init, -}; - -static void digic_register_types(void) -{ - type_register_static(&digic_type_info); -} - -type_init(digic_register_types) |