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authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/include/dt-bindings/mfd
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/include/dt-bindings/mfd')
-rw-r--r--kernel/include/dt-bindings/mfd/arizona.h93
-rw-r--r--kernel/include/dt-bindings/mfd/as3722.h52
-rw-r--r--kernel/include/dt-bindings/mfd/dbx500-prcmu.h83
-rw-r--r--kernel/include/dt-bindings/mfd/palmas.h18
-rw-r--r--kernel/include/dt-bindings/mfd/qcom-rpm.h160
5 files changed, 406 insertions, 0 deletions
diff --git a/kernel/include/dt-bindings/mfd/arizona.h b/kernel/include/dt-bindings/mfd/arizona.h
new file mode 100644
index 000000000..c7af7c7ef
--- /dev/null
+++ b/kernel/include/dt-bindings/mfd/arizona.h
@@ -0,0 +1,93 @@
+/*
+ * Device Tree defines for Arizona devices
+ *
+ * Copyright 2015 Cirrus Logic Inc.
+ *
+ * Author: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_MFD_ARIZONA_H
+#define _DT_BINDINGS_MFD_ARIZONA_H
+
+/* GPIO Function Definitions */
+#define ARIZONA_GP_FN_TXLRCLK 0x00
+#define ARIZONA_GP_FN_GPIO 0x01
+#define ARIZONA_GP_FN_IRQ1 0x02
+#define ARIZONA_GP_FN_IRQ2 0x03
+#define ARIZONA_GP_FN_OPCLK 0x04
+#define ARIZONA_GP_FN_FLL1_OUT 0x05
+#define ARIZONA_GP_FN_FLL2_OUT 0x06
+#define ARIZONA_GP_FN_PWM1 0x08
+#define ARIZONA_GP_FN_PWM2 0x09
+#define ARIZONA_GP_FN_SYSCLK_UNDERCLOCKED 0x0A
+#define ARIZONA_GP_FN_ASYNCCLK_UNDERCLOCKED 0x0B
+#define ARIZONA_GP_FN_FLL1_LOCK 0x0C
+#define ARIZONA_GP_FN_FLL2_LOCK 0x0D
+#define ARIZONA_GP_FN_FLL1_CLOCK_OK 0x0F
+#define ARIZONA_GP_FN_FLL2_CLOCK_OK 0x10
+#define ARIZONA_GP_FN_HEADPHONE_DET 0x12
+#define ARIZONA_GP_FN_MIC_DET 0x13
+#define ARIZONA_GP_FN_WSEQ_STATUS 0x15
+#define ARIZONA_GP_FN_CIF_ADDRESS_ERROR 0x16
+#define ARIZONA_GP_FN_ASRC1_LOCK 0x1A
+#define ARIZONA_GP_FN_ASRC2_LOCK 0x1B
+#define ARIZONA_GP_FN_ASRC_CONFIG_ERROR 0x1C
+#define ARIZONA_GP_FN_DRC1_SIGNAL_DETECT 0x1D
+#define ARIZONA_GP_FN_DRC1_ANTICLIP 0x1E
+#define ARIZONA_GP_FN_DRC1_DECAY 0x1F
+#define ARIZONA_GP_FN_DRC1_NOISE 0x20
+#define ARIZONA_GP_FN_DRC1_QUICK_RELEASE 0x21
+#define ARIZONA_GP_FN_DRC2_SIGNAL_DETECT 0x22
+#define ARIZONA_GP_FN_DRC2_ANTICLIP 0x23
+#define ARIZONA_GP_FN_DRC2_DECAY 0x24
+#define ARIZONA_GP_FN_DRC2_NOISE 0x25
+#define ARIZONA_GP_FN_DRC2_QUICK_RELEASE 0x26
+#define ARIZONA_GP_FN_MIXER_DROPPED_SAMPLE 0x27
+#define ARIZONA_GP_FN_AIF1_CONFIG_ERROR 0x28
+#define ARIZONA_GP_FN_AIF2_CONFIG_ERROR 0x29
+#define ARIZONA_GP_FN_AIF3_CONFIG_ERROR 0x2A
+#define ARIZONA_GP_FN_SPK_TEMP_SHUTDOWN 0x2B
+#define ARIZONA_GP_FN_SPK_TEMP_WARNING 0x2C
+#define ARIZONA_GP_FN_UNDERCLOCKED 0x2D
+#define ARIZONA_GP_FN_OVERCLOCKED 0x2E
+#define ARIZONA_GP_FN_DSP_IRQ1 0x35
+#define ARIZONA_GP_FN_DSP_IRQ2 0x36
+#define ARIZONA_GP_FN_ASYNC_OPCLK 0x3D
+#define ARIZONA_GP_FN_BOOT_DONE 0x44
+#define ARIZONA_GP_FN_DSP1_RAM_READY 0x45
+#define ARIZONA_GP_FN_SYSCLK_ENA_STATUS 0x4B
+#define ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS 0x4C
+
+/* GPIO Configuration Bits */
+#define ARIZONA_GPN_DIR 0x8000
+#define ARIZONA_GPN_PU 0x4000
+#define ARIZONA_GPN_PD 0x2000
+#define ARIZONA_GPN_LVL 0x0800
+#define ARIZONA_GPN_POL 0x0400
+#define ARIZONA_GPN_OP_CFG 0x0200
+#define ARIZONA_GPN_DB 0x0100
+
+/* Provide some defines for the most common configs */
+#define ARIZONA_GP_DEFAULT 0xffffffff
+#define ARIZONA_GP_OUTPUT (ARIZONA_GP_FN_GPIO)
+#define ARIZONA_GP_INPUT (ARIZONA_GP_FN_GPIO | \
+ ARIZONA_GPN_DIR)
+
+#define ARIZONA_32KZ_MCLK1 1
+#define ARIZONA_32KZ_MCLK2 2
+#define ARIZONA_32KZ_NONE 3
+
+#define ARIZONA_DMIC_MICVDD 0
+#define ARIZONA_DMIC_MICBIAS1 1
+#define ARIZONA_DMIC_MICBIAS2 2
+#define ARIZONA_DMIC_MICBIAS3 3
+
+#define ARIZONA_INMODE_DIFF 0
+#define ARIZONA_INMODE_SE 1
+#define ARIZONA_INMODE_DMIC 2
+
+#endif
diff --git a/kernel/include/dt-bindings/mfd/as3722.h b/kernel/include/dt-bindings/mfd/as3722.h
new file mode 100644
index 000000000..e66c0898c
--- /dev/null
+++ b/kernel/include/dt-bindings/mfd/as3722.h
@@ -0,0 +1,52 @@
+/*
+ * This header provides macros for ams AS3722 device bindings.
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ */
+
+#ifndef __DT_BINDINGS_AS3722_H__
+#define __DT_BINDINGS_AS3722_H__
+
+/* External control pins */
+#define AS3722_EXT_CONTROL_PIN_ENABLE1 1
+#define AS3722_EXT_CONTROL_PIN_ENABLE2 2
+#define AS3722_EXT_CONTROL_PIN_ENABLE3 3
+
+/* Interrupt numbers for AS3722 */
+#define AS3722_IRQ_LID 0
+#define AS3722_IRQ_ACOK 1
+#define AS3722_IRQ_ENABLE1 2
+#define AS3722_IRQ_OCCUR_ALARM_SD0 3
+#define AS3722_IRQ_ONKEY_LONG_PRESS 4
+#define AS3722_IRQ_ONKEY 5
+#define AS3722_IRQ_OVTMP 6
+#define AS3722_IRQ_LOWBAT 7
+#define AS3722_IRQ_SD0_LV 8
+#define AS3722_IRQ_SD1_LV 9
+#define AS3722_IRQ_SD2_LV 10
+#define AS3722_IRQ_PWM1_OV_PROT 11
+#define AS3722_IRQ_PWM2_OV_PROT 12
+#define AS3722_IRQ_ENABLE2 13
+#define AS3722_IRQ_SD6_LV 14
+#define AS3722_IRQ_RTC_REP 15
+#define AS3722_IRQ_RTC_ALARM 16
+#define AS3722_IRQ_GPIO1 17
+#define AS3722_IRQ_GPIO2 18
+#define AS3722_IRQ_GPIO3 19
+#define AS3722_IRQ_GPIO4 20
+#define AS3722_IRQ_GPIO5 21
+#define AS3722_IRQ_WATCHDOG 22
+#define AS3722_IRQ_ENABLE3 23
+#define AS3722_IRQ_TEMP_SD0_SHUTDOWN 24
+#define AS3722_IRQ_TEMP_SD1_SHUTDOWN 25
+#define AS3722_IRQ_TEMP_SD2_SHUTDOWN 26
+#define AS3722_IRQ_TEMP_SD0_ALARM 27
+#define AS3722_IRQ_TEMP_SD1_ALARM 28
+#define AS3722_IRQ_TEMP_SD6_ALARM 29
+#define AS3722_IRQ_OCCUR_ALARM_SD6 30
+#define AS3722_IRQ_ADC 31
+
+#endif /* __DT_BINDINGS_AS3722_H__ */
diff --git a/kernel/include/dt-bindings/mfd/dbx500-prcmu.h b/kernel/include/dt-bindings/mfd/dbx500-prcmu.h
new file mode 100644
index 000000000..552a2d174
--- /dev/null
+++ b/kernel/include/dt-bindings/mfd/dbx500-prcmu.h
@@ -0,0 +1,83 @@
+/*
+ * This header provides constants for the PRCMU bindings.
+ *
+ */
+
+#ifndef _DT_BINDINGS_MFD_PRCMU_H
+#define _DT_BINDINGS_MFD_PRCMU_H
+
+/*
+ * Clock identifiers.
+ */
+#define ARMCLK 0
+#define PRCMU_ACLK 1
+#define PRCMU_SVAMMCSPCLK 2
+#define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
+#define PRCMU_SIACLK 3
+#define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
+#define PRCMU_SGACLK 4
+#define PRCMU_UARTCLK 5
+#define PRCMU_MSP02CLK 6
+#define PRCMU_MSP1CLK 7
+#define PRCMU_I2CCLK 8
+#define PRCMU_SDMMCCLK 9
+#define PRCMU_SLIMCLK 10
+#define PRCMU_CAMCLK 10 /* DBx540 only. */
+#define PRCMU_PER1CLK 11
+#define PRCMU_PER2CLK 12
+#define PRCMU_PER3CLK 13
+#define PRCMU_PER5CLK 14
+#define PRCMU_PER6CLK 15
+#define PRCMU_PER7CLK 16
+#define PRCMU_LCDCLK 17
+#define PRCMU_BMLCLK 18
+#define PRCMU_HSITXCLK 19
+#define PRCMU_HSIRXCLK 20
+#define PRCMU_HDMICLK 21
+#define PRCMU_APEATCLK 22
+#define PRCMU_APETRACECLK 23
+#define PRCMU_MCDECLK 24
+#define PRCMU_IPI2CCLK 25
+#define PRCMU_DSIALTCLK 26
+#define PRCMU_DMACLK 27
+#define PRCMU_B2R2CLK 28
+#define PRCMU_TVCLK 29
+#define SPARE_UNIPROCLK 30
+#define PRCMU_SSPCLK 31
+#define PRCMU_RNGCLK 32
+#define PRCMU_UICCCLK 33
+#define PRCMU_G1CLK 34 /* DBx540 only. */
+#define PRCMU_HVACLK 35 /* DBx540 only. */
+#define PRCMU_SPARE1CLK 36
+#define PRCMU_SPARE2CLK 37
+
+#define PRCMU_NUM_REG_CLOCKS 38
+
+#define PRCMU_RTCCLK PRCMU_NUM_REG_CLOCKS
+#define PRCMU_SYSCLK 39
+#define PRCMU_CDCLK 40
+#define PRCMU_TIMCLK 41
+#define PRCMU_PLLSOC0 42
+#define PRCMU_PLLSOC1 43
+#define PRCMU_ARMSS 44
+#define PRCMU_PLLDDR 45
+
+/* DSI Clocks */
+#define PRCMU_PLLDSI 46
+#define PRCMU_DSI0CLK 47
+#define PRCMU_DSI1CLK 48
+#define PRCMU_DSI0ESCCLK 49
+#define PRCMU_DSI1ESCCLK 50
+#define PRCMU_DSI2ESCCLK 51
+
+/* LCD DSI PLL - Ux540 only */
+#define PRCMU_PLLDSI_LCD 52
+#define PRCMU_DSI0CLK_LCD 53
+#define PRCMU_DSI1CLK_LCD 54
+#define PRCMU_DSI0ESCCLK_LCD 55
+#define PRCMU_DSI1ESCCLK_LCD 56
+#define PRCMU_DSI2ESCCLK_LCD 57
+
+#define PRCMU_NUM_CLKS 58
+
+#endif
diff --git a/kernel/include/dt-bindings/mfd/palmas.h b/kernel/include/dt-bindings/mfd/palmas.h
new file mode 100644
index 000000000..2c8ac4841
--- /dev/null
+++ b/kernel/include/dt-bindings/mfd/palmas.h
@@ -0,0 +1,18 @@
+/*
+ * This header provides macros for Palmas device bindings.
+ *
+ * Copyright (c) 2013, NVIDIA Corporation.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ */
+
+#ifndef __DT_BINDINGS_PALMAS_H__
+#define __DT_BINDINGS_PALMAS_H
+
+/* External control pins */
+#define PALMAS_EXT_CONTROL_PIN_ENABLE1 1
+#define PALMAS_EXT_CONTROL_PIN_ENABLE2 2
+#define PALMAS_EXT_CONTROL_PIN_NSLEEP 3
+
+#endif /* __DT_BINDINGS_PALMAS_H */
diff --git a/kernel/include/dt-bindings/mfd/qcom-rpm.h b/kernel/include/dt-bindings/mfd/qcom-rpm.h
new file mode 100644
index 000000000..13a9d4bf2
--- /dev/null
+++ b/kernel/include/dt-bindings/mfd/qcom-rpm.h
@@ -0,0 +1,160 @@
+/*
+ * This header provides constants for the Qualcomm RPM bindings.
+ */
+
+#ifndef _DT_BINDINGS_MFD_QCOM_RPM_H
+#define _DT_BINDINGS_MFD_QCOM_RPM_H
+
+/*
+ * Constants use to identify individual resources in the RPM.
+ */
+#define QCOM_RPM_APPS_FABRIC_ARB 1
+#define QCOM_RPM_APPS_FABRIC_CLK 2
+#define QCOM_RPM_APPS_FABRIC_HALT 3
+#define QCOM_RPM_APPS_FABRIC_IOCTL 4
+#define QCOM_RPM_APPS_FABRIC_MODE 5
+#define QCOM_RPM_APPS_L2_CACHE_CTL 6
+#define QCOM_RPM_CFPB_CLK 7
+#define QCOM_RPM_CXO_BUFFERS 8
+#define QCOM_RPM_CXO_CLK 9
+#define QCOM_RPM_DAYTONA_FABRIC_CLK 10
+#define QCOM_RPM_DDR_DMM 11
+#define QCOM_RPM_EBI1_CLK 12
+#define QCOM_RPM_HDMI_SWITCH 13
+#define QCOM_RPM_MMFPB_CLK 14
+#define QCOM_RPM_MM_FABRIC_ARB 15
+#define QCOM_RPM_MM_FABRIC_CLK 16
+#define QCOM_RPM_MM_FABRIC_HALT 17
+#define QCOM_RPM_MM_FABRIC_IOCTL 18
+#define QCOM_RPM_MM_FABRIC_MODE 19
+#define QCOM_RPM_PLL_4 20
+#define QCOM_RPM_PM8058_LDO0 21
+#define QCOM_RPM_PM8058_LDO1 22
+#define QCOM_RPM_PM8058_LDO2 23
+#define QCOM_RPM_PM8058_LDO3 24
+#define QCOM_RPM_PM8058_LDO4 25
+#define QCOM_RPM_PM8058_LDO5 26
+#define QCOM_RPM_PM8058_LDO6 27
+#define QCOM_RPM_PM8058_LDO7 28
+#define QCOM_RPM_PM8058_LDO8 29
+#define QCOM_RPM_PM8058_LDO9 30
+#define QCOM_RPM_PM8058_LDO10 31
+#define QCOM_RPM_PM8058_LDO11 32
+#define QCOM_RPM_PM8058_LDO12 33
+#define QCOM_RPM_PM8058_LDO13 34
+#define QCOM_RPM_PM8058_LDO14 35
+#define QCOM_RPM_PM8058_LDO15 36
+#define QCOM_RPM_PM8058_LDO16 37
+#define QCOM_RPM_PM8058_LDO17 38
+#define QCOM_RPM_PM8058_LDO18 39
+#define QCOM_RPM_PM8058_LDO19 40
+#define QCOM_RPM_PM8058_LDO20 41
+#define QCOM_RPM_PM8058_LDO21 42
+#define QCOM_RPM_PM8058_LDO22 43
+#define QCOM_RPM_PM8058_LDO23 44
+#define QCOM_RPM_PM8058_LDO24 45
+#define QCOM_RPM_PM8058_LDO25 46
+#define QCOM_RPM_PM8058_LVS0 47
+#define QCOM_RPM_PM8058_LVS1 48
+#define QCOM_RPM_PM8058_NCP 49
+#define QCOM_RPM_PM8058_SMPS0 50
+#define QCOM_RPM_PM8058_SMPS1 51
+#define QCOM_RPM_PM8058_SMPS2 52
+#define QCOM_RPM_PM8058_SMPS3 53
+#define QCOM_RPM_PM8058_SMPS4 54
+#define QCOM_RPM_PM8821_LDO1 55
+#define QCOM_RPM_PM8821_SMPS1 56
+#define QCOM_RPM_PM8821_SMPS2 57
+#define QCOM_RPM_PM8901_LDO0 58
+#define QCOM_RPM_PM8901_LDO1 59
+#define QCOM_RPM_PM8901_LDO2 60
+#define QCOM_RPM_PM8901_LDO3 61
+#define QCOM_RPM_PM8901_LDO4 62
+#define QCOM_RPM_PM8901_LDO5 63
+#define QCOM_RPM_PM8901_LDO6 64
+#define QCOM_RPM_PM8901_LVS0 65
+#define QCOM_RPM_PM8901_LVS1 66
+#define QCOM_RPM_PM8901_LVS2 67
+#define QCOM_RPM_PM8901_LVS3 68
+#define QCOM_RPM_PM8901_MVS 69
+#define QCOM_RPM_PM8901_SMPS0 70
+#define QCOM_RPM_PM8901_SMPS1 71
+#define QCOM_RPM_PM8901_SMPS2 72
+#define QCOM_RPM_PM8901_SMPS3 73
+#define QCOM_RPM_PM8901_SMPS4 74
+#define QCOM_RPM_PM8921_CLK1 75
+#define QCOM_RPM_PM8921_CLK2 76
+#define QCOM_RPM_PM8921_LDO1 77
+#define QCOM_RPM_PM8921_LDO2 78
+#define QCOM_RPM_PM8921_LDO3 79
+#define QCOM_RPM_PM8921_LDO4 80
+#define QCOM_RPM_PM8921_LDO5 81
+#define QCOM_RPM_PM8921_LDO6 82
+#define QCOM_RPM_PM8921_LDO7 83
+#define QCOM_RPM_PM8921_LDO8 84
+#define QCOM_RPM_PM8921_LDO9 85
+#define QCOM_RPM_PM8921_LDO10 86
+#define QCOM_RPM_PM8921_LDO11 87
+#define QCOM_RPM_PM8921_LDO12 88
+#define QCOM_RPM_PM8921_LDO13 89
+#define QCOM_RPM_PM8921_LDO14 90
+#define QCOM_RPM_PM8921_LDO15 91
+#define QCOM_RPM_PM8921_LDO16 92
+#define QCOM_RPM_PM8921_LDO17 93
+#define QCOM_RPM_PM8921_LDO18 94
+#define QCOM_RPM_PM8921_LDO19 95
+#define QCOM_RPM_PM8921_LDO20 96
+#define QCOM_RPM_PM8921_LDO21 97
+#define QCOM_RPM_PM8921_LDO22 98
+#define QCOM_RPM_PM8921_LDO23 99
+#define QCOM_RPM_PM8921_LDO24 100
+#define QCOM_RPM_PM8921_LDO25 101
+#define QCOM_RPM_PM8921_LDO26 102
+#define QCOM_RPM_PM8921_LDO27 103
+#define QCOM_RPM_PM8921_LDO28 104
+#define QCOM_RPM_PM8921_LDO29 105
+#define QCOM_RPM_PM8921_LVS1 106
+#define QCOM_RPM_PM8921_LVS2 107
+#define QCOM_RPM_PM8921_LVS3 108
+#define QCOM_RPM_PM8921_LVS4 109
+#define QCOM_RPM_PM8921_LVS5 110
+#define QCOM_RPM_PM8921_LVS6 111
+#define QCOM_RPM_PM8921_LVS7 112
+#define QCOM_RPM_PM8921_MVS 113
+#define QCOM_RPM_PM8921_NCP 114
+#define QCOM_RPM_PM8921_SMPS1 115
+#define QCOM_RPM_PM8921_SMPS2 116
+#define QCOM_RPM_PM8921_SMPS3 117
+#define QCOM_RPM_PM8921_SMPS4 118
+#define QCOM_RPM_PM8921_SMPS5 119
+#define QCOM_RPM_PM8921_SMPS6 120
+#define QCOM_RPM_PM8921_SMPS7 121
+#define QCOM_RPM_PM8921_SMPS8 122
+#define QCOM_RPM_PXO_CLK 123
+#define QCOM_RPM_QDSS_CLK 124
+#define QCOM_RPM_SFPB_CLK 125
+#define QCOM_RPM_SMI_CLK 126
+#define QCOM_RPM_SYS_FABRIC_ARB 127
+#define QCOM_RPM_SYS_FABRIC_CLK 128
+#define QCOM_RPM_SYS_FABRIC_HALT 129
+#define QCOM_RPM_SYS_FABRIC_IOCTL 130
+#define QCOM_RPM_SYS_FABRIC_MODE 131
+#define QCOM_RPM_USB_OTG_SWITCH 132
+#define QCOM_RPM_VDDMIN_GPIO 133
+#define QCOM_RPM_NSS_FABRIC_0_CLK 134
+#define QCOM_RPM_NSS_FABRIC_1_CLK 135
+#define QCOM_RPM_SMB208_S1a 136
+#define QCOM_RPM_SMB208_S1b 137
+#define QCOM_RPM_SMB208_S2a 138
+#define QCOM_RPM_SMB208_S2b 139
+
+/*
+ * Constants used to select force mode for regulators.
+ */
+#define QCOM_RPM_FORCE_MODE_NONE 0
+#define QCOM_RPM_FORCE_MODE_LPM 1
+#define QCOM_RPM_FORCE_MODE_HPM 2
+#define QCOM_RPM_FORCE_MODE_AUTO 3
+#define QCOM_RPM_FORCE_MODE_BYPASS 4
+
+#endif