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authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw')
-rw-r--r--kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild4
-rw-r--r--kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c141
-rw-r--r--kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c139
-rw-r--r--kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c122
-rw-r--r--kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c234
-rw-r--r--kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h45
6 files changed, 685 insertions, 0 deletions
diff --git a/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild b/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
new file mode 100644
index 000000000..bdc3a0590
--- /dev/null
+++ b/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
@@ -0,0 +1,4 @@
+nvkm-y += nvkm/engine/sw/nv04.o
+nvkm-y += nvkm/engine/sw/nv10.o
+nvkm-y += nvkm/engine/sw/nv50.o
+nvkm-y += nvkm/engine/sw/gf100.o
diff --git a/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c b/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
new file mode 100644
index 000000000..533d5d8ed
--- /dev/null
+++ b/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+#include "nv50.h"
+
+#include <subdev/bar.h>
+
+/*******************************************************************************
+ * software object classes
+ ******************************************************************************/
+
+static int
+gf100_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
+{
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
+ u64 data = *(u32 *)args;
+ if (mthd == 0x0400) {
+ chan->vblank.offset &= 0x00ffffffffULL;
+ chan->vblank.offset |= data << 32;
+ } else {
+ chan->vblank.offset &= 0xff00000000ULL;
+ chan->vblank.offset |= data;
+ }
+ return 0;
+}
+
+static int
+gf100_sw_mthd_mp_control(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
+{
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
+ struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
+ u32 data = *(u32 *)args;
+
+ switch (mthd) {
+ case 0x600:
+ nv_wr32(priv, 0x419e00, data); /* MP.PM_UNK000 */
+ break;
+ case 0x644:
+ if (data & ~0x1ffffe)
+ return -EINVAL;
+ nv_wr32(priv, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */
+ break;
+ case 0x6ac:
+ nv_wr32(priv, 0x419eac, data); /* MP.PM_UNK0AC */
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static struct nvkm_omthds
+gf100_sw_omthds[] = {
+ { 0x0400, 0x0400, gf100_sw_mthd_vblsem_offset },
+ { 0x0404, 0x0404, gf100_sw_mthd_vblsem_offset },
+ { 0x0408, 0x0408, nv50_sw_mthd_vblsem_value },
+ { 0x040c, 0x040c, nv50_sw_mthd_vblsem_release },
+ { 0x0500, 0x0500, nv50_sw_mthd_flip },
+ { 0x0600, 0x0600, gf100_sw_mthd_mp_control },
+ { 0x0644, 0x0644, gf100_sw_mthd_mp_control },
+ { 0x06ac, 0x06ac, gf100_sw_mthd_mp_control },
+ {}
+};
+
+static struct nvkm_oclass
+gf100_sw_sclass[] = {
+ { 0x906e, &nvkm_object_ofuncs, gf100_sw_omthds },
+ {}
+};
+
+/*******************************************************************************
+ * software context
+ ******************************************************************************/
+
+static int
+gf100_sw_vblsem_release(struct nvkm_notify *notify)
+{
+ struct nv50_sw_chan *chan =
+ container_of(notify, typeof(*chan), vblank.notify[notify->index]);
+ struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
+ struct nvkm_bar *bar = nvkm_bar(priv);
+
+ nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
+ bar->flush(bar);
+ nv_wr32(priv, 0x06000c, upper_32_bits(chan->vblank.offset));
+ nv_wr32(priv, 0x060010, lower_32_bits(chan->vblank.offset));
+ nv_wr32(priv, 0x060014, chan->vblank.value);
+
+ return NVKM_NOTIFY_DROP;
+}
+
+static struct nv50_sw_cclass
+gf100_sw_cclass = {
+ .base.handle = NV_ENGCTX(SW, 0xc0),
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = nv50_sw_context_ctor,
+ .dtor = nv50_sw_context_dtor,
+ .init = _nvkm_sw_context_init,
+ .fini = _nvkm_sw_context_fini,
+ },
+ .vblank = gf100_sw_vblsem_release,
+};
+
+/*******************************************************************************
+ * software engine/subdev functions
+ ******************************************************************************/
+
+struct nvkm_oclass *
+gf100_sw_oclass = &(struct nv50_sw_oclass) {
+ .base.handle = NV_ENGINE(SW, 0xc0),
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = nv50_sw_ctor,
+ .dtor = _nvkm_sw_dtor,
+ .init = _nvkm_sw_init,
+ .fini = _nvkm_sw_fini,
+ },
+ .cclass = &gf100_sw_cclass.base,
+ .sclass = gf100_sw_sclass,
+}.base;
diff --git a/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c b/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
new file mode 100644
index 000000000..897024421
--- /dev/null
+++ b/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+#include <engine/sw.h>
+#include <engine/fifo.h>
+
+struct nv04_sw_priv {
+ struct nvkm_sw base;
+};
+
+struct nv04_sw_chan {
+ struct nvkm_sw_chan base;
+};
+
+/*******************************************************************************
+ * software object classes
+ ******************************************************************************/
+
+static int
+nv04_sw_set_ref(struct nvkm_object *object, u32 mthd, void *data, u32 size)
+{
+ struct nvkm_object *channel = (void *)nv_engctx(object->parent);
+ struct nvkm_fifo_chan *fifo = (void *)channel->parent;
+ atomic_set(&fifo->refcnt, *(u32*)data);
+ return 0;
+}
+
+static int
+nv04_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
+{
+ struct nv04_sw_chan *chan = (void *)nv_engctx(object->parent);
+ if (chan->base.flip)
+ return chan->base.flip(chan->base.flip_data);
+ return -EINVAL;
+}
+
+static struct nvkm_omthds
+nv04_sw_omthds[] = {
+ { 0x0150, 0x0150, nv04_sw_set_ref },
+ { 0x0500, 0x0500, nv04_sw_flip },
+ {}
+};
+
+static struct nvkm_oclass
+nv04_sw_sclass[] = {
+ { 0x006e, &nvkm_object_ofuncs, nv04_sw_omthds },
+ {}
+};
+
+/*******************************************************************************
+ * software context
+ ******************************************************************************/
+
+static int
+nv04_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
+{
+ struct nv04_sw_chan *chan;
+ int ret;
+
+ ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
+ *pobject = nv_object(chan);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct nvkm_oclass
+nv04_sw_cclass = {
+ .handle = NV_ENGCTX(SW, 0x04),
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = nv04_sw_context_ctor,
+ .dtor = _nvkm_sw_context_dtor,
+ .init = _nvkm_sw_context_init,
+ .fini = _nvkm_sw_context_fini,
+ },
+};
+
+/*******************************************************************************
+ * software engine/subdev functions
+ ******************************************************************************/
+
+void
+nv04_sw_intr(struct nvkm_subdev *subdev)
+{
+ nv_mask(subdev, 0x000100, 0x80000000, 0x00000000);
+}
+
+static int
+nv04_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
+{
+ struct nv04_sw_priv *priv;
+ int ret;
+
+ ret = nvkm_sw_create(parent, engine, oclass, &priv);
+ *pobject = nv_object(priv);
+ if (ret)
+ return ret;
+
+ nv_engine(priv)->cclass = &nv04_sw_cclass;
+ nv_engine(priv)->sclass = nv04_sw_sclass;
+ nv_subdev(priv)->intr = nv04_sw_intr;
+ return 0;
+}
+
+struct nvkm_oclass *
+nv04_sw_oclass = &(struct nvkm_oclass) {
+ .handle = NV_ENGINE(SW, 0x04),
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = nv04_sw_ctor,
+ .dtor = _nvkm_sw_dtor,
+ .init = _nvkm_sw_init,
+ .fini = _nvkm_sw_fini,
+ },
+};
diff --git a/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c b/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
new file mode 100644
index 000000000..c61153a3f
--- /dev/null
+++ b/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+#include <engine/sw.h>
+
+struct nv10_sw_priv {
+ struct nvkm_sw base;
+};
+
+struct nv10_sw_chan {
+ struct nvkm_sw_chan base;
+};
+
+/*******************************************************************************
+ * software object classes
+ ******************************************************************************/
+
+static int
+nv10_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
+{
+ struct nv10_sw_chan *chan = (void *)nv_engctx(object->parent);
+ if (chan->base.flip)
+ return chan->base.flip(chan->base.flip_data);
+ return -EINVAL;
+}
+
+static struct nvkm_omthds
+nv10_sw_omthds[] = {
+ { 0x0500, 0x0500, nv10_sw_flip },
+ {}
+};
+
+static struct nvkm_oclass
+nv10_sw_sclass[] = {
+ { 0x016e, &nvkm_object_ofuncs, nv10_sw_omthds },
+ {}
+};
+
+/*******************************************************************************
+ * software context
+ ******************************************************************************/
+
+static int
+nv10_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
+{
+ struct nv10_sw_chan *chan;
+ int ret;
+
+ ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
+ *pobject = nv_object(chan);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static struct nvkm_oclass
+nv10_sw_cclass = {
+ .handle = NV_ENGCTX(SW, 0x04),
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = nv10_sw_context_ctor,
+ .dtor = _nvkm_sw_context_dtor,
+ .init = _nvkm_sw_context_init,
+ .fini = _nvkm_sw_context_fini,
+ },
+};
+
+/*******************************************************************************
+ * software engine/subdev functions
+ ******************************************************************************/
+
+static int
+nv10_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
+{
+ struct nv10_sw_priv *priv;
+ int ret;
+
+ ret = nvkm_sw_create(parent, engine, oclass, &priv);
+ *pobject = nv_object(priv);
+ if (ret)
+ return ret;
+
+ nv_engine(priv)->cclass = &nv10_sw_cclass;
+ nv_engine(priv)->sclass = nv10_sw_sclass;
+ nv_subdev(priv)->intr = nv04_sw_intr;
+ return 0;
+}
+
+struct nvkm_oclass *
+nv10_sw_oclass = &(struct nvkm_oclass) {
+ .handle = NV_ENGINE(SW, 0x10),
+ .ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = nv10_sw_ctor,
+ .dtor = _nvkm_sw_dtor,
+ .init = _nvkm_sw_init,
+ .fini = _nvkm_sw_fini,
+ },
+};
diff --git a/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
new file mode 100644
index 000000000..401fcd730
--- /dev/null
+++ b/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+#include "nv50.h"
+
+#include <core/device.h>
+#include <core/handle.h>
+#include <core/namedb.h>
+#include <engine/disp.h>
+#include <subdev/bar.h>
+
+#include <nvif/event.h>
+
+/*******************************************************************************
+ * software object classes
+ ******************************************************************************/
+
+static int
+nv50_sw_mthd_dma_vblsem(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
+{
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
+ struct nvkm_fifo_chan *fifo = (void *)nv_object(chan)->parent;
+ struct nvkm_handle *handle;
+ int ret = -EINVAL;
+
+ handle = nvkm_namedb_get(nv_namedb(fifo), *(u32 *)args);
+ if (!handle)
+ return -ENOENT;
+
+ if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
+ struct nvkm_gpuobj *gpuobj = nv_gpuobj(handle->object);
+ chan->vblank.ctxdma = gpuobj->node->offset >> 4;
+ ret = 0;
+ }
+ nvkm_namedb_put(handle);
+ return ret;
+}
+
+static int
+nv50_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
+{
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
+ chan->vblank.offset = *(u32 *)args;
+ return 0;
+}
+
+int
+nv50_sw_mthd_vblsem_value(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
+{
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
+ chan->vblank.value = *(u32 *)args;
+ return 0;
+}
+
+int
+nv50_sw_mthd_vblsem_release(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
+{
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
+ u32 head = *(u32 *)args;
+ if (head >= nvkm_disp(chan)->vblank.index_nr)
+ return -EINVAL;
+
+ nvkm_notify_get(&chan->vblank.notify[head]);
+ return 0;
+}
+
+int
+nv50_sw_mthd_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
+{
+ struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
+ if (chan->base.flip)
+ return chan->base.flip(chan->base.flip_data);
+ return -EINVAL;
+}
+
+static struct nvkm_omthds
+nv50_sw_omthds[] = {
+ { 0x018c, 0x018c, nv50_sw_mthd_dma_vblsem },
+ { 0x0400, 0x0400, nv50_sw_mthd_vblsem_offset },
+ { 0x0404, 0x0404, nv50_sw_mthd_vblsem_value },
+ { 0x0408, 0x0408, nv50_sw_mthd_vblsem_release },
+ { 0x0500, 0x0500, nv50_sw_mthd_flip },
+ {}
+};
+
+static struct nvkm_oclass
+nv50_sw_sclass[] = {
+ { 0x506e, &nvkm_object_ofuncs, nv50_sw_omthds },
+ {}
+};
+
+/*******************************************************************************
+ * software context
+ ******************************************************************************/
+
+static int
+nv50_sw_vblsem_release(struct nvkm_notify *notify)
+{
+ struct nv50_sw_chan *chan =
+ container_of(notify, typeof(*chan), vblank.notify[notify->index]);
+ struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
+ struct nvkm_bar *bar = nvkm_bar(priv);
+
+ nv_wr32(priv, 0x001704, chan->vblank.channel);
+ nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
+ bar->flush(bar);
+
+ if (nv_device(priv)->chipset == 0x50) {
+ nv_wr32(priv, 0x001570, chan->vblank.offset);
+ nv_wr32(priv, 0x001574, chan->vblank.value);
+ } else {
+ nv_wr32(priv, 0x060010, chan->vblank.offset);
+ nv_wr32(priv, 0x060014, chan->vblank.value);
+ }
+
+ return NVKM_NOTIFY_DROP;
+}
+
+void
+nv50_sw_context_dtor(struct nvkm_object *object)
+{
+ struct nv50_sw_chan *chan = (void *)object;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++)
+ nvkm_notify_fini(&chan->vblank.notify[i]);
+
+ nvkm_sw_context_destroy(&chan->base);
+}
+
+int
+nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
+{
+ struct nvkm_disp *pdisp = nvkm_disp(parent);
+ struct nv50_sw_cclass *pclass = (void *)oclass;
+ struct nv50_sw_chan *chan;
+ int ret, i;
+
+ ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
+ *pobject = nv_object(chan);
+ if (ret)
+ return ret;
+
+ for (i = 0; pdisp && i < pdisp->vblank.index_nr; i++) {
+ ret = nvkm_notify_init(NULL, &pdisp->vblank, pclass->vblank,
+ false,
+ &(struct nvif_notify_head_req_v0) {
+ .head = i,
+ },
+ sizeof(struct nvif_notify_head_req_v0),
+ sizeof(struct nvif_notify_head_rep_v0),
+ &chan->vblank.notify[i]);
+ if (ret)
+ return ret;
+ }
+
+ chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12;
+ return 0;
+}
+
+static struct nv50_sw_cclass
+nv50_sw_cclass = {
+ .base.handle = NV_ENGCTX(SW, 0x50),
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = nv50_sw_context_ctor,
+ .dtor = nv50_sw_context_dtor,
+ .init = _nvkm_sw_context_init,
+ .fini = _nvkm_sw_context_fini,
+ },
+ .vblank = nv50_sw_vblsem_release,
+};
+
+/*******************************************************************************
+ * software engine/subdev functions
+ ******************************************************************************/
+
+int
+nv50_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
+{
+ struct nv50_sw_oclass *pclass = (void *)oclass;
+ struct nv50_sw_priv *priv;
+ int ret;
+
+ ret = nvkm_sw_create(parent, engine, oclass, &priv);
+ *pobject = nv_object(priv);
+ if (ret)
+ return ret;
+
+ nv_engine(priv)->cclass = pclass->cclass;
+ nv_engine(priv)->sclass = pclass->sclass;
+ nv_subdev(priv)->intr = nv04_sw_intr;
+ return 0;
+}
+
+struct nvkm_oclass *
+nv50_sw_oclass = &(struct nv50_sw_oclass) {
+ .base.handle = NV_ENGINE(SW, 0x50),
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = nv50_sw_ctor,
+ .dtor = _nvkm_sw_dtor,
+ .init = _nvkm_sw_init,
+ .fini = _nvkm_sw_fini,
+ },
+ .cclass = &nv50_sw_cclass.base,
+ .sclass = nv50_sw_sclass,
+}.base;
diff --git a/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h b/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
new file mode 100644
index 000000000..d8adc1108
--- /dev/null
+++ b/kernel/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
@@ -0,0 +1,45 @@
+#ifndef __NVKM_SW_NV50_H__
+#define __NVKM_SW_NV50_H__
+#include <engine/sw.h>
+#include <core/notify.h>
+
+struct nv50_sw_oclass {
+ struct nvkm_oclass base;
+ struct nvkm_oclass *cclass;
+ struct nvkm_oclass *sclass;
+};
+
+struct nv50_sw_priv {
+ struct nvkm_sw base;
+};
+
+int nv50_sw_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+
+struct nv50_sw_cclass {
+ struct nvkm_oclass base;
+ int (*vblank)(struct nvkm_notify *);
+};
+
+struct nv50_sw_chan {
+ struct nvkm_sw_chan base;
+ struct {
+ struct nvkm_notify notify[4];
+ u32 channel;
+ u32 ctxdma;
+ u64 offset;
+ u32 value;
+ } vblank;
+};
+
+int nv50_sw_context_ctor(struct nvkm_object *,
+ struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void nv50_sw_context_dtor(struct nvkm_object *);
+
+int nv50_sw_mthd_vblsem_value(struct nvkm_object *, u32, void *, u32);
+int nv50_sw_mthd_vblsem_release(struct nvkm_object *, u32, void *, u32);
+int nv50_sw_mthd_flip(struct nvkm_object *, u32, void *, u32);
+#endif