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authorDon Dugger <donald.d.dugger@intel.com>2015-10-29 22:15:25 +0000
committerGerrit Code Review <gerrit@172.30.200.206>2015-10-29 22:15:25 +0000
commitafc76d554ed517e38d46b6b182a7016406a1323f (patch)
tree06133cb33a43488837ea67667458e1582f2f40ce /kernel/drivers/clk/pistachio/clk-pistachio.c
parent41f827bfbb10e03c4d228fbcc801dd51fb9983b0 (diff)
parentec0a2ed6d8a5e555edef907895c041e285fdb495 (diff)
Merge "These changes are a raw update to a vanilla kernel 4.1.10, with the recently announced rt patch patch-4.1.10-rt10.patch. No further changes needed."
Diffstat (limited to 'kernel/drivers/clk/pistachio/clk-pistachio.c')
-rw-r--r--kernel/drivers/clk/pistachio/clk-pistachio.c19
1 files changed, 14 insertions, 5 deletions
diff --git a/kernel/drivers/clk/pistachio/clk-pistachio.c b/kernel/drivers/clk/pistachio/clk-pistachio.c
index 8c0fe8828..c4ceb5eaf 100644
--- a/kernel/drivers/clk/pistachio/clk-pistachio.c
+++ b/kernel/drivers/clk/pistachio/clk-pistachio.c
@@ -159,9 +159,15 @@ PNAME(mux_debug) = { "mips_pll_mux", "rpu_v_pll_mux",
"wifi_pll_mux", "bt_pll_mux" };
static u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 };
-static unsigned int pistachio_critical_clks[] __initdata = {
- CLK_MIPS,
- CLK_PERIPH_SYS,
+static unsigned int pistachio_critical_clks_core[] __initdata = {
+ CLK_MIPS
+};
+
+static unsigned int pistachio_critical_clks_sys[] __initdata = {
+ PERIPH_CLK_SYS,
+ PERIPH_CLK_SYS_BUS,
+ PERIPH_CLK_DDR,
+ PERIPH_CLK_ROM,
};
static void __init pistachio_clk_init(struct device_node *np)
@@ -193,8 +199,8 @@ static void __init pistachio_clk_init(struct device_node *np)
pistachio_clk_register_provider(p);
- pistachio_clk_force_enable(p, pistachio_critical_clks,
- ARRAY_SIZE(pistachio_critical_clks));
+ pistachio_clk_force_enable(p, pistachio_critical_clks_core,
+ ARRAY_SIZE(pistachio_critical_clks_core));
}
CLK_OF_DECLARE(pistachio_clk, "img,pistachio-clk", pistachio_clk_init);
@@ -261,6 +267,9 @@ static void __init pistachio_clk_periph_init(struct device_node *np)
ARRAY_SIZE(pistachio_periph_gates));
pistachio_clk_register_provider(p);
+
+ pistachio_clk_force_enable(p, pistachio_critical_clks_sys,
+ ARRAY_SIZE(pistachio_critical_clks_sys));
}
CLK_OF_DECLARE(pistachio_clk_periph, "img,pistachio-clk-periph",
pistachio_clk_periph_init);