diff options
author | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 12:17:53 -0700 |
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committer | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 15:44:42 -0700 |
commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/unicore32/include/mach/regs-spi.h | |
parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/unicore32/include/mach/regs-spi.h')
-rw-r--r-- | kernel/arch/unicore32/include/mach/regs-spi.h | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/kernel/arch/unicore32/include/mach/regs-spi.h b/kernel/arch/unicore32/include/mach/regs-spi.h new file mode 100644 index 000000000..de16895e2 --- /dev/null +++ b/kernel/arch/unicore32/include/mach/regs-spi.h @@ -0,0 +1,98 @@ +/* + * PKUnity Serial Peripheral Interface (SPI) Registers + */ +/* + * Control reg. 0 SPI_CR0 + */ +#define SPI_CR0 (PKUNITY_SPI_BASE + 0x0000) +/* + * Control reg. 1 SPI_CR1 + */ +#define SPI_CR1 (PKUNITY_SPI_BASE + 0x0004) +/* + * Enable reg SPI_SSIENR + */ +#define SPI_SSIENR (PKUNITY_SPI_BASE + 0x0008) +/* + * Status reg SPI_SR + */ +#define SPI_SR (PKUNITY_SPI_BASE + 0x0028) +/* + * Interrupt Mask reg SPI_IMR + */ +#define SPI_IMR (PKUNITY_SPI_BASE + 0x002C) +/* + * Interrupt Status reg SPI_ISR + */ +#define SPI_ISR (PKUNITY_SPI_BASE + 0x0030) + +/* + * Enable SPI Controller SPI_SSIENR_EN + */ +#define SPI_SSIENR_EN FIELD(1, 1, 0) + +/* + * SPI Busy SPI_SR_BUSY + */ +#define SPI_SR_BUSY FIELD(1, 1, 0) +/* + * Transmit FIFO Not Full SPI_SR_TFNF + */ +#define SPI_SR_TFNF FIELD(1, 1, 1) +/* + * Transmit FIFO Empty SPI_SR_TFE + */ +#define SPI_SR_TFE FIELD(1, 1, 2) +/* + * Receive FIFO Not Empty SPI_SR_RFNE + */ +#define SPI_SR_RFNE FIELD(1, 1, 3) +/* + * Receive FIFO Full SPI_SR_RFF + */ +#define SPI_SR_RFF FIELD(1, 1, 4) + +/* + * Trans. FIFO Empty Interrupt Status SPI_ISR_TXEIS + */ +#define SPI_ISR_TXEIS FIELD(1, 1, 0) +/* + * Trans. FIFO Overflow Interrupt Status SPI_ISR_TXOIS + */ +#define SPI_ISR_TXOIS FIELD(1, 1, 1) +/* + * Receiv. FIFO Underflow Interrupt Status SPI_ISR_RXUIS + */ +#define SPI_ISR_RXUIS FIELD(1, 1, 2) +/* + * Receiv. FIFO Overflow Interrupt Status SPI_ISR_RXOIS + */ +#define SPI_ISR_RXOIS FIELD(1, 1, 3) +/* + * Receiv. FIFO Full Interrupt Status SPI_ISR_RXFIS + */ +#define SPI_ISR_RXFIS FIELD(1, 1, 4) +#define SPI_ISR_MSTIS FIELD(1, 1, 5) + +/* + * Trans. FIFO Empty Interrupt Mask SPI_IMR_TXEIM + */ +#define SPI_IMR_TXEIM FIELD(1, 1, 0) +/* + * Trans. FIFO Overflow Interrupt Mask SPI_IMR_TXOIM + */ +#define SPI_IMR_TXOIM FIELD(1, 1, 1) +/* + * Receiv. FIFO Underflow Interrupt Mask SPI_IMR_RXUIM + */ +#define SPI_IMR_RXUIM FIELD(1, 1, 2) +/* + * Receiv. FIFO Overflow Interrupt Mask SPI_IMR_RXOIM + */ +#define SPI_IMR_RXOIM FIELD(1, 1, 3) +/* + * Receiv. FIFO Full Interrupt Mask SPI_IMR_RXFIM + */ +#define SPI_IMR_RXFIM FIELD(1, 1, 4) +#define SPI_IMR_MSTIM FIELD(1, 1, 5) + |