diff options
author | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 12:17:53 -0700 |
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committer | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 15:44:42 -0700 |
commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/m32r/boot/compressed/m32r_sio.c | |
parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/m32r/boot/compressed/m32r_sio.c')
-rw-r--r-- | kernel/arch/m32r/boot/compressed/m32r_sio.c | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/kernel/arch/m32r/boot/compressed/m32r_sio.c b/kernel/arch/m32r/boot/compressed/m32r_sio.c new file mode 100644 index 000000000..01d877c68 --- /dev/null +++ b/kernel/arch/m32r/boot/compressed/m32r_sio.c @@ -0,0 +1,75 @@ +/* + * arch/m32r/boot/compressed/m32r_sio.c + * + * 2003-02-12: Takeo Takahashi + * 2006-11-30: OPSPUT support by Kazuhiro Inaoka + * + */ + +#include <asm/processor.h> + +static void putc(char c); + +static int puts(const char *s) +{ + char c; + while ((c = *s++)) putc(c); + return 0; +} + +#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) +#include <asm/m32r.h> +#include <asm/io.h> + +#define USE_FPGA_MAP 0 + +#if USE_FPGA_MAP +/* + * fpga configuration program uses MMU, and define map as same as + * M32104 uT-Engine board. + */ +#define BOOT_SIO0STS (volatile unsigned short *)(0x02c00000 + 0x20006) +#define BOOT_SIO0TXB (volatile unsigned short *)(0x02c00000 + 0x2000c) +#else +#undef PLD_BASE +#if defined(CONFIG_PLAT_OPSPUT) +#define PLD_BASE 0x1cc00000 +#else +#define PLD_BASE 0xa4c00000 +#endif +#define BOOT_SIO0STS PLD_ESIO0STS +#define BOOT_SIO0TXB PLD_ESIO0TXB +#endif + +static void putc(char c) +{ + while ((*BOOT_SIO0STS & 0x3) != 0x3) + cpu_relax(); + if (c == '\n') { + *BOOT_SIO0TXB = '\r'; + while ((*BOOT_SIO0STS & 0x3) != 0x3) + cpu_relax(); + } + *BOOT_SIO0TXB = c; +} +#else /* !(CONFIG_PLAT_M32700UT) */ +#if defined(CONFIG_PLAT_MAPPI2) +#define SIO0STS (volatile unsigned short *)(0xa0efd000 + 14) +#define SIO0TXB (volatile unsigned short *)(0xa0efd000 + 30) +#else +#define SIO0STS (volatile unsigned short *)(0x00efd000 + 14) +#define SIO0TXB (volatile unsigned short *)(0x00efd000 + 30) +#endif + +static void putc(char c) +{ + while ((*SIO0STS & 0x1) == 0) + cpu_relax(); + if (c == '\n') { + *SIO0TXB = '\r'; + while ((*SIO0STS & 0x1) == 0) + cpu_relax(); + } + *SIO0TXB = c; +} +#endif |