diff options
| author |   Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 12:17:53 -0700 |
|---|---|---|
| committer | Yunhong Jiang <yunhong.jiang@intel.com> | 2015-08-04 15:44:42 -0700 |
| commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
| tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/blackfin/include/asm | |
| parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) | |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/blackfin/include/asm')
95 files changed, 12108 insertions, 0 deletions
diff --git a/kernel/arch/blackfin/include/asm/Kbuild b/kernel/arch/blackfin/include/asm/Kbuild new file mode 100644 index 000000000..4bd3c3cfc --- /dev/null +++ b/kernel/arch/blackfin/include/asm/Kbuild @@ -0,0 +1,49 @@ + +generic-y += auxvec.h +generic-y += bitsperlong.h +generic-y += bugs.h +generic-y += cputime.h +generic-y += current.h +generic-y += device.h +generic-y += div64.h +generic-y += emergency-restart.h +generic-y += errno.h +generic-y += fb.h +generic-y += futex.h +generic-y += hw_irq.h +generic-y += ioctl.h +generic-y += ipcbuf.h +generic-y += irq_regs.h +generic-y += irq_work.h +generic-y += kdebug.h +generic-y += kmap_types.h +generic-y += kvm_para.h +generic-y += local.h +generic-y += local64.h +generic-y += mcs_spinlock.h +generic-y += mman.h +generic-y += msgbuf.h +generic-y += mutex.h +generic-y += param.h +generic-y += percpu.h +generic-y += pgalloc.h +generic-y += preempt.h +generic-y += resource.h +generic-y += scatterlist.h +generic-y += sembuf.h +generic-y += serial.h +generic-y += setup.h +generic-y += shmbuf.h +generic-y += shmparam.h +generic-y += socket.h +generic-y += sockios.h +generic-y += statfs.h +generic-y += termbits.h +generic-y += termios.h +generic-y += topology.h +generic-y += trace_clock.h +generic-y += types.h +generic-y += ucontext.h +generic-y += unaligned.h +generic-y += user.h +generic-y += xor.h diff --git a/kernel/arch/blackfin/include/asm/asm-offsets.h b/kernel/arch/blackfin/include/asm/asm-offsets.h new file mode 100644 index 000000000..d370ee36a --- /dev/null +++ b/kernel/arch/blackfin/include/asm/asm-offsets.h @@ -0,0 +1 @@ +#include <generated/asm-offsets.h> diff --git a/kernel/arch/blackfin/include/asm/atomic.h b/kernel/arch/blackfin/include/asm/atomic.h new file mode 100644 index 000000000..a107a98e9 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/atomic.h @@ -0,0 +1,37 @@ +/* + * Copyright 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ARCH_BLACKFIN_ATOMIC__ +#define __ARCH_BLACKFIN_ATOMIC__ + +#include <asm/cmpxchg.h> + +#ifdef CONFIG_SMP + +#include <asm/barrier.h> +#include <linux/linkage.h> +#include <linux/types.h> + +asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr); +asmlinkage int __raw_atomic_update_asm(volatile int *ptr, int value); +asmlinkage int __raw_atomic_clear_asm(volatile int *ptr, int value); +asmlinkage int __raw_atomic_set_asm(volatile int *ptr, int value); +asmlinkage int __raw_atomic_xor_asm(volatile int *ptr, int value); +asmlinkage int __raw_atomic_test_asm(const volatile int *ptr, int value); + +#define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter) + +#define atomic_add_return(i, v) __raw_atomic_update_asm(&(v)->counter, i) +#define atomic_sub_return(i, v) __raw_atomic_update_asm(&(v)->counter, -(i)) + +#define atomic_clear_mask(m, v) __raw_atomic_clear_asm(&(v)->counter, m) +#define atomic_set_mask(m, v) __raw_atomic_set_asm(&(v)->counter, m) + +#endif + +#include <asm-generic/atomic.h> + +#endif diff --git a/kernel/arch/blackfin/include/asm/barrier.h b/kernel/arch/blackfin/include/asm/barrier.h new file mode 100644 index 000000000..dfb66fe88 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/barrier.h @@ -0,0 +1,86 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * Tony Kou (tonyko@lineo.ca) + * + * Licensed under the GPL-2 or later + */ + +#ifndef _BLACKFIN_BARRIER_H +#define _BLACKFIN_BARRIER_H + +#include <asm/cache.h> + +#define nop() __asm__ __volatile__ ("nop;\n\t" : : ) + +/* + * Force strict CPU ordering. + */ +#ifdef CONFIG_SMP + +#ifdef __ARCH_SYNC_CORE_DCACHE +/* Force Core data cache coherence */ +# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0) +# define rmb() do { barrier(); smp_check_barrier(); } while (0) +# define wmb() do { barrier(); smp_mark_barrier(); } while (0) +/* + * read_barrier_depends - Flush all pending reads that subsequents reads + * depend on. + * + * No data-dependent reads from memory-like regions are ever reordered + * over this barrier. All reads preceding this primitive are guaranteed + * to access memory (but not necessarily other CPUs' caches) before any + * reads following this primitive that depend on the data return by + * any of the preceding reads. This primitive is much lighter weight than + * rmb() on most CPUs, and is never heavier weight than is + * rmb(). + * + * These ordering constraints are respected by both the local CPU + * and the compiler. + * + * Ordering is not guaranteed by anything other than these primitives, + * not even by data dependencies. See the documentation for + * memory_barrier() for examples and URLs to more information. + * + * For example, the following code would force ordering (the initial + * value of "a" is zero, "b" is one, and "p" is "&a"): + * + * <programlisting> + * CPU 0 CPU 1 + * + * b = 2; + * memory_barrier(); + * p = &b; q = p; + * read_barrier_depends(); + * d = *q; + * </programlisting> + * + * because the read of "*q" depends on the read of "p" and these + * two reads are separated by a read_barrier_depends(). However, + * the following code, with the same initial values for "a" and "b": + * + * <programlisting> + * CPU 0 CPU 1 + * + * a = 2; + * memory_barrier(); + * b = 3; y = b; + * read_barrier_depends(); + * x = a; + * </programlisting> + * + * does not enforce ordering, since there is no data dependency between + * the read of "a" and the read of "b". Therefore, on some CPUs, such + * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() + * in cases like this where there are no data dependencies. + */ +# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0) +#endif + +#endif /* !CONFIG_SMP */ + +#define smp_mb__before_atomic() barrier() +#define smp_mb__after_atomic() barrier() + +#include <asm-generic/barrier.h> + +#endif /* _BLACKFIN_BARRIER_H */ diff --git a/kernel/arch/blackfin/include/asm/bfin-global.h b/kernel/arch/blackfin/include/asm/bfin-global.h new file mode 100644 index 000000000..dc47d7928 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin-global.h @@ -0,0 +1,95 @@ +/* + * Global extern defines for blackfin + * + * Copyright 2006-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BFIN_GLOBAL_H_ +#define _BFIN_GLOBAL_H_ + +#ifndef __ASSEMBLY__ + +#include <linux/linkage.h> +#include <linux/types.h> + +#if defined(CONFIG_DMA_UNCACHED_32M) +# define DMA_UNCACHED_REGION (32 * 1024 * 1024) +#elif defined(CONFIG_DMA_UNCACHED_16M) +# define DMA_UNCACHED_REGION (16 * 1024 * 1024) +#elif defined(CONFIG_DMA_UNCACHED_8M) +# define DMA_UNCACHED_REGION (8 * 1024 * 1024) +#elif defined(CONFIG_DMA_UNCACHED_4M) +# define DMA_UNCACHED_REGION (4 * 1024 * 1024) +#elif defined(CONFIG_DMA_UNCACHED_2M) +# define DMA_UNCACHED_REGION (2 * 1024 * 1024) +#elif defined(CONFIG_DMA_UNCACHED_1M) +# define DMA_UNCACHED_REGION (1024 * 1024) +#elif defined(CONFIG_DMA_UNCACHED_512K) +# define DMA_UNCACHED_REGION (512 * 1024) +#elif defined(CONFIG_DMA_UNCACHED_256K) +# define DMA_UNCACHED_REGION (256 * 1024) +#elif defined(CONFIG_DMA_UNCACHED_128K) +# define DMA_UNCACHED_REGION (128 * 1024) +#else +# define DMA_UNCACHED_REGION (0) +#endif + +extern void bfin_setup_caches(unsigned int cpu); +extern void bfin_setup_cpudata(unsigned int cpu); + +extern unsigned long get_cclk(void); +extern unsigned long get_sclk(void); +#ifdef CONFIG_BF60x +extern unsigned long get_sclk0(void); +extern unsigned long get_sclk1(void); +extern unsigned long get_dclk(void); +#endif +extern unsigned long sclk_to_usecs(unsigned long sclk); +extern unsigned long usecs_to_sclk(unsigned long usecs); + +struct pt_regs; +#if defined(CONFIG_DEBUG_VERBOSE) +extern void dump_bfin_process(struct pt_regs *regs); +extern void dump_bfin_mem(struct pt_regs *regs); +extern void dump_bfin_trace_buffer(void); +#else +#define dump_bfin_process(regs) +#define dump_bfin_mem(regs) +#define dump_bfin_trace_buffer() +#endif + +extern void *l1_data_A_sram_alloc(size_t); +extern void *l1_data_B_sram_alloc(size_t); +extern void *l1_inst_sram_alloc(size_t); +extern void *l1_data_sram_alloc(size_t); +extern void *l1_data_sram_zalloc(size_t); +extern void *l2_sram_alloc(size_t); +extern void *l2_sram_zalloc(size_t); +extern int l1_data_A_sram_free(const void*); +extern int l1_data_B_sram_free(const void*); +extern int l1_inst_sram_free(const void*); +extern int l1_data_sram_free(const void*); +extern int l2_sram_free(const void *); +extern int sram_free(const void*); + +#define L1_INST_SRAM 0x00000001 +#define L1_DATA_A_SRAM 0x00000002 +#define L1_DATA_B_SRAM 0x00000004 +#define L1_DATA_SRAM 0x00000006 +#define L2_SRAM 0x00000008 +extern void *sram_alloc_with_lsl(size_t, unsigned long); +extern int sram_free_with_lsl(const void*); + +extern void *isram_memcpy(void *dest, const void *src, size_t n); + +extern const char bfin_board_name[]; + +extern unsigned long bfin_sic_iwr[]; +extern unsigned vr_wakeup; +extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */ + +#endif + +#endif /* _BLACKFIN_H_ */ diff --git a/kernel/arch/blackfin/include/asm/bfin-lq035q1.h b/kernel/arch/blackfin/include/asm/bfin-lq035q1.h new file mode 100644 index 000000000..836895156 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin-lq035q1.h @@ -0,0 +1,40 @@ +/* + * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02 + * + * Copyright 2008-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef BFIN_LQ035Q1_H +#define BFIN_LQ035Q1_H + +/* + * LCD Modes + */ +#define LQ035_RL (0 << 8) /* Right -> Left Scan */ +#define LQ035_LR (1 << 8) /* Left -> Right Scan */ +#define LQ035_TB (1 << 9) /* Top -> Botton Scan */ +#define LQ035_BT (0 << 9) /* Botton -> Top Scan */ +#define LQ035_BGR (1 << 11) /* Use BGR format */ +#define LQ035_RGB (0 << 11) /* Use RGB format */ +#define LQ035_NORM (1 << 13) /* Reversal */ +#define LQ035_REV (0 << 13) /* Reversal */ + +/* + * PPI Modes + */ + +#define USE_RGB565_16_BIT_PPI 1 +#define USE_RGB565_8_BIT_PPI 2 +#define USE_RGB888_8_BIT_PPI 3 + +struct bfin_lq035q1fb_disp_info { + + unsigned mode; + unsigned ppi_mode; + /* GPIOs */ + int use_bl; + unsigned gpio_bl; +}; + +#endif /* BFIN_LQ035Q1_H */ diff --git a/kernel/arch/blackfin/include/asm/bfin5xx_spi.h b/kernel/arch/blackfin/include/asm/bfin5xx_spi.h new file mode 100644 index 000000000..fb95c853b --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin5xx_spi.h @@ -0,0 +1,86 @@ +/* + * Blackfin On-Chip SPI Driver + * + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _SPI_CHANNEL_H_ +#define _SPI_CHANNEL_H_ + +#define MIN_SPI_BAUD_VAL 2 + +#define BIT_CTL_ENABLE 0x4000 +#define BIT_CTL_OPENDRAIN 0x2000 +#define BIT_CTL_MASTER 0x1000 +#define BIT_CTL_CPOL 0x0800 +#define BIT_CTL_CPHA 0x0400 +#define BIT_CTL_LSBF 0x0200 +#define BIT_CTL_WORDSIZE 0x0100 +#define BIT_CTL_EMISO 0x0020 +#define BIT_CTL_PSSE 0x0010 +#define BIT_CTL_GM 0x0008 +#define BIT_CTL_SZ 0x0004 +#define BIT_CTL_RXMOD 0x0000 +#define BIT_CTL_TXMOD 0x0001 +#define BIT_CTL_TIMOD_DMA_TX 0x0003 +#define BIT_CTL_TIMOD_DMA_RX 0x0002 +#define BIT_CTL_SENDOPT 0x0004 +#define BIT_CTL_TIMOD 0x0003 + +#define BIT_STAT_SPIF 0x0001 +#define BIT_STAT_MODF 0x0002 +#define BIT_STAT_TXE 0x0004 +#define BIT_STAT_TXS 0x0008 +#define BIT_STAT_RBSY 0x0010 +#define BIT_STAT_RXS 0x0020 +#define BIT_STAT_TXCOL 0x0040 +#define BIT_STAT_CLR 0xFFFF + +#define BIT_STU_SENDOVER 0x0001 +#define BIT_STU_RECVFULL 0x0020 + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m + +/* + * bfin spi registers layout + */ +struct bfin_spi_regs { + __BFP(ctl); + __BFP(flg); + __BFP(stat); + __BFP(tdbr); + __BFP(rdbr); + __BFP(baud); + __BFP(shadow); +}; + +#undef __BFP + +#define MAX_CTRL_CS 8 /* cs in spi controller */ + +/* device.platform_data for SSP controller devices */ +struct bfin5xx_spi_master { + u16 num_chipselect; + u8 enable_dma; + u16 pin_req[7]; +}; + +/* spi_board_info.controller_data for SPI slave devices, + * copied to spi_device.platform_data ... mostly for dma tuning + */ +struct bfin5xx_spi_chip { + u16 ctl_reg; + u8 enable_dma; + u16 cs_chg_udelay; /* Some devices require 16-bit delays */ + /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */ + u16 idle_tx_val; + u8 pio_interrupt; /* Enable spi data irq */ +}; + +#endif /* _SPI_CHANNEL_H_ */ diff --git a/kernel/arch/blackfin/include/asm/bfin_can.h b/kernel/arch/blackfin/include/asm/bfin_can.h new file mode 100644 index 000000000..b1492e0bc --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin_can.h @@ -0,0 +1,728 @@ +/* + * bfin_can.h - interface to Blackfin CANs + * + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BFIN_CAN_H__ +#define __ASM_BFIN_CAN_H__ + +/* + * transmit and receive channels + */ +#define TRANSMIT_CHL 24 +#define RECEIVE_STD_CHL 0 +#define RECEIVE_EXT_CHL 4 +#define RECEIVE_RTR_CHL 8 +#define RECEIVE_EXT_RTR_CHL 12 +#define MAX_CHL_NUMBER 32 + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m + +/* + * bfin can registers layout + */ +struct bfin_can_mask_regs { + __BFP(aml); + __BFP(amh); +}; + +struct bfin_can_channel_regs { + /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */ + u16 data[8]; + __BFP(dlc); + __BFP(tsv); + __BFP(id0); + __BFP(id1); +}; + +struct bfin_can_regs { + /* + * global control and status registers + */ + __BFP(mc1); /* offset 0x00 */ + __BFP(md1); /* offset 0x04 */ + __BFP(trs1); /* offset 0x08 */ + __BFP(trr1); /* offset 0x0c */ + __BFP(ta1); /* offset 0x10 */ + __BFP(aa1); /* offset 0x14 */ + __BFP(rmp1); /* offset 0x18 */ + __BFP(rml1); /* offset 0x1c */ + __BFP(mbtif1); /* offset 0x20 */ + __BFP(mbrif1); /* offset 0x24 */ + __BFP(mbim1); /* offset 0x28 */ + __BFP(rfh1); /* offset 0x2c */ + __BFP(opss1); /* offset 0x30 */ + u32 __pad1[3]; + __BFP(mc2); /* offset 0x40 */ + __BFP(md2); /* offset 0x44 */ + __BFP(trs2); /* offset 0x48 */ + __BFP(trr2); /* offset 0x4c */ + __BFP(ta2); /* offset 0x50 */ + __BFP(aa2); /* offset 0x54 */ + __BFP(rmp2); /* offset 0x58 */ + __BFP(rml2); /* offset 0x5c */ + __BFP(mbtif2); /* offset 0x60 */ + __BFP(mbrif2); /* offset 0x64 */ + __BFP(mbim2); /* offset 0x68 */ + __BFP(rfh2); /* offset 0x6c */ + __BFP(opss2); /* offset 0x70 */ + u32 __pad2[3]; + __BFP(clock); /* offset 0x80 */ + __BFP(timing); /* offset 0x84 */ + __BFP(debug); /* offset 0x88 */ + __BFP(status); /* offset 0x8c */ + __BFP(cec); /* offset 0x90 */ + __BFP(gis); /* offset 0x94 */ + __BFP(gim); /* offset 0x98 */ + __BFP(gif); /* offset 0x9c */ + __BFP(control); /* offset 0xa0 */ + __BFP(intr); /* offset 0xa4 */ + __BFP(version); /* offset 0xa8 */ + __BFP(mbtd); /* offset 0xac */ + __BFP(ewr); /* offset 0xb0 */ + __BFP(esr); /* offset 0xb4 */ + u32 __pad3[2]; + __BFP(ucreg); /* offset 0xc0 */ + __BFP(uccnt); /* offset 0xc4 */ + __BFP(ucrc); /* offset 0xc8 */ + __BFP(uccnf); /* offset 0xcc */ + u32 __pad4[1]; + __BFP(version2); /* offset 0xd4 */ + u32 __pad5[10]; + + /* + * channel(mailbox) mask and message registers + */ + struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */ + struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */ +}; + +#undef __BFP + +/* CAN_CONTROL Masks */ +#define SRS 0x0001 /* Software Reset */ +#define DNM 0x0002 /* Device Net Mode */ +#define ABO 0x0004 /* Auto-Bus On Enable */ +#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */ +#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */ +#define SMR 0x0020 /* Sleep Mode Request */ +#define CSR 0x0040 /* CAN Suspend Mode Request */ +#define CCR 0x0080 /* CAN Configuration Mode Request */ + +/* CAN_STATUS Masks */ +#define WT 0x0001 /* TX Warning Flag */ +#define WR 0x0002 /* RX Warning Flag */ +#define EP 0x0004 /* Error Passive Mode */ +#define EBO 0x0008 /* Error Bus Off Mode */ +#define SMA 0x0020 /* Sleep Mode Acknowledge */ +#define CSA 0x0040 /* Suspend Mode Acknowledge */ +#define CCA 0x0080 /* Configuration Mode Acknowledge */ +#define MBPTR 0x1F00 /* Mailbox Pointer */ +#define TRM 0x4000 /* Transmit Mode */ +#define REC 0x8000 /* Receive Mode */ + +/* CAN_CLOCK Masks */ +#define BRP 0x03FF /* Bit-Rate Pre-Scaler */ + +/* CAN_TIMING Masks */ +#define TSEG1 0x000F /* Time Segment 1 */ +#define TSEG2 0x0070 /* Time Segment 2 */ +#define SAM 0x0080 /* Sampling */ +#define SJW 0x0300 /* Synchronization Jump Width */ + +/* CAN_DEBUG Masks */ +#define DEC 0x0001 /* Disable CAN Error Counters */ +#define DRI 0x0002 /* Disable CAN RX Input */ +#define DTO 0x0004 /* Disable CAN TX Output */ +#define DIL 0x0008 /* Disable CAN Internal Loop */ +#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */ +#define MRB 0x0020 /* Mode Read Back Enable */ +#define CDE 0x8000 /* CAN Debug Enable */ + +/* CAN_CEC Masks */ +#define RXECNT 0x00FF /* Receive Error Counter */ +#define TXECNT 0xFF00 /* Transmit Error Counter */ + +/* CAN_INTR Masks */ +#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */ +#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */ +#define GIRQ 0x0004 /* Global Interrupt */ +#define SMACK 0x0008 /* Sleep Mode Acknowledge */ +#define CANTX 0x0040 /* CAN TX Bus Value */ +#define CANRX 0x0080 /* CAN RX Bus Value */ + +/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */ +#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */ +#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */ +#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */ +#define BASEID 0x1FFC /* Base Identifier */ +#define IDE 0x2000 /* Identifier Extension */ +#define RTR 0x4000 /* Remote Frame Transmission Request */ +#define AME 0x8000 /* Acceptance Mask Enable */ + +/* CAN_MBxx_TIMESTAMP Masks */ +#define TSV 0xFFFF /* Timestamp */ + +/* CAN_MBxx_LENGTH Masks */ +#define DLC 0x000F /* Data Length Code */ + +/* CAN_AMxxH and CAN_AMxxL Masks */ +#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */ +#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */ +#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */ +#define BASEID 0x1FFC /* Base Identifier */ +#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */ +#define FMD 0x4000 /* Full Mask Data Field Enable */ +#define FDF 0x8000 /* Filter On Data Field Enable */ + +/* CAN_MC1 Masks */ +#define MC0 0x0001 /* Enable Mailbox 0 */ +#define MC1 0x0002 /* Enable Mailbox 1 */ +#define MC2 0x0004 /* Enable Mailbox 2 */ +#define MC3 0x0008 /* Enable Mailbox 3 */ +#define MC4 0x0010 /* Enable Mailbox 4 */ +#define MC5 0x0020 /* Enable Mailbox 5 */ +#define MC6 0x0040 /* Enable Mailbox 6 */ +#define MC7 0x0080 /* Enable Mailbox 7 */ +#define MC8 0x0100 /* Enable Mailbox 8 */ +#define MC9 0x0200 /* Enable Mailbox 9 */ +#define MC10 0x0400 /* Enable Mailbox 10 */ +#define MC11 0x0800 /* Enable Mailbox 11 */ +#define MC12 0x1000 /* Enable Mailbox 12 */ +#define MC13 0x2000 /* Enable Mailbox 13 */ +#define MC14 0x4000 /* Enable Mailbox 14 */ +#define MC15 0x8000 /* Enable Mailbox 15 */ + +/* CAN_MC2 Masks */ +#define MC16 0x0001 /* Enable Mailbox 16 */ +#define MC17 0x0002 /* Enable Mailbox 17 */ +#define MC18 0x0004 /* Enable Mailbox 18 */ +#define MC19 0x0008 /* Enable Mailbox 19 */ +#define MC20 0x0010 /* Enable Mailbox 20 */ +#define MC21 0x0020 /* Enable Mailbox 21 */ +#define MC22 0x0040 /* Enable Mailbox 22 */ +#define MC23 0x0080 /* Enable Mailbox 23 */ +#define MC24 0x0100 /* Enable Mailbox 24 */ +#define MC25 0x0200 /* Enable Mailbox 25 */ +#define MC26 0x0400 /* Enable Mailbox 26 */ +#define MC27 0x0800 /* Enable Mailbox 27 */ +#define MC28 0x1000 /* Enable Mailbox 28 */ +#define MC29 0x2000 /* Enable Mailbox 29 */ +#define MC30 0x4000 /* Enable Mailbox 30 */ +#define MC31 0x8000 /* Enable Mailbox 31 */ + +/* CAN_MD1 Masks */ +#define MD0 0x0001 /* Enable Mailbox 0 For Receive */ +#define MD1 0x0002 /* Enable Mailbox 1 For Receive */ +#define MD2 0x0004 /* Enable Mailbox 2 For Receive */ +#define MD3 0x0008 /* Enable Mailbox 3 For Receive */ +#define MD4 0x0010 /* Enable Mailbox 4 For Receive */ +#define MD5 0x0020 /* Enable Mailbox 5 For Receive */ +#define MD6 0x0040 /* Enable Mailbox 6 For Receive */ +#define MD7 0x0080 /* Enable Mailbox 7 For Receive */ +#define MD8 0x0100 /* Enable Mailbox 8 For Receive */ +#define MD9 0x0200 /* Enable Mailbox 9 For Receive */ +#define MD10 0x0400 /* Enable Mailbox 10 For Receive */ +#define MD11 0x0800 /* Enable Mailbox 11 For Receive */ +#define MD12 0x1000 /* Enable Mailbox 12 For Receive */ +#define MD13 0x2000 /* Enable Mailbox 13 For Receive */ +#define MD14 0x4000 /* Enable Mailbox 14 For Receive */ +#define MD15 0x8000 /* Enable Mailbox 15 For Receive */ + +/* CAN_MD2 Masks */ +#define MD16 0x0001 /* Enable Mailbox 16 For Receive */ +#define MD17 0x0002 /* Enable Mailbox 17 For Receive */ +#define MD18 0x0004 /* Enable Mailbox 18 For Receive */ +#define MD19 0x0008 /* Enable Mailbox 19 For Receive */ +#define MD20 0x0010 /* Enable Mailbox 20 For Receive */ +#define MD21 0x0020 /* Enable Mailbox 21 For Receive */ +#define MD22 0x0040 /* Enable Mailbox 22 For Receive */ +#define MD23 0x0080 /* Enable Mailbox 23 For Receive */ +#define MD24 0x0100 /* Enable Mailbox 24 For Receive */ +#define MD25 0x0200 /* Enable Mailbox 25 For Receive */ +#define MD26 0x0400 /* Enable Mailbox 26 For Receive */ +#define MD27 0x0800 /* Enable Mailbox 27 For Receive */ +#define MD28 0x1000 /* Enable Mailbox 28 For Receive */ +#define MD29 0x2000 /* Enable Mailbox 29 For Receive */ +#define MD30 0x4000 /* Enable Mailbox 30 For Receive */ +#define MD31 0x8000 /* Enable Mailbox 31 For Receive */ + +/* CAN_RMP1 Masks */ +#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */ +#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */ +#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */ +#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */ +#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */ +#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */ +#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */ +#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */ +#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */ +#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */ +#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */ +#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */ +#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */ +#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */ +#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */ +#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */ + +/* CAN_RMP2 Masks */ +#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */ +#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */ +#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */ +#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */ +#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */ +#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */ +#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */ +#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */ +#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */ +#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */ +#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */ +#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */ +#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */ +#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */ +#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */ +#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */ + +/* CAN_RML1 Masks */ +#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */ +#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */ +#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */ +#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */ +#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */ +#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */ +#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */ +#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */ +#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */ +#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */ +#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */ +#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */ +#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */ +#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */ +#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */ +#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */ + +/* CAN_RML2 Masks */ +#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */ +#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */ +#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */ +#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */ +#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */ +#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */ +#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */ +#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */ +#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */ +#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */ +#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */ +#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */ +#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */ +#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */ +#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */ +#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */ + +/* CAN_OPSS1 Masks */ +#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */ +#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */ +#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */ +#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */ +#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */ +#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */ +#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */ +#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */ +#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */ +#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */ +#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */ +#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */ +#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */ +#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */ +#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */ +#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */ + +/* CAN_OPSS2 Masks */ +#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */ +#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */ +#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */ +#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */ +#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */ +#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */ +#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */ +#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */ +#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */ +#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */ +#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */ +#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */ +#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */ +#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */ +#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */ +#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */ + +/* CAN_TRR1 Masks */ +#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */ +#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */ +#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */ +#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */ +#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */ +#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */ +#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */ +#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */ +#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */ +#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */ +#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */ +#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */ +#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */ +#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */ +#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */ +#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */ + +/* CAN_TRR2 Masks */ +#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */ +#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */ +#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */ +#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */ +#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */ +#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */ +#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */ +#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */ +#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */ +#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */ +#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */ +#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */ +#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */ +#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */ +#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */ +#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */ + +/* CAN_TRS1 Masks */ +#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */ +#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */ +#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */ +#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */ +#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */ +#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */ +#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */ +#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */ +#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */ +#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */ +#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */ +#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */ +#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */ +#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */ +#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */ +#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */ + +/* CAN_TRS2 Masks */ +#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */ +#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */ +#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */ +#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */ +#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */ +#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */ +#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */ +#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */ +#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */ +#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */ +#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */ +#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */ +#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */ +#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */ +#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */ +#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */ + +/* CAN_AA1 Masks */ +#define AA0 0x0001 /* Aborted Message In Mailbox 0 */ +#define AA1 0x0002 /* Aborted Message In Mailbox 1 */ +#define AA2 0x0004 /* Aborted Message In Mailbox 2 */ +#define AA3 0x0008 /* Aborted Message In Mailbox 3 */ +#define AA4 0x0010 /* Aborted Message In Mailbox 4 */ +#define AA5 0x0020 /* Aborted Message In Mailbox 5 */ +#define AA6 0x0040 /* Aborted Message In Mailbox 6 */ +#define AA7 0x0080 /* Aborted Message In Mailbox 7 */ +#define AA8 0x0100 /* Aborted Message In Mailbox 8 */ +#define AA9 0x0200 /* Aborted Message In Mailbox 9 */ +#define AA10 0x0400 /* Aborted Message In Mailbox 10 */ +#define AA11 0x0800 /* Aborted Message In Mailbox 11 */ +#define AA12 0x1000 /* Aborted Message In Mailbox 12 */ +#define AA13 0x2000 /* Aborted Message In Mailbox 13 */ +#define AA14 0x4000 /* Aborted Message In Mailbox 14 */ +#define AA15 0x8000 /* Aborted Message In Mailbox 15 */ + +/* CAN_AA2 Masks */ +#define AA16 0x0001 /* Aborted Message In Mailbox 16 */ +#define AA17 0x0002 /* Aborted Message In Mailbox 17 */ +#define AA18 0x0004 /* Aborted Message In Mailbox 18 */ +#define AA19 0x0008 /* Aborted Message In Mailbox 19 */ +#define AA20 0x0010 /* Aborted Message In Mailbox 20 */ +#define AA21 0x0020 /* Aborted Message In Mailbox 21 */ +#define AA22 0x0040 /* Aborted Message In Mailbox 22 */ +#define AA23 0x0080 /* Aborted Message In Mailbox 23 */ +#define AA24 0x0100 /* Aborted Message In Mailbox 24 */ +#define AA25 0x0200 /* Aborted Message In Mailbox 25 */ +#define AA26 0x0400 /* Aborted Message In Mailbox 26 */ +#define AA27 0x0800 /* Aborted Message In Mailbox 27 */ +#define AA28 0x1000 /* Aborted Message In Mailbox 28 */ +#define AA29 0x2000 /* Aborted Message In Mailbox 29 */ +#define AA30 0x4000 /* Aborted Message In Mailbox 30 */ +#define AA31 0x8000 /* Aborted Message In Mailbox 31 */ + +/* CAN_TA1 Masks */ +#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */ +#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */ +#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */ +#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */ +#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */ +#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */ +#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */ +#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */ +#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */ +#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */ +#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */ +#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */ +#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */ +#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */ +#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */ +#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */ + +/* CAN_TA2 Masks */ +#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */ +#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */ +#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */ +#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */ +#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */ +#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */ +#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */ +#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */ +#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */ +#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */ +#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */ +#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */ +#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */ +#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */ +#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */ +#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */ + +/* CAN_MBTD Masks */ +#define TDPTR 0x001F /* Mailbox To Temporarily Disable */ +#define TDA 0x0040 /* Temporary Disable Acknowledge */ +#define TDR 0x0080 /* Temporary Disable Request */ + +/* CAN_RFH1 Masks */ +#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */ +#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */ +#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */ +#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */ +#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */ +#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */ +#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */ +#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */ +#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */ +#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */ +#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */ +#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */ +#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */ +#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */ +#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */ +#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */ + +/* CAN_RFH2 Masks */ +#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */ +#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */ +#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */ +#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */ +#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */ +#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */ +#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */ +#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */ +#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */ +#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */ +#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */ +#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */ +#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */ +#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */ +#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */ +#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */ + +/* CAN_MBTIF1 Masks */ +#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */ +#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */ +#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */ +#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */ +#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */ +#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */ +#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */ +#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */ +#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */ +#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */ +#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */ +#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */ +#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */ +#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */ +#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */ +#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */ + +/* CAN_MBTIF2 Masks */ +#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */ +#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */ +#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */ +#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */ +#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */ +#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */ +#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */ +#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */ +#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */ +#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */ +#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */ +#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */ +#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */ +#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */ +#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */ +#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */ + +/* CAN_MBRIF1 Masks */ +#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */ +#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */ +#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */ +#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */ +#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */ +#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */ +#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */ +#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */ +#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */ +#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */ +#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */ +#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */ +#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */ +#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */ +#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */ +#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */ + +/* CAN_MBRIF2 Masks */ +#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */ +#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */ +#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */ +#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */ +#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */ +#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */ +#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */ +#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */ +#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */ +#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */ +#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */ +#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */ +#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */ +#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */ +#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */ +#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */ + +/* CAN_MBIM1 Masks */ +#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */ +#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */ +#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */ +#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */ +#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */ +#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */ +#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */ +#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */ +#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */ +#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */ +#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */ +#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */ +#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */ +#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */ +#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */ +#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */ + +/* CAN_MBIM2 Masks */ +#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */ +#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */ +#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */ +#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */ +#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */ +#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */ +#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */ +#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */ +#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */ +#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */ +#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */ +#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */ +#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */ +#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */ +#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */ +#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */ + +/* CAN_GIM Masks */ +#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */ +#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */ +#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */ +#define BOIM 0x0008 /* Enable Bus Off Interrupt */ +#define WUIM 0x0010 /* Enable Wake-Up Interrupt */ +#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */ +#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */ +#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */ +#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */ +#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */ +#define ADIM 0x0400 /* Enable Access Denied Interrupt */ + +/* CAN_GIS Masks */ +#define EWTIS 0x0001 /* TX Error Count IRQ Status */ +#define EWRIS 0x0002 /* RX Error Count IRQ Status */ +#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */ +#define BOIS 0x0008 /* Bus Off IRQ Status */ +#define WUIS 0x0010 /* Wake-Up IRQ Status */ +#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */ +#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */ +#define RMLIS 0x0080 /* RX Message Lost IRQ Status */ +#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */ +#define EXTIS 0x0200 /* External Trigger Output IRQ Status */ +#define ADIS 0x0400 /* Access Denied IRQ Status */ + +/* CAN_GIF Masks */ +#define EWTIF 0x0001 /* TX Error Count IRQ Flag */ +#define EWRIF 0x0002 /* RX Error Count IRQ Flag */ +#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */ +#define BOIF 0x0008 /* Bus Off IRQ Flag */ +#define WUIF 0x0010 /* Wake-Up IRQ Flag */ +#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */ +#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */ +#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */ +#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */ +#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */ +#define ADIF 0x0400 /* Access Denied IRQ Flag */ + +/* CAN_UCCNF Masks */ +#define UCCNF 0x000F /* Universal Counter Mode */ +#define UC_STAMP 0x0001 /* Timestamp Mode */ +#define UC_WDOG 0x0002 /* Watchdog Mode */ +#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */ +#define UC_ERROR 0x0006 /* CAN Error Frame Count */ +#define UC_OVER 0x0007 /* CAN Overload Frame Count */ +#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */ +#define UC_AA 0x0009 /* TX Abort Count */ +#define UC_TA 0x000A /* TX Successful Count */ +#define UC_REJECT 0x000B /* RX Message Rejected Count */ +#define UC_RML 0x000C /* RX Message Lost Count */ +#define UC_RX 0x000D /* Total Successful RX Messages Count */ +#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */ +#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */ +#define UCRC 0x0020 /* Universal Counter Reload/Clear */ +#define UCCT 0x0040 /* Universal Counter CAN Trigger */ +#define UCE 0x0080 /* Universal Counter Enable */ + +/* CAN_ESR Masks */ +#define ACKE 0x0004 /* Acknowledge Error */ +#define SER 0x0008 /* Stuff Error */ +#define CRCE 0x0010 /* CRC Error */ +#define SA0 0x0020 /* Stuck At Dominant Error */ +#define BEF 0x0040 /* Bit Error Flag */ +#define FER 0x0080 /* Form Error Flag */ + +/* CAN_EWR Masks */ +#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */ +#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */ + +#endif diff --git a/kernel/arch/blackfin/include/asm/bfin_dma.h b/kernel/arch/blackfin/include/asm/bfin_dma.h new file mode 100644 index 000000000..6319f4e49 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin_dma.h @@ -0,0 +1,165 @@ +/* + * bfin_dma.h - Blackfin DMA defines/structures/etc... + * + * Copyright 2004-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BFIN_DMA_H__ +#define __ASM_BFIN_DMA_H__ + +#include <linux/types.h> + +/* DMA_CONFIG Masks */ +#define DMAEN 0x0001 /* DMA Channel Enable */ +#define WNR 0x0002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ +#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */ + +#ifdef CONFIG_BF60x + +#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */ +#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */ +#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */ +#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */ +#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */ +#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */ +#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */ +#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */ +#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */ +#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */ +#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */ +#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */ +#define DI_EN DI_EN_X /* Data Interrupt Enable */ +#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */ +#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */ +#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */ +#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */ +#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */ +#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */ +#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */ +#define NDSIZE 0x00070000 /* Next Descriptor Size */ +#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */ +#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */ +#define DMAFLOW_LARGE DMAFLOW_LIST +#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */ +#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */ +#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */ +#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */ +#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */ +#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */ +#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */ + +#else + +#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */ +#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */ +#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ +#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ +#define RESTART 0x0020 /* DMA Buffer Clear */ +#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ +#define DI_EN 0x0080 /* Data Interrupt Enable */ +#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/ +#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x0f00 /* Next Descriptor Size */ +#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ +#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + +#endif +#define DMAFLOW 0x7000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ + +/* DMA_IRQ_STATUS Masks */ +#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ +#ifdef CONFIG_BF60x +#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */ +#else +#define DMA_PIRQ 0 +#endif + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m + +/* + * bfin dma registers layout + */ +struct bfin_dma_regs { + u32 next_desc_ptr; + u32 start_addr; +#ifdef CONFIG_BF60x + u32 cfg; + u32 x_count; + u32 x_modify; + u32 y_count; + u32 y_modify; + u32 pad1; + u32 pad2; + u32 curr_desc_ptr; + u32 prev_desc_ptr; + u32 curr_addr; + u32 irq_status; + u32 curr_x_count; + u32 curr_y_count; + u32 pad3; + u32 bw_limit_count; + u32 curr_bw_limit_count; + u32 bw_monitor_count; + u32 curr_bw_monitor_count; +#else + __BFP(config); + u32 __pad0; + __BFP(x_count); + __BFP(x_modify); + __BFP(y_count); + __BFP(y_modify); + u32 curr_desc_ptr; + u32 curr_addr; + __BFP(irq_status); + __BFP(peripheral_map); + __BFP(curr_x_count); + u32 __pad1; + __BFP(curr_y_count); + u32 __pad2; +#endif +}; + +#ifndef CONFIG_BF60x +/* + * bfin handshake mdma registers layout + */ +struct bfin_hmdma_regs { + __BFP(control); + __BFP(ecinit); + __BFP(bcinit); + __BFP(ecurgent); + __BFP(ecoverflow); + __BFP(ecount); + __BFP(bcount); +}; +#endif + +#undef __BFP + +#endif diff --git a/kernel/arch/blackfin/include/asm/bfin_pfmon.h b/kernel/arch/blackfin/include/asm/bfin_pfmon.h new file mode 100644 index 000000000..bf52e1f32 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin_pfmon.h @@ -0,0 +1,44 @@ +/* + * Blackfin Performance Monitor definitions + * + * Copyright 2005-2011 Analog Devices Inc. + * + * Licensed under the Clear BSD license or GPL-2 (or later). + */ + +#ifndef __ASM_BFIN_PFMON_H__ +#define __ASM_BFIN_PFMON_H__ + +/* PFCTL Masks */ +#define PFMON_MASK 0xff +#define PFCEN_MASK 0x3 +#define PFCEN_DISABLE 0x0 +#define PFCEN_ENABLE_USER 0x1 +#define PFCEN_ENABLE_SUPV 0x2 +#define PFCEN_ENABLE_ALL (PFCEN_ENABLE_USER | PFCEN_ENABLE_SUPV) + +#define PFPWR_P 0 +#define PEMUSW0_P 2 +#define PFCEN0_P 3 +#define PFMON0_P 5 +#define PEMUSW1_P 13 +#define PFCEN1_P 14 +#define PFMON1_P 16 +#define PFCNT0_P 24 +#define PFCNT1_P 25 + +#define PFPWR (1 << PFPWR_P) +#define PEMUSW(n, x) ((x) << ((n) ? PEMUSW1_P : PEMUSW0_P)) +#define PEMUSW0 PEMUSW(0, 1) +#define PEMUSW1 PEMUSW(1, 1) +#define PFCEN(n, x) ((x) << ((n) ? PFCEN1_P : PFCEN0_P)) +#define PFCEN0 PFCEN(0, PFCEN_MASK) +#define PFCEN1 PFCEN(1, PFCEN_MASK) +#define PFCNT(n, x) ((x) << ((n) ? PFCNT1_P : PFCNT0_P)) +#define PFCNT0 PFCNT(0, 1) +#define PFCNT1 PFCNT(1, 1) +#define PFMON(n, x) ((x) << ((n) ? PFMON1_P : PFMON0_P)) +#define PFMON0 PFMON(0, PFMON_MASK) +#define PFMON1 PFMON(1, PFMON_MASK) + +#endif diff --git a/kernel/arch/blackfin/include/asm/bfin_ppi.h b/kernel/arch/blackfin/include/asm/bfin_ppi.h new file mode 100644 index 000000000..a4e872e16 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin_ppi.h @@ -0,0 +1,181 @@ +/* + * bfin_ppi.h - interface to Blackfin PPIs + * + * Copyright 2005-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BFIN_PPI_H__ +#define __ASM_BFIN_PPI_H__ + +#include <linux/types.h> +#include <asm/blackfin.h> + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m + +/* + * bfin ppi registers layout + */ +struct bfin_ppi_regs { + __BFP(control); + __BFP(status); + __BFP(count); + __BFP(delay); + __BFP(frame); +}; + +/* + * bfin eppi registers layout + */ +struct bfin_eppi_regs { + __BFP(status); + __BFP(hcount); + __BFP(hdelay); + __BFP(vcount); + __BFP(vdelay); + __BFP(frame); + __BFP(line); + __BFP(clkdiv); + u32 control; + u32 fs1w_hbl; + u32 fs1p_avpl; + u32 fs2w_lvb; + u32 fs2p_lavf; + u32 clip; +}; + +/* + * bfin eppi3 registers layout + */ +struct bfin_eppi3_regs { + u32 stat; + u32 hcnt; + u32 hdly; + u32 vcnt; + u32 vdly; + u32 frame; + u32 line; + u32 clkdiv; + u32 ctl; + u32 fs1_wlhb; + u32 fs1_paspl; + u32 fs2_wlvb; + u32 fs2_palpf; + u32 imsk; + u32 oddclip; + u32 evenclip; + u32 fs1_dly; + u32 fs2_dly; + u32 ctl2; +}; + +#undef __BFP + +#ifdef EPPI0_CTL2 +#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */ +#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */ +#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */ +#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */ +#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */ +#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */ +#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */ +#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */ +#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */ +#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */ + +#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */ + +#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */ + +#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */ + +#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */ + +#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */ + +#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */ + +#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */ + +#define EPPI_CTL_EN 0x00000001 /* PPI Enable */ +#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */ +#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */ +#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */ +#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */ +#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */ +#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */ +#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */ +#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */ +#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */ +#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */ +#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */ +#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */ +#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */ +#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */ +#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */ +#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */ +#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */ +#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */ +#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */ +#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */ +#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */ +#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */ +#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */ +#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */ +#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */ +#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */ +#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */ +#define EPPI_CTL_DLEN 0x00070000 /* Data Length */ +#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */ +#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */ +#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */ +#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */ +#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */ +#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */ +#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */ +#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */ +#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */ +#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */ +#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */ +#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */ +#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */ +#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */ +#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */ +#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */ +#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */ +#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */ +#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */ +#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */ +#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */ + +#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */ +#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */ +#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */ +#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */ + +#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */ +#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */ + +#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */ +#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */ +#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */ +#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */ +#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */ +#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */ +#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */ +#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */ + +#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000 +#define EPPI_ODDCLIP_LOWODD 0x0000FFFF + +#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000 +#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF + +#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */ +#endif +#endif diff --git a/kernel/arch/blackfin/include/asm/bfin_sdh.h b/kernel/arch/blackfin/include/asm/bfin_sdh.h new file mode 100644 index 000000000..a99957ea9 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin_sdh.h @@ -0,0 +1,161 @@ +/* + * Blackfin Secure Digital Host (SDH) definitions + * + * Copyright 2008-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_SDH_H__ +#define __BFIN_SDH_H__ + +/* Platform resources */ +struct bfin_sd_host { + int dma_chan; + int irq_int0; + int irq_int1; + u16 pin_req[7]; +}; + +/* SDH_COMMAND bitmasks */ +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP (1 << 6) /* Response */ +#define CMD_L_RSP (1 << 7) /* Long Response */ +#define CMD_INT_E (1 << 8) /* Command Interrupt */ +#define CMD_PEND_E (1 << 9) /* Command Pending */ +#define CMD_E (1 << 10) /* Command Enable */ +#ifdef RSI_BLKSZ +#define CMD_CRC_CHECK_D (1 << 11) /* CRC Check is disabled */ +#define CMD_DATA0_BUSY (1 << 12) /* Check for Busy State on the DATA0 pin */ +#endif + +/* SDH_PWR_CTL bitmasks */ +#ifndef RSI_BLKSZ +#define PWR_ON 0x3 /* Power On */ +#define SD_CMD_OD (1 << 6) /* Open Drain Output */ +#define ROD_CTL (1 << 7) /* Rod Control */ +#endif + +/* SDH_CLK_CTL bitmasks */ +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E (1 << 9) /* Power Save Enable */ +#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */ +#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */ +#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */ +#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */ +#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */ + +/* SDH_RESP_CMD bitmasks */ +#define RESP_CMD 0x3f /* Response Command */ + +/* SDH_DATA_CTL bitmasks */ +#define DTX_E (1 << 0) /* Data Transfer Enable */ +#define DTX_DIR (1 << 1) /* Data Transfer Direction */ +#define DTX_MODE (1 << 2) /* Data Transfer Mode */ +#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */ +#ifndef RSI_BLKSZ +#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */ +#else + +/* Bit masks for SDH_BLK_SIZE */ +#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */ +#endif + +/* SDH_STATUS bitmasks */ +#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */ +#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */ +#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */ +#define DAT_TIME_OUT (1 << 3) /* Data Time Out */ +#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */ +#define RX_OVERRUN (1 << 5) /* Receive Overrun */ +#define CMD_RESP_END (1 << 6) /* CMD Response End */ +#define CMD_SENT (1 << 7) /* CMD Sent */ +#define DAT_END (1 << 8) /* Data End */ +#define START_BIT_ERR (1 << 9) /* Start Bit Error */ +#define DAT_BLK_END (1 << 10) /* Data Block End */ +#define CMD_ACT (1 << 11) /* CMD Active */ +#define TX_ACT (1 << 12) /* Transmit Active */ +#define RX_ACT (1 << 13) /* Receive Active */ +#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */ +#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */ +#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */ +#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */ +#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */ +#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */ +#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */ +#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */ + +/* SDH_STATUS_CLR bitmasks */ +#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */ +#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */ +#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */ +#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */ +#define DAT_END_STAT (1 << 8) /* Data End Status */ +#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */ +#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */ + +/* SDH_MASK0 bitmasks */ +#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */ +#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */ +#define DAT_END_MASK (1 << 8) /* Data End Mask */ +#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */ +#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */ +#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */ +#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */ + +/* SDH_FIFO_CNT bitmasks */ +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* SDH_E_STATUS bitmasks */ +#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */ +#define SD_CARD_DET (1 << 4) /* SD Card Detect */ +#define SD_CARD_BUSYMODE (1 << 31) /* Card is in Busy mode */ +#define SD_CARD_SLPMODE (1 << 30) /* Card in Sleep Mode */ +#define SD_CARD_READY (1 << 17) /* Card Ready */ + +/* SDH_E_MASK bitmasks */ +#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */ +#define SCD_MSK (1 << 4) /* Mask Card Detect */ +#define CARD_READY_MSK (1 << 16) /* Mask Card Ready */ + +/* SDH_CFG bitmasks */ +#define CLKS_EN (1 << 0) /* Clocks Enable */ +#define SD4E (1 << 2) /* SDIO 4-Bit Enable */ +#define MWE (1 << 3) /* Moving Window Enable */ +#define SD_RST (1 << 4) /* SDMMC Reset */ +#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */ +#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */ +#ifndef RSI_BLKSZ +#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */ +#else +#define PWR_ON 0x600 /* Power On */ +#define SD_CMD_OD (1 << 11) /* Open Drain Output */ +#define BOOT_EN (1 << 12) /* Boot Enable */ +#define BOOT_MODE (1 << 13) /* Alternate Boot Mode */ +#define BOOT_ACK_EN (1 << 14) /* Boot ACK is expected */ +#endif + +/* SDH_RD_WAIT_EN bitmasks */ +#define RWR (1 << 0) /* Read Wait Request */ + +#endif diff --git a/kernel/arch/blackfin/include/asm/bfin_serial.h b/kernel/arch/blackfin/include/asm/bfin_serial.h new file mode 100644 index 000000000..d00d73278 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin_serial.h @@ -0,0 +1,429 @@ +/* + * bfin_serial.h - Blackfin UART/Serial definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_ASM_SERIAL_H__ +#define __BFIN_ASM_SERIAL_H__ + +#include <linux/circ_buf.h> +#include <linux/serial_core.h> +#include <linux/spinlock.h> +#include <linux/timer.h> +#include <linux/workqueue.h> +#include <mach/anomaly.h> +#include <mach/bfin_serial.h> + +#if defined(CONFIG_BFIN_UART0_CTSRTS) || \ + defined(CONFIG_BFIN_UART1_CTSRTS) || \ + defined(CONFIG_BFIN_UART2_CTSRTS) || \ + defined(CONFIG_BFIN_UART3_CTSRTS) +# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE) +# define CONFIG_SERIAL_BFIN_HARD_CTSRTS +# else +# define CONFIG_SERIAL_BFIN_CTSRTS +# endif +#endif + +struct bfin_serial_port { + struct uart_port port; + unsigned int old_status; + int tx_irq; + int rx_irq; + int status_irq; +#ifndef BFIN_UART_BF54X_STYLE + unsigned int lsr; +#endif +#ifdef CONFIG_SERIAL_BFIN_DMA + int tx_done; + int tx_count; + struct circ_buf rx_dma_buf; + struct timer_list rx_dma_timer; + int rx_dma_nrows; + spinlock_t rx_lock; + unsigned int tx_dma_channel; + unsigned int rx_dma_channel; + struct work_struct tx_dma_workqueue; +#elif ANOMALY_05000363 + unsigned int anomaly_threshold; +#endif +#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ + defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) + int cts_pin; + int rts_pin; +#endif +}; + +#ifdef BFIN_UART_BF60X_STYLE + +/* UART_CTL Masks */ +#define UCEN 0x1 /* Enable UARTx Clocks */ +#define LOOP_ENA 0x2 /* Loopback Mode Enable */ +#define UMOD_MDB 0x10 /* Enable MDB Mode */ +#define UMOD_IRDA 0x20 /* Enable IrDA Mode */ +#define UMOD_MASK 0x30 /* Uart Mode Mask */ +#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */ +#define WLS_MASK 0x300 /* Word length Select Mask */ +#define WLS_OFFSET 8 /* Word length Select Offset */ +#define STB 0x1000 /* Stop Bits */ +#define STBH 0x2000 /* Half Stop Bits */ +#define PEN 0x4000 /* Parity Enable */ +#define EPS 0x8000 /* Even Parity Select */ +#define STP 0x10000 /* Stick Parity */ +#define FPE 0x20000 /* Force Parity Error On Transmit */ +#define FFE 0x40000 /* Force Framing Error On Transmit */ +#define SB 0x80000 /* Set Break */ +#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK) +#define FCPOL 0x400000 /* Flow Control Pin Polarity */ +#define RPOLC 0x800000 /* IrDA RX Polarity Change */ +#define TPOLC 0x1000000 /* IrDA TX Polarity Change */ +#define MRTS 0x2000000 /* Manual Request To Send */ +#define XOFF 0x4000000 /* Transmitter Off */ +#define ARTS 0x8000000 /* Automatic Request To Send */ +#define ACTS 0x10000000 /* Automatic Clear To Send */ +#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */ +#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */ + +/* UART_STAT Masks */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* THR Empty */ +#define TEMT 0x80 /* TSR and UART_THR Empty */ +#define TFI 0x100 /* Transmission Finished Indicator */ + +#define ASTKY 0x200 /* Address Sticky */ +#define ADDR 0x400 /* Address bit status */ +#define RO 0x800 /* Reception Ongoing */ +#define SCTS 0x1000 /* Sticky CTS */ +#define CTS 0x10000 /* Clear To Send */ +#define RFCS 0x20000 /* Receive FIFO Count Status */ + +/* UART_CLOCK Masks */ +#define EDBO 0x80000000 /* Enable Devide by One */ + +#else /* BFIN_UART_BF60X_STYLE */ + +/* UART_LCR Masks */ +#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ +#define WLS_MASK 0x03 /* Word length Select Mask */ +#define WLS_OFFSET 0 /* Word length Select Offset */ +#define STB 0x04 /* Stop Bits */ +#define PEN 0x08 /* Parity Enable */ +#define EPS 0x10 /* Even Parity Select */ +#define STP 0x20 /* Stick Parity */ +#define SB 0x40 /* Set Break */ +#define DLAB 0x80 /* Divisor Latch Access */ +#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK) + +/* UART_LSR Masks */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* THR Empty */ +#define TEMT 0x40 /* TSR and UART_THR Empty */ +#define TFI 0x80 /* Transmission Finished Indicator */ + +/* UART_MCR Masks */ +#define XOFF 0x01 /* Transmitter Off */ +#define MRTS 0x02 /* Manual Request To Send */ +#define RFIT 0x04 /* Receive FIFO IRQ Threshold */ +#define RFRT 0x08 /* Receive FIFO RTS Threshold */ +#define LOOP_ENA 0x10 /* Loopback Mode Enable */ +#define FCPOL 0x20 /* Flow Control Pin Polarity */ +#define ARTS 0x40 /* Automatic Request To Send */ +#define ACTS 0x80 /* Automatic Clear To Send */ + +/* UART_MSR Masks */ +#define SCTS 0x01 /* Sticky CTS */ +#define CTS 0x10 /* Clear To Send */ +#define RFCS 0x20 /* Receive FIFO Count Status */ + +/* UART_GCTL Masks */ +#define UCEN 0x01 /* Enable UARTx Clocks */ +#define UMOD_IRDA 0x02 /* Enable IrDA Mode */ +#define UMOD_MASK 0x02 /* Uart Mode Mask */ +#define TPOLC 0x04 /* IrDA TX Polarity Change */ +#define RPOLC 0x08 /* IrDA RX Polarity Change */ +#define FPE 0x10 /* Force Parity Error On Transmit */ +#define FFE 0x20 /* Force Framing Error On Transmit */ + +#endif /* BFIN_UART_BF60X_STYLE */ + +/* UART_IER Masks */ +#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ +#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ +#define ELSI 0x04 /* Enable RX Status Interrupt */ +#define EDSSI 0x08 /* Enable Modem Status Interrupt */ +#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */ +#define ETFI 0x20 /* Enable Transmission Finished Interrupt */ +#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ + +#if defined(BFIN_UART_BF60X_STYLE) +# define OFFSET_REDIV 0x00 /* Version ID Register */ +# define OFFSET_CTL 0x04 /* Control Register */ +# define OFFSET_STAT 0x08 /* Status Register */ +# define OFFSET_SCR 0x0C /* SCR Scratch Register */ +# define OFFSET_CLK 0x10 /* Clock Rate Register */ +# define OFFSET_IER 0x14 /* Interrupt Enable Register */ +# define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */ +# define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */ +# define OFFSET_RBR 0x20 /* Receive Buffer register */ +# define OFFSET_THR 0x24 /* Transmit Holding register */ +#elif defined(BFIN_UART_BF54X_STYLE) +# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +# define OFFSET_GCTL 0x08 /* Global Control Register */ +# define OFFSET_LCR 0x0C /* Line Control Register */ +# define OFFSET_MCR 0x10 /* Modem Control Register */ +# define OFFSET_LSR 0x14 /* Line Status Register */ +# define OFFSET_MSR 0x18 /* Modem Status Register */ +# define OFFSET_SCR 0x1C /* SCR Scratch Register */ +# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */ +# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */ +# define OFFSET_THR 0x28 /* Transmit Holding register */ +# define OFFSET_RBR 0x2C /* Receive Buffer register */ +#else /* BF533 style */ +# define OFFSET_THR 0x00 /* Transmit Holding register */ +# define OFFSET_RBR 0x00 /* Receive Buffer register */ +# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ +# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ +# define OFFSET_IER 0x04 /* Interrupt Enable Register */ +# define OFFSET_IIR 0x08 /* Interrupt Identification Register */ +# define OFFSET_LCR 0x0C /* Line Control Register */ +# define OFFSET_MCR 0x10 /* Modem Control Register */ +# define OFFSET_LSR 0x14 /* Line Status Register */ +# define OFFSET_MSR 0x18 /* Modem Status Register */ +# define OFFSET_SCR 0x1C /* SCR Scratch Register */ +# define OFFSET_GCTL 0x24 /* Global Control Register */ +/* code should not need IIR, so force build error if they use it */ +# undef OFFSET_IIR +#endif + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m +struct bfin_uart_regs { +#if defined(BFIN_UART_BF60X_STYLE) + u32 revid; + u32 ctl; + u32 stat; + u32 scr; + u32 clk; + u32 ier; + u32 ier_set; + u32 ier_clear; + u32 rbr; + u32 thr; + u32 taip; + u32 tsr; + u32 rsr; + u32 txdiv; + u32 rxdiv; +#elif defined(BFIN_UART_BF54X_STYLE) + __BFP(dll); + __BFP(dlh); + __BFP(gctl); + __BFP(lcr); + __BFP(mcr); + __BFP(lsr); + __BFP(msr); + __BFP(scr); + __BFP(ier_set); + __BFP(ier_clear); + __BFP(thr); + __BFP(rbr); +#else + union { + u16 dll; + u16 thr; + const u16 rbr; + }; + const u16 __pad0; + union { + u16 dlh; + u16 ier; + }; + const u16 __pad1; + const __BFP(iir); + __BFP(lcr); + __BFP(mcr); + __BFP(lsr); + __BFP(msr); + __BFP(scr); + const u32 __pad2; + __BFP(gctl); +#endif +}; +#undef __BFP + +#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase) + +/* +#ifndef port_membase +# define port_membase(p) 0 +#endif +*/ +#ifdef BFIN_UART_BF60X_STYLE + +#define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR) +#define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK) +#define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL) +#define UART_GET_GCTL(p) UART_GET_CTL(p) +#define UART_GET_LCR(p) UART_GET_CTL(p) +#define UART_GET_MCR(p) UART_GET_CTL(p) +#if ANOMALY_16000030 +#define UART_GET_STAT(p) \ +({ \ + u32 __ret; \ + unsigned long flags; \ + flags = hard_local_irq_save(); \ + __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \ + hard_local_irq_restore(flags); \ + __ret; \ +}) +#else +#define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT) +#endif +#define UART_GET_MSR(p) UART_GET_STAT(p) + +#define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v) +#define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v) +#define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v) +#define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v) +#define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v) +#define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v) +#define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v) + +#define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v) +#define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER) +#define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v) + +#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */ +#define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */ + +#define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1) +#define UART_GET_LSR(p) UART_GET_STAT(p) +#define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v) + +/* This handles hard CTS/RTS */ +#define BFIN_UART_CTSRTS_HARD +#define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS) +#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) +#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS)) +#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS) +#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) +#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) + +#else /* BFIN_UART_BF60X_STYLE */ + +#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR) +#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL) +#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH) +#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p)) +#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL) +#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR) +#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR) +#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR) + +#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v) +#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v) +#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v) +#define UART_PUT_CLK(p, v) do \ +{\ +UART_PUT_DLL(p, v & 0xFF); \ +UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0); + +#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v) +#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v) +#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v) + +#ifdef BFIN_UART_BF54X_STYLE + +#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v) +#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET) +#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v) + +#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */ +#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */ + +#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1) +#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR) +#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v) + +/* This handles hard CTS/RTS */ +#define BFIN_UART_CTSRTS_HARD +#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS) +#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS) +#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS)) +#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS) +#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) +#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) + +#else /* BF533 style */ + +#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v)) +#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER) +#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v) +#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v)) + +#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0) +#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0) + +#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr) +#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v)) + +/* +#ifndef put_lsr_cache +# define put_lsr_cache(p, v) +#endif +#ifndef get_lsr_cache +# define get_lsr_cache(p) 0 +#endif +*/ + +/* The hardware clears the LSR bits upon read, so we need to cache + * some of the more fun bits in software so they don't get lost + * when checking the LSR in other code paths (TX). + */ +static inline void UART_CLEAR_LSR(void *p) +{ + put_lsr_cache(p, 0); + bfin_write16(port_membase(p) + OFFSET_LSR, -1); +} +static inline unsigned int UART_GET_LSR(void *p) +{ + unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR); + put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE))); + return lsr | get_lsr_cache(p); +} +static inline void UART_PUT_LSR(void *p, uint16_t val) +{ + put_lsr_cache(p, get_lsr_cache(p) & ~val); +} + +/* This handles soft CTS/RTS */ +#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin) +#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1) +#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0) +#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) +#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) + +#endif /* BFIN_UART_BF54X_STYLE */ + +#endif /* BFIN_UART_BF60X_STYLE */ + +#ifndef BFIN_UART_TX_FIFO_SIZE +# define BFIN_UART_TX_FIFO_SIZE 2 +#endif + +#endif /* __BFIN_ASM_SERIAL_H__ */ diff --git a/kernel/arch/blackfin/include/asm/bfin_simple_timer.h b/kernel/arch/blackfin/include/asm/bfin_simple_timer.h new file mode 100644 index 000000000..b2d5e7330 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin_simple_timer.h @@ -0,0 +1,27 @@ +/* + * Copyright 2006-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _bfin_simple_timer_h_ +#define _bfin_simple_timer_h_ + +#include <linux/ioctl.h> + +#define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't' + +#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 2) +#define BFIN_SIMPLE_TIMER_SET_WIDTH _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 3) +#define BFIN_SIMPLE_TIMER_SET_MODE _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 4) +#define BFIN_SIMPLE_TIMER_START _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6) +#define BFIN_SIMPLE_TIMER_STOP _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8) +#define BFIN_SIMPLE_TIMER_READ _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10) +#define BFIN_SIMPLE_TIMER_READ_COUNTER _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 11) + +#define BFIN_SIMPLE_TIMER_MODE_PWM_ONESHOT 0 +#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT 1 +#define BFIN_SIMPLE_TIMER_MODE_WDTH_CAP 2 +#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT_NOIRQ 3 + +#endif diff --git a/kernel/arch/blackfin/include/asm/bfin_sport.h b/kernel/arch/blackfin/include/asm/bfin_sport.h new file mode 100644 index 000000000..50b9dfd48 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin_sport.h @@ -0,0 +1,71 @@ +/* + * bfin_sport.h - interface to Blackfin SPORTs + * + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ +#ifndef __BFIN_SPORT_H__ +#define __BFIN_SPORT_H__ + + +#include <linux/types.h> +#include <uapi/asm/bfin_sport.h> + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m +struct sport_register { + __BFP(tcr1); + __BFP(tcr2); + __BFP(tclkdiv); + __BFP(tfsdiv); + union { + u32 tx32; + u16 tx16; + }; + u32 __pad_tx; + union { + u32 rx32; /* use the anomaly wrapper below */ + u16 rx16; + }; + u32 __pad_rx; + __BFP(rcr1); + __BFP(rcr2); + __BFP(rclkdiv); + __BFP(rfsdiv); + __BFP(stat); + __BFP(chnl); + __BFP(mcmc1); + __BFP(mcmc2); + u32 mtcs0; + u32 mtcs1; + u32 mtcs2; + u32 mtcs3; + u32 mrcs0; + u32 mrcs1; + u32 mrcs2; + u32 mrcs3; +}; +#undef __BFP + +struct bfin_snd_platform_data { + const unsigned short *pin_req; +}; + +#define bfin_read_sport_rx32(base) \ +({ \ + struct sport_register *__mmrs = (void *)base; \ + u32 __ret; \ + unsigned long flags; \ + if (ANOMALY_05000473) \ + local_irq_save(flags); \ + __ret = __mmrs->rx32; \ + if (ANOMALY_05000473) \ + local_irq_restore(flags); \ + __ret; \ +}) + +#endif diff --git a/kernel/arch/blackfin/include/asm/bfin_sport3.h b/kernel/arch/blackfin/include/asm/bfin_sport3.h new file mode 100644 index 000000000..d82f5fa0a --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin_sport3.h @@ -0,0 +1,107 @@ +/* + * bfin_sport - Analog Devices BF6XX SPORT registers + * + * Copyright (c) 2012 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _BFIN_SPORT3_H_ +#define _BFIN_SPORT3_H_ + +#include <linux/types.h> + +#define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */ +#define SPORT_CTL_DTYPE 0x00000006 /* Data type select */ +#define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */ +#define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */ +#define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */ +#define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */ +#define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */ +#define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */ +#define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */ +#define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */ +#define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */ +#define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */ +#define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */ +#define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */ +#define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */ +#define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */ +#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */ +#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */ +#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */ +#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrupt enable select */ +#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */ +#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */ +#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */ +#define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */ +#define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */ +#define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */ +#define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */ +#define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */ +#define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */ +#define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */ +#define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */ +#define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */ +#define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */ + +#define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */ +#define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */ + +#define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */ +#define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */ +#define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */ +#define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */ +#define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */ + +#define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */ +#define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */ + +#define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */ +#define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */ +#define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */ +#define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */ +#define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */ +#define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */ + +#define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */ + +#define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */ +#define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */ +#define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */ + +struct sport_register { + u32 spctl; + u32 div; + u32 spmctl; + u32 spcs0; + u32 spcs1; + u32 spcs2; + u32 spcs3; + u32 spcnt; + u32 sperrctl; + u32 spmstat; + u32 spctl2; + u32 txa; + u32 rxa; + u32 txb; + u32 rxb; + u32 revid; +}; + +struct bfin_snd_platform_data { + const unsigned short *pin_req; +}; + +#endif diff --git a/kernel/arch/blackfin/include/asm/bfin_twi.h b/kernel/arch/blackfin/include/asm/bfin_twi.h new file mode 100644 index 000000000..aaa0834d3 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin_twi.h @@ -0,0 +1,82 @@ +/* + * bfin_twi.h - interface to Blackfin TWIs + * + * Copyright 2005-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BFIN_TWI_H__ +#define __ASM_BFIN_TWI_H__ + +#include <asm/blackfin.h> + +#define DEFINE_TWI_REG(reg_name, reg) \ +static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \ + { return bfin_read16(&iface->regs_base->reg); } \ +static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \ + { bfin_write16(&iface->regs_base->reg, v); } + +DEFINE_TWI_REG(CLKDIV, clkdiv) +DEFINE_TWI_REG(SLAVE_CTL, slave_ctl) +DEFINE_TWI_REG(SLAVE_STAT, slave_stat) +DEFINE_TWI_REG(SLAVE_ADDR, slave_addr) +DEFINE_TWI_REG(MASTER_CTL, master_ctl) +DEFINE_TWI_REG(MASTER_STAT, master_stat) +DEFINE_TWI_REG(MASTER_ADDR, master_addr) +DEFINE_TWI_REG(INT_STAT, int_stat) +DEFINE_TWI_REG(INT_MASK, int_mask) +DEFINE_TWI_REG(FIFO_STAT, fifo_stat) +DEFINE_TWI_REG(XMT_DATA8, xmt_data8) +DEFINE_TWI_REG(XMT_DATA16, xmt_data16) +#if !ANOMALY_16000030 +DEFINE_TWI_REG(RCV_DATA8, rcv_data8) +DEFINE_TWI_REG(RCV_DATA16, rcv_data16) +#else +static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface) +{ + u16 ret; + unsigned long flags; + + flags = hard_local_irq_save(); + ret = bfin_read16(&iface->regs_base->rcv_data8); + hard_local_irq_restore(flags); + + return ret; +} + +static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface) +{ + u16 ret; + unsigned long flags; + + flags = hard_local_irq_save(); + ret = bfin_read16(&iface->regs_base->rcv_data16); + hard_local_irq_restore(flags); + + return ret; +} +#endif + +static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface) +{ + return bfin_read16(&iface->regs_base->fifo_ctl); +} + +static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v) +{ + bfin_write16(&iface->regs_base->fifo_ctl, v); + SSYNC(); +} + +static inline u16 read_CONTROL(struct bfin_twi_iface *iface) +{ + return bfin_read16(&iface->regs_base->control); +} + +static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v) +{ + SSYNC(); + bfin_write16(&iface->regs_base->control, v); +} +#endif diff --git a/kernel/arch/blackfin/include/asm/bfin_watchdog.h b/kernel/arch/blackfin/include/asm/bfin_watchdog.h new file mode 100644 index 000000000..dce09829a --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfin_watchdog.h @@ -0,0 +1,30 @@ +/* + * bfin_watchdog.h - Blackfin watchdog definitions + * + * Copyright 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BFIN_WATCHDOG_H +#define _BFIN_WATCHDOG_H + +/* Bit in SWRST that indicates boot caused by watchdog */ +#define SWRST_RESET_WDOG 0x4000 + +/* Bit in WDOG_CTL that indicates watchdog has expired (WDR0) */ +#define WDOG_EXPIRED 0x8000 + +/* Masks for WDEV field in WDOG_CTL register */ +#define ICTL_RESET 0x0 +#define ICTL_NMI 0x2 +#define ICTL_GPI 0x4 +#define ICTL_NONE 0x6 +#define ICTL_MASK 0x6 + +/* Masks for WDEN field in WDOG_CTL register */ +#define WDEN_MASK 0x0FF0 +#define WDEN_ENABLE 0x0000 +#define WDEN_DISABLE 0x0AD0 + +#endif diff --git a/kernel/arch/blackfin/include/asm/bfrom.h b/kernel/arch/blackfin/include/asm/bfrom.h new file mode 100644 index 000000000..9e4be5e5e --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bfrom.h @@ -0,0 +1,90 @@ +/* Blackfin on-chip ROM API + * + * Copyright 2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFROM_H__ +#define __BFROM_H__ + +#include <linux/types.h> + +/* Possible syscontrol action flags */ +#define SYSCTRL_READ 0x00000000 /* read registers */ +#define SYSCTRL_WRITE 0x00000001 /* write registers */ +#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */ +#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */ +#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */ +#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */ +#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */ +#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */ +#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */ +#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */ +#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */ +#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */ +#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */ + +typedef struct ADI_SYSCTRL_VALUES { + uint16_t uwVrCtl; + uint16_t uwPllCtl; + uint16_t uwPllDiv; + uint16_t uwPllLockCnt; + uint16_t uwPllStat; +} ADI_SYSCTRL_VALUES; + +static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038; + +/* We need a dedicated function since we need to screw with the stack pointer + * when resetting. The on-chip ROM will save/restore registers on the stack + * when doing a system reset, so the stack cannot be outside of the chip. + */ +__attribute__((__noreturn__)) +static inline void bfrom_SoftReset(void *new_stack) +{ + while (1) + /* + * We don't declare the SP as clobbered on purpose, since + * it confuses the heck out of the compiler, and this function + * never returns + */ + __asm__ __volatile__( + "sp = %[stack];" + "jump (%[bfrom_syscontrol]);" + : : [bfrom_syscontrol] "p"(bfrom_SysControl), + "q0"(SYSCTRL_SOFTRESET), + "q1"(0), + "q2"(NULL), + [stack] "p"(new_stack) + ); +} + +/* OTP Functions */ +static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018; +static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A; +static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C; + +/* otp command: defines for "command" */ +#define OTP_INIT 0x00000001 +#define OTP_CLOSE 0x00000002 + +/* otp read/write: defines for "flags" */ +#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */ +#define OTP_UPPER_HALF 0x00000001 +#define OTP_NO_ECC 0x00000010 /* do not use ECC */ +#define OTP_LOCK 0x00000020 /* sets page protection bit for page */ +#define OTP_CHECK_FOR_PREV_WRITE 0x00000080 + +/* Return values for all functions */ +#define OTP_SUCCESS 0x00000000 +#define OTP_MASTER_ERROR 0x001 +#define OTP_WRITE_ERROR 0x003 +#define OTP_READ_ERROR 0x005 +#define OTP_ACC_VIO_ERROR 0x009 +#define OTP_DATA_MULT_ERROR 0x011 +#define OTP_ECC_MULT_ERROR 0x021 +#define OTP_PREV_WR_ERROR 0x041 +#define OTP_DATA_SB_WARN 0x100 +#define OTP_ECC_SB_WARN 0x200 + +#endif diff --git a/kernel/arch/blackfin/include/asm/bitops.h b/kernel/arch/blackfin/include/asm/bitops.h new file mode 100644 index 000000000..b298b654a --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bitops.h @@ -0,0 +1,140 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_BITOPS_H +#define _BLACKFIN_BITOPS_H + +#include <linux/compiler.h> + +#include <asm-generic/bitops/__ffs.h> +#include <asm-generic/bitops/ffz.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/find.h> + +#ifndef _LINUX_BITOPS_H +#error only <linux/bitops.h> can be included directly +#endif + +#include <asm-generic/bitops/sched.h> +#include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/const_hweight.h> +#include <asm-generic/bitops/lock.h> + +#include <asm-generic/bitops/ext2-atomic.h> + +#include <asm/barrier.h> + +#ifndef CONFIG_SMP +#include <linux/irqflags.h> +/* + * clear_bit may not imply a memory barrier + */ +#include <asm-generic/bitops/atomic.h> +#include <asm-generic/bitops/non-atomic.h> +#else + +#include <asm/byteorder.h> /* swab32 */ +#include <linux/linkage.h> + +asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr); + +asmlinkage int __raw_bit_clear_asm(volatile unsigned long *addr, int nr); + +asmlinkage int __raw_bit_toggle_asm(volatile unsigned long *addr, int nr); + +asmlinkage int __raw_bit_test_set_asm(volatile unsigned long *addr, int nr); + +asmlinkage int __raw_bit_test_clear_asm(volatile unsigned long *addr, int nr); + +asmlinkage int __raw_bit_test_toggle_asm(volatile unsigned long *addr, int nr); + +asmlinkage int __raw_bit_test_asm(const volatile unsigned long *addr, int nr); + +static inline void set_bit(int nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr + (nr >> 5); + __raw_bit_set_asm(a, nr & 0x1f); +} + +static inline void clear_bit(int nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr + (nr >> 5); + __raw_bit_clear_asm(a, nr & 0x1f); +} + +static inline void change_bit(int nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr + (nr >> 5); + __raw_bit_toggle_asm(a, nr & 0x1f); +} + +static inline int test_bit(int nr, const volatile unsigned long *addr) +{ + volatile const unsigned long *a = addr + (nr >> 5); + return __raw_bit_test_asm(a, nr & 0x1f) != 0; +} + +static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr + (nr >> 5); + return __raw_bit_test_set_asm(a, nr & 0x1f); +} + +static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr + (nr >> 5); + return __raw_bit_test_clear_asm(a, nr & 0x1f); +} + +static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +{ + volatile unsigned long *a = addr + (nr >> 5); + return __raw_bit_test_toggle_asm(a, nr & 0x1f); +} + +#define test_bit __skip_test_bit +#include <asm-generic/bitops/non-atomic.h> +#undef test_bit + +#endif /* CONFIG_SMP */ + +/* Needs to be after test_bit and friends */ +#include <asm-generic/bitops/le.h> + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +static inline unsigned int __arch_hweight32(unsigned int w) +{ + unsigned int res; + + __asm__ ("%0.l = ONES %1;" + "%0 = %0.l (Z);" + : "=d" (res) : "d" (w)); + return res; +} + +static inline unsigned int __arch_hweight64(__u64 w) +{ + return __arch_hweight32((unsigned int)(w >> 32)) + + __arch_hweight32((unsigned int)w); +} + +static inline unsigned int __arch_hweight16(unsigned int w) +{ + return __arch_hweight32(w & 0xffff); +} + +static inline unsigned int __arch_hweight8(unsigned int w) +{ + return __arch_hweight32(w & 0xff); +} + +#endif /* _BLACKFIN_BITOPS_H */ diff --git a/kernel/arch/blackfin/include/asm/blackfin.h b/kernel/arch/blackfin/include/asm/blackfin.h new file mode 100644 index 000000000..f111f366d --- /dev/null +++ b/kernel/arch/blackfin/include/asm/blackfin.h @@ -0,0 +1,88 @@ +/* + * Common header file for Blackfin family of processors. + * + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_H_ +#define _BLACKFIN_H_ + +#include <mach/anomaly.h> + +#ifndef __ASSEMBLY__ + +/* SSYNC implementation for C file */ +static inline void SSYNC(void) +{ + int _tmp; + if (ANOMALY_05000312 || ANOMALY_05000244) + __asm__ __volatile__( + "cli %0;" + "nop;" + "nop;" + "nop;" + "ssync;" + "sti %0;" + : "=d" (_tmp) + ); + else + __asm__ __volatile__("ssync;"); +} + +/* CSYNC implementation for C file */ +static inline void CSYNC(void) +{ + int _tmp; + if (ANOMALY_05000312 || ANOMALY_05000244) + __asm__ __volatile__( + "cli %0;" + "nop;" + "nop;" + "nop;" + "csync;" + "sti %0;" + : "=d" (_tmp) + ); + else + __asm__ __volatile__("csync;"); +} + +#else /* __ASSEMBLY__ */ + +#define LO(con32) ((con32) & 0xFFFF) +#define lo(con32) ((con32) & 0xFFFF) +#define HI(con32) (((con32) >> 16) & 0xFFFF) +#define hi(con32) (((con32) >> 16) & 0xFFFF) + +/* SSYNC & CSYNC implementations for assembly files */ + +#define ssync(x) SSYNC(x) +#define csync(x) CSYNC(x) + +#if ANOMALY_05000312 || ANOMALY_05000244 +#define SSYNC(scratch) \ + cli scratch; \ + nop; nop; nop; \ + SSYNC; \ + sti scratch; + +#define CSYNC(scratch) \ + cli scratch; \ + nop; nop; nop; \ + CSYNC; \ + sti scratch; + +#else +#define SSYNC(scratch) SSYNC; +#define CSYNC(scratch) CSYNC; +#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */ + +#endif /* __ASSEMBLY__ */ + +#include <asm/mem_map.h> +#include <mach/blackfin.h> +#include <asm/bfin-global.h> + +#endif /* _BLACKFIN_H_ */ diff --git a/kernel/arch/blackfin/include/asm/bug.h b/kernel/arch/blackfin/include/asm/bug.h new file mode 100644 index 000000000..8d9b1eba8 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/bug.h @@ -0,0 +1,73 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_BUG_H +#define _BLACKFIN_BUG_H + +#ifdef CONFIG_BUG + +/* + * This can be any undefined 16-bit opcode, meaning + * ((opcode & 0xc000) != 0xc000) + * Anything from 0x0001 to 0x000A (inclusive) will work + */ +#define BFIN_BUG_OPCODE 0x0001 + +#ifdef CONFIG_DEBUG_BUGVERBOSE + +#define _BUG_OR_WARN(flags) \ + asm volatile( \ + "1: .hword %0\n" \ + " .section __bug_table,\"a\",@progbits\n" \ + "2: .long 1b\n" \ + " .long %1\n" \ + " .short %2\n" \ + " .short %3\n" \ + " .org 2b + %4\n" \ + " .previous" \ + : \ + : "i"(BFIN_BUG_OPCODE), "i"(__FILE__), \ + "i"(__LINE__), "i"(flags), \ + "i"(sizeof(struct bug_entry))) + +#else + +#define _BUG_OR_WARN(flags) \ + asm volatile( \ + "1: .hword %0\n" \ + " .section __bug_table,\"a\",@progbits\n" \ + "2: .long 1b\n" \ + " .short %1\n" \ + " .org 2b + %2\n" \ + " .previous" \ + : \ + : "i"(BFIN_BUG_OPCODE), "i"(flags), \ + "i"(sizeof(struct bug_entry))) + +#endif /* CONFIG_DEBUG_BUGVERBOSE */ + +#define BUG() \ + do { \ + _BUG_OR_WARN(0); \ + unreachable(); \ + } while (0) + +#define WARN_ON(condition) \ + ({ \ + int __ret_warn_on = !!(condition); \ + if (unlikely(__ret_warn_on)) \ + _BUG_OR_WARN(BUGFLAG_WARNING); \ + unlikely(__ret_warn_on); \ + }) + +#define HAVE_ARCH_BUG +#define HAVE_ARCH_WARN_ON + +#endif + +#include <asm-generic/bug.h> + +#endif diff --git a/kernel/arch/blackfin/include/asm/cache.h b/kernel/arch/blackfin/include/asm/cache.h new file mode 100644 index 000000000..568885a2c --- /dev/null +++ b/kernel/arch/blackfin/include/asm/cache.h @@ -0,0 +1,70 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ARCH_BLACKFIN_CACHE_H +#define __ARCH_BLACKFIN_CACHE_H + +#include <linux/linkage.h> /* for asmlinkage */ + +/* + * Bytes per L1 cache line + * Blackfin loads 32 bytes for cache + */ +#define L1_CACHE_SHIFT 5 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES + +#ifdef CONFIG_SMP +#define __cacheline_aligned +#else +#define ____cacheline_aligned + +/* + * Put cacheline_aliged data to L1 data memory + */ +#ifdef CONFIG_CACHELINE_ALIGNED_L1 +#define __cacheline_aligned \ + __attribute__((__aligned__(L1_CACHE_BYTES), \ + __section__(".data_l1.cacheline_aligned"))) +#endif + +#endif + +/* + * largest L1 which this arch supports + */ +#define L1_CACHE_SHIFT_MAX 5 + +#if defined(CONFIG_SMP) && \ + !defined(CONFIG_BFIN_CACHE_COHERENT) +# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE) +# define __ARCH_SYNC_CORE_ICACHE +# endif +# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE) +# define __ARCH_SYNC_CORE_DCACHE +# endif +#ifndef __ASSEMBLY__ +asmlinkage void __raw_smp_mark_barrier_asm(void); +asmlinkage void __raw_smp_check_barrier_asm(void); + +static inline void smp_mark_barrier(void) +{ + __raw_smp_mark_barrier_asm(); +} +static inline void smp_check_barrier(void) +{ + __raw_smp_check_barrier_asm(); +} + +void resync_core_dcache(void); +void resync_core_icache(void); +#endif +#endif + + +#endif diff --git a/kernel/arch/blackfin/include/asm/cacheflush.h b/kernel/arch/blackfin/include/asm/cacheflush.h new file mode 100644 index 000000000..9a5b2c572 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/cacheflush.h @@ -0,0 +1,118 @@ +/* + * Blackfin low-level cache routines + * + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_CACHEFLUSH_H +#define _BLACKFIN_CACHEFLUSH_H + +#include <asm/blackfin.h> /* for SSYNC() */ +#include <asm/sections.h> /* for _ramend */ +#ifdef CONFIG_SMP +#include <asm/smp.h> +#endif + +extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); +extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); +extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address); +extern void blackfin_dflush_page(void *page); +extern void blackfin_invalidate_entire_dcache(void); +extern void blackfin_invalidate_entire_icache(void); + +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) do { } while (0) +#define flush_cache_page(vma, vmaddr) do { } while (0) +#define flush_cache_vmap(start, end) do { } while (0) +#define flush_cache_vunmap(start, end) do { } while (0) + +#ifdef CONFIG_SMP +#define flush_icache_range_others(start, end) \ + smp_icache_flush_range_others((start), (end)) +#else +#define flush_icache_range_others(start, end) do { } while (0) +#endif + +static inline void flush_icache_range(unsigned start, unsigned end) +{ +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) + if (end <= physical_mem_end) + blackfin_dcache_flush_range(start, end); +#endif +#if defined(CONFIG_BFIN_L2_WRITEBACK) + if (start >= L2_START && end <= L2_START + L2_LENGTH) + blackfin_dcache_flush_range(start, end); +#endif + + /* Make sure all write buffers in the data side of the core + * are flushed before trying to invalidate the icache. This + * needs to be after the data flush and before the icache + * flush so that the SSYNC does the right thing in preventing + * the instruction prefetcher from hitting things in cached + * memory at the wrong time -- it runs much further ahead than + * the pipeline. + */ + SSYNC(); +#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) + if (end <= physical_mem_end) { + blackfin_icache_flush_range(start, end); + flush_icache_range_others(start, end); + } +#endif +#if defined(CONFIG_BFIN_L2_ICACHEABLE) + if (start >= L2_START && end <= L2_START + L2_LENGTH) { + blackfin_icache_flush_range(start, end); + flush_icache_range_others(start, end); + } +#endif +} + +#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ +do { memcpy(dst, src, len); \ + flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ +} while (0) + +#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) + +#if defined(CONFIG_BFIN_DCACHE) +# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end)) +#else +# define invalidate_dcache_range(start,end) do { } while (0) +#endif +#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) +# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) +#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 +# define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) +#else +# define flush_dcache_range(start,end) do { } while (0) +#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 +# define flush_dcache_page(page) do { } while (0) +#endif + +extern unsigned long reserved_mem_dcache_on; +extern unsigned long reserved_mem_icache_on; + +static inline int bfin_addr_dcacheable(unsigned long addr) +{ +#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE + if (addr < (_ramend - DMA_UNCACHED_REGION)) + return 1; +#endif + + if (reserved_mem_dcache_on && + addr >= _ramend && addr < physical_mem_end) + return 1; + +#ifdef CONFIG_BFIN_L2_DCACHEABLE + if (addr >= L2_START && addr < L2_START + L2_LENGTH) + return 1; +#endif + + return 0; +} + +#endif /* _BLACKFIN_ICACHEFLUSH_H */ diff --git a/kernel/arch/blackfin/include/asm/cdef_LPBlackfin.h b/kernel/arch/blackfin/include/asm/cdef_LPBlackfin.h new file mode 100644 index 000000000..59af63c0c --- /dev/null +++ b/kernel/arch/blackfin/include/asm/cdef_LPBlackfin.h @@ -0,0 +1,309 @@ +/* + * Copyright 2005-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _CDEF_LPBLACKFIN_H +#define _CDEF_LPBLACKFIN_H + +/*#if !defined(__ADSPLPBLACKFIN__) +#warning cdef_LPBlackfin.h should only be included for 532 compatible chips. +#endif +*/ +#include <asm/def_LPBlackfin.h> + +/*Cache & SRAM Memory*/ +#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) +#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) +#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) +#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) +#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) +#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val) +#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) +#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val) +/* +#define MMR_TIMEOUT 0xFFE00010 +*/ +#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0) +#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val) +#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1) +#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val) +#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2) +#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val) +#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3) +#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val) +#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4) +#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val) +#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5) +#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val) +#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6) +#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val) +#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7) +#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val) +#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8) +#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val) +#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9) +#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val) +#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10) +#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val) +#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11) +#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val) +#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12) +#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val) +#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13) +#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val) +#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14) +#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val) +#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15) +#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val) +#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) +#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val) +#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) +#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val) +#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) +#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val) +#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) +#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val) +#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) +#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val) +#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) +#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val) +#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) +#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val) +#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) +#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val) +#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) +#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val) +#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) +#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val) +#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) +#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val) +#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) +#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val) +#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) +#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val) +#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) +#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val) +#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) +#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val) +#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) +#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val) +#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) +#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val) +/* +#define DTEST_INDEX 0xFFE00304 +*/ +#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) +#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val) +#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) +#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val) +/* +#define DTEST_DATA2 0xFFE00408 +#define DTEST_DATA3 0xFFE0040C +*/ +#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) +#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) +#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) +#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val) +#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) +#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR,val) +#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0) +#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val) +#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1) +#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1,val) +#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2) +#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2,val) +#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3) +#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3,val) +#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4) +#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4,val) +#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5) +#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5,val) +#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6) +#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6,val) +#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7) +#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7,val) +#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8) +#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8,val) +#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9) +#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9,val) +#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10) +#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10,val) +#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11) +#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11,val) +#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12) +#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12,val) +#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13) +#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13,val) +#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14) +#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14,val) +#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15) +#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15,val) +#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) +#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0,val) +#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) +#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1,val) +#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) +#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2,val) +#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) +#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3,val) +#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) +#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4,val) +#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) +#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5,val) +#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) +#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6,val) +#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) +#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7,val) +#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) +#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8,val) +#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) +#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9,val) +#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) +#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10,val) +#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) +#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11,val) +#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) +#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12,val) +#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) +#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13,val) +#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) +#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val) +#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) +#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val) +#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val) +#if 0 +#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */ +#endif +#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val) +#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val) + +#if !ANOMALY_05000481 +#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) +#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) +#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) +#endif + +/* Event/Interrupt Registers*/ + +#define bfin_read_EVT0() bfin_read32(EVT0) +#define bfin_write_EVT0(val) bfin_write32(EVT0,val) +#define bfin_read_EVT1() bfin_read32(EVT1) +#define bfin_write_EVT1(val) bfin_write32(EVT1,val) +#define bfin_read_EVT2() bfin_read32(EVT2) +#define bfin_write_EVT2(val) bfin_write32(EVT2,val) +#define bfin_read_EVT3() bfin_read32(EVT3) +#define bfin_write_EVT3(val) bfin_write32(EVT3,val) +#define bfin_read_EVT4() bfin_read32(EVT4) +#define bfin_write_EVT4(val) bfin_write32(EVT4,val) +#define bfin_read_EVT5() bfin_read32(EVT5) +#define bfin_write_EVT5(val) bfin_write32(EVT5,val) +#define bfin_read_EVT6() bfin_read32(EVT6) +#define bfin_write_EVT6(val) bfin_write32(EVT6,val) +#define bfin_read_EVT7() bfin_read32(EVT7) +#define bfin_write_EVT7(val) bfin_write32(EVT7,val) +#define bfin_read_EVT8() bfin_read32(EVT8) +#define bfin_write_EVT8(val) bfin_write32(EVT8,val) +#define bfin_read_EVT9() bfin_read32(EVT9) +#define bfin_write_EVT9(val) bfin_write32(EVT9,val) +#define bfin_read_EVT10() bfin_read32(EVT10) +#define bfin_write_EVT10(val) bfin_write32(EVT10,val) +#define bfin_read_EVT11() bfin_read32(EVT11) +#define bfin_write_EVT11(val) bfin_write32(EVT11,val) +#define bfin_read_EVT12() bfin_read32(EVT12) +#define bfin_write_EVT12(val) bfin_write32(EVT12,val) +#define bfin_read_EVT13() bfin_read32(EVT13) +#define bfin_write_EVT13(val) bfin_write32(EVT13,val) +#define bfin_read_EVT14() bfin_read32(EVT14) +#define bfin_write_EVT14(val) bfin_write32(EVT14,val) +#define bfin_read_EVT15() bfin_read32(EVT15) +#define bfin_write_EVT15(val) bfin_write32(EVT15,val) +#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE) +#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE,val) +#define bfin_read_IMASK() bfin_read32(IMASK) +#define bfin_write_IMASK(val) bfin_write32(IMASK,val) +#define bfin_read_IPEND() bfin_read32(IPEND) +#define bfin_write_IPEND(val) bfin_write32(IPEND,val) +#define bfin_read_ILAT() bfin_read32(ILAT) +#define bfin_write_ILAT(val) bfin_write32(ILAT,val) +#define bfin_read_IPRIO() bfin_read32(IPRIO) +#define bfin_write_IPRIO(val) bfin_write32(IPRIO,val) + +/*Core Timer Registers*/ +#define bfin_read_TCNTL() bfin_read32(TCNTL) +#define bfin_write_TCNTL(val) bfin_write32(TCNTL,val) +#define bfin_read_TPERIOD() bfin_read32(TPERIOD) +#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD,val) +#define bfin_read_TSCALE() bfin_read32(TSCALE) +#define bfin_write_TSCALE(val) bfin_write32(TSCALE,val) +#define bfin_read_TCOUNT() bfin_read32(TCOUNT) +#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT,val) + +/*Debug/MP/Emulation Registers*/ +#define bfin_read_DSPID() bfin_read32(DSPID) +#define bfin_write_DSPID(val) bfin_write32(DSPID,val) +#define bfin_read_DBGCTL() bfin_read32(DBGCTL) +#define bfin_write_DBGCTL(val) bfin_write32(DBGCTL,val) +#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT) +#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT,val) +#define bfin_read_EMUDAT() bfin_read32(EMUDAT) +#define bfin_write_EMUDAT(val) bfin_write32(EMUDAT,val) + +/*Trace Buffer Registers*/ +#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) +#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL,val) +#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) +#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT,val) +#define bfin_read_TBUF() bfin_read32(TBUF) +#define bfin_write_TBUF(val) bfin_write32(TBUF,val) + +/*Watch Point Control Registers*/ +#define bfin_read_WPIACTL() bfin_read32(WPIACTL) +#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL,val) +#define bfin_read_WPIA0() bfin_read32(WPIA0) +#define bfin_write_WPIA0(val) bfin_write32(WPIA0,val) +#define bfin_read_WPIA1() bfin_read32(WPIA1) +#define bfin_write_WPIA1(val) bfin_write32(WPIA1,val) +#define bfin_read_WPIA2() bfin_read32(WPIA2) +#define bfin_write_WPIA2(val) bfin_write32(WPIA2,val) +#define bfin_read_WPIA3() bfin_read32(WPIA3) +#define bfin_write_WPIA3(val) bfin_write32(WPIA3,val) +#define bfin_read_WPIA4() bfin_read32(WPIA4) +#define bfin_write_WPIA4(val) bfin_write32(WPIA4,val) +#define bfin_read_WPIA5() bfin_read32(WPIA5) +#define bfin_write_WPIA5(val) bfin_write32(WPIA5,val) +#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0) +#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0,val) +#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1) +#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1,val) +#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2) +#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2,val) +#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3) +#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3,val) +#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4) +#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4,val) +#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5) +#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5,val) +#define bfin_read_WPDACTL() bfin_read32(WPDACTL) +#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL,val) +#define bfin_read_WPDA0() bfin_read32(WPDA0) +#define bfin_write_WPDA0(val) bfin_write32(WPDA0,val) +#define bfin_read_WPDA1() bfin_read32(WPDA1) +#define bfin_write_WPDA1(val) bfin_write32(WPDA1,val) +#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0) +#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0,val) +#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1) +#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1,val) +#define bfin_read_WPSTAT() bfin_read32(WPSTAT) +#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT,val) + +/*Performance Monitor Registers*/ +#define bfin_read_PFCTL() bfin_read32(PFCTL) +#define bfin_write_PFCTL(val) bfin_write32(PFCTL,val) +#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) +#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0,val) +#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) +#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val) + +#endif /* _CDEF_LPBLACKFIN_H */ diff --git a/kernel/arch/blackfin/include/asm/checksum.h b/kernel/arch/blackfin/include/asm/checksum.h new file mode 100644 index 000000000..623cc7fb0 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/checksum.h @@ -0,0 +1,44 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * akbar.hussain@lineo.com + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BFIN_CHECKSUM_H +#define _BFIN_CHECKSUM_H + +/* + * computes the checksum of the TCP/UDP pseudo-header + * returns a 16-bit checksum, already complemented + */ + +static inline __wsum +__csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, + unsigned short proto, __wsum sum) +{ + unsigned int carry; + + __asm__ ("%0 = %0 + %2;\n\t" + "CC = AC0;\n\t" + "%1 = CC;\n\t" + "%0 = %0 + %1;\n\t" + "%0 = %0 + %3;\n\t" + "CC = AC0;\n\t" + "%1 = CC;\n\t" + "%0 = %0 + %1;\n\t" + "%0 = %0 + %4;\n\t" + "CC = AC0;\n\t" + "%1 = CC;\n\t" + "%0 = %0 + %1;\n\t" + : "=d" (sum), "=&d" (carry) + : "d" (daddr), "d" (saddr), "d" ((len + proto) << 8), "0"(sum) + : "CC"); + + return (sum); +} +#define csum_tcpudp_nofold __csum_tcpudp_nofold + +#include <asm-generic/checksum.h> + +#endif diff --git a/kernel/arch/blackfin/include/asm/clkdev.h b/kernel/arch/blackfin/include/asm/clkdev.h new file mode 100644 index 000000000..7ac243685 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/clkdev.h @@ -0,0 +1,16 @@ +#ifndef __ASM_CLKDEV__H_ +#define __ASM_CLKDEV__H_ + +#include <linux/slab.h> + +static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) +{ + return kzalloc(size, GFP_KERNEL); +} + +#ifndef CONFIG_COMMON_CLK +#define __clk_put(clk) +#define __clk_get(clk) ({ 1; }) +#endif + +#endif diff --git a/kernel/arch/blackfin/include/asm/clocks.h b/kernel/arch/blackfin/include/asm/clocks.h new file mode 100644 index 000000000..9b3c85b3c --- /dev/null +++ b/kernel/arch/blackfin/include/asm/clocks.h @@ -0,0 +1,74 @@ +/* + * Common Clock definitions for various kernel files + * + * Copyright 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BFIN_CLOCKS_H +#define _BFIN_CLOCKS_H + +#include <asm/dpmc.h> + +#ifdef CONFIG_CCLK_DIV_1 +# define CONFIG_CCLK_ACT_DIV CCLK_DIV1 +# define CONFIG_CCLK_DIV 1 +#endif + +#ifdef CONFIG_CCLK_DIV_2 +# define CONFIG_CCLK_ACT_DIV CCLK_DIV2 +# define CONFIG_CCLK_DIV 2 +#endif + +#ifdef CONFIG_CCLK_DIV_4 +# define CONFIG_CCLK_ACT_DIV CCLK_DIV4 +# define CONFIG_CCLK_DIV 4 +#endif + +#ifdef CONFIG_CCLK_DIV_8 +# define CONFIG_CCLK_ACT_DIV CCLK_DIV8 +# define CONFIG_CCLK_DIV 8 +#endif + +#ifndef CONFIG_PLL_BYPASS +# ifndef CONFIG_CLKIN_HALF +# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) +# else +# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2) +# endif + +# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV) +# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV) + +#else +# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ) +# define CONFIG_CCLK_HZ (CONFIG_CLKIN_HZ) +# define CONFIG_SCLK_HZ (CONFIG_CLKIN_HZ) +# define CONFIG_VCO_MULT 0 +#endif + +#include <linux/clk.h> + +struct clk_ops { + unsigned long (*get_rate)(struct clk *clk); + unsigned long (*round_rate)(struct clk *clk, unsigned long rate); + int (*set_rate)(struct clk *clk, unsigned long rate); + int (*enable)(struct clk *clk); + int (*disable)(struct clk *clk); +}; + +struct clk { + struct clk *parent; + const char *name; + unsigned long rate; + spinlock_t lock; + u32 flags; + const struct clk_ops *ops; + void __iomem *reg; + u32 mask; + u32 shift; +}; + +int clk_init(void); +#endif diff --git a/kernel/arch/blackfin/include/asm/cmpxchg.h b/kernel/arch/blackfin/include/asm/cmpxchg.h new file mode 100644 index 000000000..c05868cc6 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/cmpxchg.h @@ -0,0 +1,133 @@ +/* + * Copyright 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ARCH_BLACKFIN_CMPXCHG__ +#define __ARCH_BLACKFIN_CMPXCHG__ + +#ifdef CONFIG_SMP + +#include <linux/linkage.h> + +asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value); +asmlinkage unsigned long __raw_xchg_2_asm(volatile void *ptr, unsigned long value); +asmlinkage unsigned long __raw_xchg_4_asm(volatile void *ptr, unsigned long value); +asmlinkage unsigned long __raw_cmpxchg_1_asm(volatile void *ptr, + unsigned long new, unsigned long old); +asmlinkage unsigned long __raw_cmpxchg_2_asm(volatile void *ptr, + unsigned long new, unsigned long old); +asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr, + unsigned long new, unsigned long old); + +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, + int size) +{ + unsigned long tmp; + + switch (size) { + case 1: + tmp = __raw_xchg_1_asm(ptr, x); + break; + case 2: + tmp = __raw_xchg_2_asm(ptr, x); + break; + case 4: + tmp = __raw_xchg_4_asm(ptr, x); + break; + } + + return tmp; +} + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ +static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, + unsigned long new, int size) +{ + unsigned long tmp; + + switch (size) { + case 1: + tmp = __raw_cmpxchg_1_asm(ptr, new, old); + break; + case 2: + tmp = __raw_cmpxchg_2_asm(ptr, new, old); + break; + case 4: + tmp = __raw_cmpxchg_4_asm(ptr, new, old); + break; + } + + return tmp; +} +#define cmpxchg(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ + (unsigned long)(n), sizeof(*(ptr)))) + +#else /* !CONFIG_SMP */ + +#include <mach/blackfin.h> +#include <asm/irqflags.h> + +struct __xchg_dummy { + unsigned long a[100]; +}; +#define __xg(x) ((volatile struct __xchg_dummy *)(x)) + +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, + int size) +{ + unsigned long tmp = 0; + unsigned long flags; + + flags = hard_local_irq_save(); + + switch (size) { + case 1: + __asm__ __volatile__ + ("%0 = b%2 (z);\n\t" + "b%2 = %1;\n\t" + : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + case 2: + __asm__ __volatile__ + ("%0 = w%2 (z);\n\t" + "w%2 = %1;\n\t" + : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + case 4: + __asm__ __volatile__ + ("%0 = %2;\n\t" + "%2 = %1;\n\t" + : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + } + hard_local_irq_restore(flags); + return tmp; +} + +#include <asm-generic/cmpxchg-local.h> + +/* + * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make + * them available. + */ +#define cmpxchg_local(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ + (unsigned long)(n), sizeof(*(ptr)))) +#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) + +#define cmpxchg(ptr, o, n) cmpxchg_local((ptr), (o), (n)) +#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n)) + +#endif /* !CONFIG_SMP */ + +#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))) +#define tas(ptr) ((void)xchg((ptr), 1)) + +#endif /* __ARCH_BLACKFIN_CMPXCHG__ */ diff --git a/kernel/arch/blackfin/include/asm/context.S b/kernel/arch/blackfin/include/asm/context.S new file mode 100644 index 000000000..507e7aa6a --- /dev/null +++ b/kernel/arch/blackfin/include/asm/context.S @@ -0,0 +1,407 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +/* + * NOTE! The single-stepping code assumes that all interrupt handlers + * start by saving SYSCFG on the stack with their first instruction. + */ + +/* + * Code to save processor context. + * We even save the register which are preserved by a function call + * - r4, r5, r6, r7, p3, p4, p5 + */ +.macro save_context_with_interrupts + [--sp] = SYSCFG; + + [--sp] = P0; /*orig_p0*/ + [--sp] = R0; /*orig_r0*/ + + [--sp] = ( R7:0, P5:0 ); + [--sp] = fp; + [--sp] = usp; + + [--sp] = i0; + [--sp] = i1; + [--sp] = i2; + [--sp] = i3; + + [--sp] = m0; + [--sp] = m1; + [--sp] = m2; + [--sp] = m3; + + [--sp] = l0; + [--sp] = l1; + [--sp] = l2; + [--sp] = l3; + + [--sp] = b0; + [--sp] = b1; + [--sp] = b2; + [--sp] = b3; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + + [--sp] = LC0; + [--sp] = LC1; + [--sp] = LT0; + [--sp] = LT1; + [--sp] = LB0; + [--sp] = LB1; + + [--sp] = ASTAT; + + [--sp] = r0; /* Skip reserved */ + [--sp] = RETS; + r0 = RETI; + [--sp] = r0; + [--sp] = RETX; + [--sp] = RETN; + [--sp] = RETE; + [--sp] = SEQSTAT; + [--sp] = r0; /* Skip IPEND as well. */ + /* Switch to other method of keeping interrupts disabled. */ +#ifdef CONFIG_DEBUG_HWERR + r0 = 0x3f; + sti r0; +#else + cli r0; +#endif +#ifdef CONFIG_TRACE_IRQFLAGS + sp += -12; + call _trace_hardirqs_off; + sp += 12; +#endif + [--sp] = RETI; /*orig_pc*/ + /* Clear all L registers. */ + r0 = 0 (x); + l0 = r0; + l1 = r0; + l2 = r0; + l3 = r0; +.endm + +.macro save_context_syscall + [--sp] = SYSCFG; + + [--sp] = P0; /*orig_p0*/ + [--sp] = R0; /*orig_r0*/ + [--sp] = ( R7:0, P5:0 ); + [--sp] = fp; + [--sp] = usp; + + [--sp] = i0; + [--sp] = i1; + [--sp] = i2; + [--sp] = i3; + + [--sp] = m0; + [--sp] = m1; + [--sp] = m2; + [--sp] = m3; + + [--sp] = l0; + [--sp] = l1; + [--sp] = l2; + [--sp] = l3; + + [--sp] = b0; + [--sp] = b1; + [--sp] = b2; + [--sp] = b3; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + + [--sp] = LC0; + [--sp] = LC1; + [--sp] = LT0; + [--sp] = LT1; + [--sp] = LB0; + [--sp] = LB1; + + [--sp] = ASTAT; + + [--sp] = r0; /* Skip reserved */ + [--sp] = RETS; + r0 = RETI; + [--sp] = r0; + [--sp] = RETX; + [--sp] = RETN; + [--sp] = RETE; + [--sp] = SEQSTAT; + [--sp] = r0; /* Skip IPEND as well. */ + [--sp] = RETI; /*orig_pc*/ + /* Clear all L registers. */ + r0 = 0 (x); + l0 = r0; + l1 = r0; + l2 = r0; + l3 = r0; +.endm + +.macro save_context_no_interrupts + [--sp] = SYSCFG; + [--sp] = P0; /* orig_p0 */ + [--sp] = R0; /* orig_r0 */ + [--sp] = ( R7:0, P5:0 ); + [--sp] = fp; + [--sp] = usp; + + [--sp] = i0; + [--sp] = i1; + [--sp] = i2; + [--sp] = i3; + + [--sp] = m0; + [--sp] = m1; + [--sp] = m2; + [--sp] = m3; + + [--sp] = l0; + [--sp] = l1; + [--sp] = l2; + [--sp] = l3; + + [--sp] = b0; + [--sp] = b1; + [--sp] = b2; + [--sp] = b3; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + + [--sp] = LC0; + [--sp] = LC1; + [--sp] = LT0; + [--sp] = LT1; + [--sp] = LB0; + [--sp] = LB1; + + [--sp] = ASTAT; + +#ifdef CONFIG_KGDB + fp = 0(Z); + r1 = sp; + r1 += 60; + r1 += 60; + r1 += 60; + [--sp] = r1; +#else + [--sp] = r0; /* Skip reserved */ +#endif + [--sp] = RETS; + r0 = RETI; + [--sp] = r0; + [--sp] = RETX; + [--sp] = RETN; + [--sp] = RETE; + [--sp] = SEQSTAT; +#ifdef CONFIG_DEBUG_KERNEL + p1.l = lo(IPEND); + p1.h = hi(IPEND); + r1 = [p1]; + [--sp] = r1; +#else + [--sp] = r0; /* Skip IPEND as well. */ +#endif + [--sp] = r0; /*orig_pc*/ + /* Clear all L registers. */ + r0 = 0 (x); + l0 = r0; + l1 = r0; + l2 = r0; + l3 = r0; +.endm + +.macro restore_context_no_interrupts + sp += 4; /* Skip orig_pc */ + sp += 4; /* Skip IPEND */ + SEQSTAT = [sp++]; + RETE = [sp++]; + RETN = [sp++]; + RETX = [sp++]; + r0 = [sp++]; + RETI = r0; /* Restore RETI indirectly when in exception */ + RETS = [sp++]; + + sp += 4; /* Skip Reserved */ + + ASTAT = [sp++]; + + LB1 = [sp++]; + LB0 = [sp++]; + LT1 = [sp++]; + LT0 = [sp++]; + LC1 = [sp++]; + LC0 = [sp++]; + + a1.w = [sp++]; + a1.x = [sp++]; + a0.w = [sp++]; + a0.x = [sp++]; + b3 = [sp++]; + b2 = [sp++]; + b1 = [sp++]; + b0 = [sp++]; + + l3 = [sp++]; + l2 = [sp++]; + l1 = [sp++]; + l0 = [sp++]; + + m3 = [sp++]; + m2 = [sp++]; + m1 = [sp++]; + m0 = [sp++]; + + i3 = [sp++]; + i2 = [sp++]; + i1 = [sp++]; + i0 = [sp++]; + + sp += 4; + fp = [sp++]; + + ( R7 : 0, P5 : 0) = [ SP ++ ]; + sp += 8; /* Skip orig_r0/orig_p0 */ + SYSCFG = [sp++]; +.endm + +.macro restore_context_with_interrupts + sp += 4; /* Skip orig_pc */ + sp += 4; /* Skip IPEND */ + SEQSTAT = [sp++]; + RETE = [sp++]; + RETN = [sp++]; + RETX = [sp++]; + RETI = [sp++]; + +#ifdef CONFIG_TRACE_IRQFLAGS + sp += -12; + call _trace_hardirqs_on; + sp += 12; +#endif + + RETS = [sp++]; + +#ifdef CONFIG_SMP + GET_PDA(p0, r0); + r0 = [p0 + PDA_IRQFLAGS]; +#else + p0.h = _bfin_irq_flags; + p0.l = _bfin_irq_flags; + r0 = [p0]; +#endif + sti r0; + + sp += 4; /* Skip Reserved */ + + ASTAT = [sp++]; + + LB1 = [sp++]; + LB0 = [sp++]; + LT1 = [sp++]; + LT0 = [sp++]; + LC1 = [sp++]; + LC0 = [sp++]; + + a1.w = [sp++]; + a1.x = [sp++]; + a0.w = [sp++]; + a0.x = [sp++]; + b3 = [sp++]; + b2 = [sp++]; + b1 = [sp++]; + b0 = [sp++]; + + l3 = [sp++]; + l2 = [sp++]; + l1 = [sp++]; + l0 = [sp++]; + + m3 = [sp++]; + m2 = [sp++]; + m1 = [sp++]; + m0 = [sp++]; + + i3 = [sp++]; + i2 = [sp++]; + i1 = [sp++]; + i0 = [sp++]; + + sp += 4; + fp = [sp++]; + + ( R7 : 0, P5 : 0) = [ SP ++ ]; + sp += 8; /* Skip orig_r0/orig_p0 */ + csync; + SYSCFG = [sp++]; + csync; +.endm + +.macro save_context_cplb + [--sp] = (R7:0, P5:0); + [--sp] = fp; + + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + + [--sp] = LC0; + [--sp] = LC1; + [--sp] = LT0; + [--sp] = LT1; + [--sp] = LB0; + [--sp] = LB1; + + [--sp] = RETS; +.endm + +.macro restore_context_cplb + RETS = [sp++]; + + LB1 = [sp++]; + LB0 = [sp++]; + LT1 = [sp++]; + LT0 = [sp++]; + LC1 = [sp++]; + LC0 = [sp++]; + + a1.w = [sp++]; + a1.x = [sp++]; + a0.w = [sp++]; + a0.x = [sp++]; + + fp = [sp++]; + + (R7:0, P5:0) = [SP++]; +.endm + +.macro pseudo_long_call func:req, scratch:req +#ifdef CONFIG_ROMKERNEL + \scratch\().l = \func; + \scratch\().h = \func; + call (\scratch); +#else + call \func; +#endif +.endm + +#if defined(CONFIG_BFIN_SCRATCH_REG_RETN) +# define EX_SCRATCH_REG RETN +#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE) +# define EX_SCRATCH_REG RETE +#else +# define EX_SCRATCH_REG CYCLES +#endif + diff --git a/kernel/arch/blackfin/include/asm/cplb.h b/kernel/arch/blackfin/include/asm/cplb.h new file mode 100644 index 000000000..5c37f620c --- /dev/null +++ b/kernel/arch/blackfin/include/asm/cplb.h @@ -0,0 +1,153 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _CPLB_H +#define _CPLB_H + +#include <mach/anomaly.h> + +#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) +#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) +#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) + +#if ANOMALY_05000158 +#define ANOMALY_05000158_WORKAROUND 0x200 +#else +#define ANOMALY_05000158_WORKAROUND 0x0 +#endif + +#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) + +#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK +#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) +#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH) +#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) +#else +#define SDRAM_DGENERIC (CPLB_COMMON) +#endif + +#define SDRAM_DNON_CHBL (CPLB_COMMON) +#define SDRAM_EBIU (CPLB_COMMON) +#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) + +#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) + +#ifdef CONFIG_SMP +#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) +#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) +#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB) + +#else +#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) +# if defined(CONFIG_BFIN_L2_ICACHEABLE) +# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) +# else +# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) +# endif + +# if defined(CONFIG_BFIN_L2_WRITEBACK) +# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB) +# elif defined(CONFIG_BFIN_L2_WRITETHROUGH) +# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB) +# else +# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) +# endif +#endif /* CONFIG_SMP */ + +#define SIZE_1K 0x00000400 /* 1K */ +#define SIZE_4K 0x00001000 /* 4K */ +#define SIZE_1M 0x00100000 /* 1M */ +#define SIZE_4M 0x00400000 /* 4M */ +#define SIZE_16K 0x00004000 /* 16K */ +#define SIZE_64K 0x00010000 /* 64K */ +#define SIZE_16M 0x01000000 /* 16M */ +#define SIZE_64M 0x04000000 /* 64M */ + +#define MAX_CPLBS 16 + +#define CPLB_ENABLE_ICACHE_P 0 +#define CPLB_ENABLE_DCACHE_P 1 +#define CPLB_ENABLE_DCACHE2_P 2 +#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */ +#define CPLB_ENABLE_ICPLBS_P 4 +#define CPLB_ENABLE_DCPLBS_P 5 + +#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P) +#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P) +#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P) +#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P) +#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P) +#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P) +#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \ + CPLB_ENABLE_ICPLBS | \ + CPLB_ENABLE_DCPLBS + +#define CPLB_RELOADED 0x0000 +#define CPLB_NO_UNLOCKED 0x0001 +#define CPLB_NO_ADDR_MATCH 0x0002 +#define CPLB_PROT_VIOL 0x0003 +#define CPLB_UNKNOWN_ERR 0x0004 + +#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT +#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY + +#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID +#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID +#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID +#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE +#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID +#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL + +#define FAULT_RW (1 << 16) +#define FAULT_USERSUPV (1 << 17) +#define FAULT_CPLBBITS 0x0000ffff + +#ifndef __ASSEMBLY__ + +static inline void _disable_cplb(u32 mmr, u32 mask) +{ + u32 ctrl = bfin_read32(mmr) & ~mask; + /* CSYNC to ensure load store ordering */ + __builtin_bfin_csync(); + bfin_write32(mmr, ctrl); + __builtin_bfin_ssync(); +} +static inline void disable_cplb(u32 mmr, u32 mask) +{ + u32 ctrl = bfin_read32(mmr) & ~mask; + CSYNC(); + bfin_write32(mmr, ctrl); + SSYNC(); +} +#define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB) +#define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB) +#define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB) +#define disable_icplb() disable_cplb(IMEM_CONTROL, ENICPLB) + +static inline void _enable_cplb(u32 mmr, u32 mask) +{ + u32 ctrl = bfin_read32(mmr) | mask; + /* CSYNC to ensure load store ordering */ + __builtin_bfin_csync(); + bfin_write32(mmr, ctrl); + __builtin_bfin_ssync(); +} +static inline void enable_cplb(u32 mmr, u32 mask) +{ + u32 ctrl = bfin_read32(mmr) | mask; + CSYNC(); + bfin_write32(mmr, ctrl); + SSYNC(); +} +#define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB) +#define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB) +#define _enable_icplb() _enable_cplb(IMEM_CONTROL, ENICPLB) +#define enable_icplb() enable_cplb(IMEM_CONTROL, ENICPLB) + +#endif /* __ASSEMBLY__ */ + +#endif /* _CPLB_H */ diff --git a/kernel/arch/blackfin/include/asm/cplbinit.h b/kernel/arch/blackfin/include/asm/cplbinit.h new file mode 100644 index 000000000..f315c83a0 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/cplbinit.h @@ -0,0 +1,66 @@ +/* + * Common CPLB definitions for CPLB init + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_CPLBINIT_H__ +#define __ASM_CPLBINIT_H__ + +#include <asm/blackfin.h> +#include <asm/cplb.h> +#include <linux/threads.h> + +#ifdef CONFIG_CPLB_SWITCH_TAB_L1 +# define PDT_ATTR __attribute__((l1_data)) +#else +# define PDT_ATTR +#endif + +struct cplb_entry { + unsigned long data, addr; +}; + +struct cplb_boundary { + unsigned long eaddr; /* End of this region. */ + unsigned long data; /* CPLB data value. */ +}; + +extern struct cplb_boundary dcplb_bounds[]; +extern struct cplb_boundary icplb_bounds[]; +extern int dcplb_nr_bounds, icplb_nr_bounds; + +extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS]; +extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS]; +extern int first_switched_icplb; +extern int first_switched_dcplb; + +extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[]; +extern int nr_dcplb_prot[], nr_cplb_flush[]; + +#ifdef CONFIG_MPU + +extern int first_mask_dcplb; + +extern int page_mask_order; +extern int page_mask_nelts; + +extern unsigned long *current_rwx_mask[NR_CPUS]; + +extern void flush_switched_cplbs(unsigned int); +extern void set_mask_dcplbs(unsigned long *, unsigned int); + +extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *); + +#endif /* CONFIG_MPU */ + +extern void bfin_icache_init(struct cplb_entry *icplb_tbl); +extern void bfin_dcache_init(struct cplb_entry *icplb_tbl); + +#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) +extern void generate_cplb_tables_all(void); +extern void generate_cplb_tables_cpu(unsigned int cpu); +#endif +#endif diff --git a/kernel/arch/blackfin/include/asm/cpu.h b/kernel/arch/blackfin/include/asm/cpu.h new file mode 100644 index 000000000..e349631c8 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/cpu.h @@ -0,0 +1,24 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * Philippe Gerum <rpm@xenomai.org> + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BLACKFIN_CPU_H +#define __ASM_BLACKFIN_CPU_H + +#include <linux/percpu.h> + +struct blackfin_cpudata { + struct cpu cpu; + unsigned int imemctl; + unsigned int dmemctl; +#ifdef CONFIG_SMP + struct task_struct *idle; +#endif +}; + +DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data); + +#endif diff --git a/kernel/arch/blackfin/include/asm/def_LPBlackfin.h b/kernel/arch/blackfin/include/asm/def_LPBlackfin.h new file mode 100644 index 000000000..c5c8d8a3a --- /dev/null +++ b/kernel/arch/blackfin/include/asm/def_LPBlackfin.h @@ -0,0 +1,697 @@ +/* + * Blackfin core register bit & address definitions + * + * Copyright 2005-2008 Analog Devices Inc. + * + * Licensed under the Clear BSD license or GPL-2 (or later). + */ + +#ifndef _DEF_LPBLACKFIN_H +#define _DEF_LPBLACKFIN_H + +#include <mach/anomaly.h> + +#define MK_BMSK_(x) (1<<x) +#define BFIN_DEPOSIT(mask, x) (((x) << __ffs(mask)) & (mask)) +#define BFIN_EXTRACT(mask, x) (((x) & (mask)) >> __ffs(mask)) + +#ifndef __ASSEMBLY__ + +#include <linux/types.h> + +#if ANOMALY_05000198 +# define NOP_PAD_ANOMALY_05000198 "nop;" +#else +# define NOP_PAD_ANOMALY_05000198 +#endif + +#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \ + u32 __v; \ + __asm__ __volatile__( \ + NOP_PAD_ANOMALY_05000198 \ + "%0 = " #asm_size "[%1]" #asm_ext ";" \ + : "=d" (__v) \ + : "a" (addr) \ + ); \ + __v; }) +#define _bfin_writeX(addr, val, size, asm_size) \ + __asm__ __volatile__( \ + NOP_PAD_ANOMALY_05000198 \ + #asm_size "[%0] = %1;" \ + : \ + : "a" (addr), "d" ((u##size)(val)) \ + : "memory" \ + ) + +#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z)) +#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z)) +#define bfin_read32(addr) _bfin_readX(addr, 32, , ) +#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b) +#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w) +#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, ) + +#define bfin_read(addr) \ +({ \ + sizeof(*(addr)) == 1 ? bfin_read8(addr) : \ + sizeof(*(addr)) == 2 ? bfin_read16(addr) : \ + sizeof(*(addr)) == 4 ? bfin_read32(addr) : \ + ({ BUG(); 0; }); \ +}) +#define bfin_write(addr, val) \ +do { \ + switch (sizeof(*(addr))) { \ + case 1: bfin_write8(addr, val); break; \ + case 2: bfin_write16(addr, val); break; \ + case 4: bfin_write32(addr, val); break; \ + default: BUG(); \ + } \ +} while (0) + +#define bfin_write_or(addr, bits) \ +do { \ + typeof(addr) __addr = (addr); \ + bfin_write(__addr, bfin_read(__addr) | (bits)); \ +} while (0) + +#define bfin_write_and(addr, bits) \ +do { \ + typeof(addr) __addr = (addr); \ + bfin_write(__addr, bfin_read(__addr) & (bits)); \ +} while (0) + +#endif /* __ASSEMBLY__ */ + +/************************************************** + * System Register Bits + **************************************************/ + +/************************************************** + * ASTAT register + **************************************************/ + +/* definitions of ASTAT bit positions*/ + +/*Result of last ALU0 or shifter operation is zero*/ +#define ASTAT_AZ_P 0x00000000 +/*Result of last ALU0 or shifter operation is negative*/ +#define ASTAT_AN_P 0x00000001 +/*Condition Code, used for holding comparison results*/ +#define ASTAT_CC_P 0x00000005 +/*Quotient Bit*/ +#define ASTAT_AQ_P 0x00000006 +/*Rounding mode, set for biased, clear for unbiased*/ +#define ASTAT_RND_MOD_P 0x00000008 +/*Result of last ALU0 operation generated a carry*/ +#define ASTAT_AC0_P 0x0000000C +/*Result of last ALU0 operation generated a carry*/ +#define ASTAT_AC0_COPY_P 0x00000002 +/*Result of last ALU1 operation generated a carry*/ +#define ASTAT_AC1_P 0x0000000D +/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/ +#define ASTAT_AV0_P 0x00000010 +/*Sticky version of ASTAT_AV0 */ +#define ASTAT_AV0S_P 0x00000011 +/*Result of last MAC1 operation overflowed, sticky for MAC*/ +#define ASTAT_AV1_P 0x00000012 +/*Sticky version of ASTAT_AV1 */ +#define ASTAT_AV1S_P 0x00000013 +/*Result of last ALU0 or MAC0 operation overflowed*/ +#define ASTAT_V_P 0x00000018 +/*Result of last ALU0 or MAC0 operation overflowed*/ +#define ASTAT_V_COPY_P 0x00000003 +/*Sticky version of ASTAT_V*/ +#define ASTAT_VS_P 0x00000019 + +/* Masks */ + +/*Result of last ALU0 or shifter operation is zero*/ +#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) +/*Result of last ALU0 or shifter operation is negative*/ +#define ASTAT_AN MK_BMSK_(ASTAT_AN_P) +/*Result of last ALU0 operation generated a carry*/ +#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) +/*Result of last ALU0 operation generated a carry*/ +#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) +/*Result of last ALU0 operation generated a carry*/ +#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) +/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/ +#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) +/*Result of last MAC1 operation overflowed, sticky for MAC*/ +#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) +/*Condition Code, used for holding comparison results*/ +#define ASTAT_CC MK_BMSK_(ASTAT_CC_P) +/*Quotient Bit*/ +#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) +/*Rounding mode, set for biased, clear for unbiased*/ +#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) +/*Overflow Bit*/ +#define ASTAT_V MK_BMSK_(ASTAT_V_P) +/*Overflow Bit*/ +#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) + +/************************************************** + * SEQSTAT register + **************************************************/ + +/* Bit Positions */ +#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */ +#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */ +#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */ +#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */ +#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */ +#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */ +#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, + * set by IDLE instruction. + */ +#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last + * reset was a software reset + * (=1) + */ +#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */ +#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */ +#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */ +#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */ +#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */ +/* Masks */ +/* Exception cause */ +#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \ + MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \ + MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \ + MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \ + MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \ + MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \ + 0) + +/* Indicates whether the last reset was a software reset (=1) */ +#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P)) + +/* Last hw error cause */ +#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \ + MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \ + MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \ + MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \ + MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \ + 0) + +/* Translate bits to something useful */ + +/* Last hw error cause */ +#define SEQSTAT_HWERRCAUSE_SHIFT (14) +#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT) +#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT) +#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT) +#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT) + +/************************************************** + * SYSCFG register + **************************************************/ + +/* Bit Positions */ +#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when + * set it forces an exception + * for each instruction executed + */ +#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */ +#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */ + +/* Masks */ + +/* Supervisor single step, when set it forces an exception for each + *instruction executed + */ +#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P ) +/* Enable cycle counter (=1) */ +#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P ) +/* Self Nesting Interrupt Enable */ +#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P) +/* Backward-compatibility for typos in prior releases */ +#define SYSCFG_SSSSTEP SYSCFG_SSSTEP +#define SYSCFG_CCCEN SYSCFG_CCEN + +/**************************************************** + * Core MMR Register Map + ****************************************************/ + +/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */ + +#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */ +#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ +#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside + * Buffer Status + */ +#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */ +#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside + * Buffer Fault Address + */ +#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside + * Buffer 0 + */ +#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside + * Buffer 1 + */ +#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside + * Buffer 2 + */ +#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection + * Lookaside Buffer 3 + */ +#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection + * Lookaside Buffer 4 + */ +#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection + * Lookaside Buffer 5 + */ +#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection + * Lookaside Buffer 6 + */ +#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection + * Lookaside Buffer 7 + */ +#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection + * Lookaside Buffer 8 + */ +#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection + * Lookaside Buffer 9 + */ +#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection + * Lookaside Buffer 10 + */ +#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection + * Lookaside Buffer 11 + */ +#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection + * Lookaside Buffer 12 + */ +#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection + * Lookaside Buffer 13 + */ +#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection + * Lookaside Buffer 14 + */ +#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection + * Lookaside Buffer 15 + */ +#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ +#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ +#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ +#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ +#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ +#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ +#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ +#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ +#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ +#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ +#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ +#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ +#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ +#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ +#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ +#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ +#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */ + +#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ +#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ +#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ + +/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */ + +#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ +#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */ +#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */ +#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */ +#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */ +#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability + * Protection Lookaside Buffer 0 + */ +#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability + * Protection Lookaside Buffer 1 + */ +#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability + * Protection Lookaside Buffer 2 + */ +#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability + * Protection Lookaside Buffer 3 + */ +#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability + * Protection Lookaside Buffer 4 + */ +#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability + * Protection Lookaside Buffer 5 + */ +#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability + * Protection Lookaside Buffer 6 + */ +#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability + * Protection Lookaside Buffer 7 + */ +#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability + * Protection Lookaside Buffer 8 + */ +#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability + * Protection Lookaside Buffer 9 + */ +#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability + * Protection Lookaside Buffer 10 + */ +#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability + * Protection Lookaside Buffer 11 + */ +#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability + * Protection Lookaside Buffer 12 + */ +#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability + * Protection Lookaside Buffer 13 + */ +#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability + * Protection Lookaside Buffer 14 + */ +#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability + * Protection Lookaside Buffer 15 + */ +#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ +#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ +#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ +#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ +#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ +#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ +#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ +#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ +#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ +#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ +#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ +#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ +#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ +#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ +#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ +#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ +#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ +#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ +#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ + +/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */ + +#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ +#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ +#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ +#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ +#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ +#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ +#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ +#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ +#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ +#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ +#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ +#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ +#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ +#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ +#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ +#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ +#define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */ +#define IMASK 0xFFE02104 /* Interrupt Mask Register */ +#define IPEND 0xFFE02108 /* Interrupt Pending Register */ +#define ILAT 0xFFE0210C /* Interrupt Latch Register */ +#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */ + +/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */ + +#define TCNTL 0xFFE03000 /* Core Timer Control Register */ +#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ +#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ +#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ + +/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */ +#define DSPID 0xFFE05000 /* DSP Processor ID Register for + * MP implementations + */ + +#define DBGSTAT 0xFFE05008 /* Debug Status Register */ + +/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */ + +#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ +#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ +#define TBUF 0xFFE06100 /* Trace Buffer */ + +/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */ + +/* Watchpoint Instruction Address Control Register */ +#define WPIACTL 0xFFE07000 +/* Watchpoint Instruction Address Register 0 */ +#define WPIA0 0xFFE07040 +/* Watchpoint Instruction Address Register 1 */ +#define WPIA1 0xFFE07044 +/* Watchpoint Instruction Address Register 2 */ +#define WPIA2 0xFFE07048 +/* Watchpoint Instruction Address Register 3 */ +#define WPIA3 0xFFE0704C +/* Watchpoint Instruction Address Register 4 */ +#define WPIA4 0xFFE07050 +/* Watchpoint Instruction Address Register 5 */ +#define WPIA5 0xFFE07054 +/* Watchpoint Instruction Address Count Register 0 */ +#define WPIACNT0 0xFFE07080 +/* Watchpoint Instruction Address Count Register 1 */ +#define WPIACNT1 0xFFE07084 +/* Watchpoint Instruction Address Count Register 2 */ +#define WPIACNT2 0xFFE07088 +/* Watchpoint Instruction Address Count Register 3 */ +#define WPIACNT3 0xFFE0708C +/* Watchpoint Instruction Address Count Register 4 */ +#define WPIACNT4 0xFFE07090 +/* Watchpoint Instruction Address Count Register 5 */ +#define WPIACNT5 0xFFE07094 +/* Watchpoint Data Address Control Register */ +#define WPDACTL 0xFFE07100 +/* Watchpoint Data Address Register 0 */ +#define WPDA0 0xFFE07140 +/* Watchpoint Data Address Register 1 */ +#define WPDA1 0xFFE07144 +/* Watchpoint Data Address Count Value Register 0 */ +#define WPDACNT0 0xFFE07180 +/* Watchpoint Data Address Count Value Register 1 */ +#define WPDACNT1 0xFFE07184 +/* Watchpoint Status Register */ +#define WPSTAT 0xFFE07200 + +/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */ + +/* Performance Monitor Control Register */ +#define PFCTL 0xFFE08000 +/* Performance Monitor Counter Register 0 */ +#define PFCNTR0 0xFFE08100 +/* Performance Monitor Counter Register 1 */ +#define PFCNTR1 0xFFE08104 + +/**************************************************** + * Core MMR Register Bits + ****************************************************/ + +/************************************************** + * EVT registers (ILAT, IMASK, and IPEND). + **************************************************/ + +/* Bit Positions */ +#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */ +#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */ +#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */ +#define EVT_EVX_P 0x00000003 /* Exception bit position */ +#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */ +#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */ +#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */ +#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */ +#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */ +#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */ +#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */ +#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */ +#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */ +#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */ +#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */ +#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */ + +/* Masks */ +#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */ +#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */ +#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */ +#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */ +#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */ +#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */ +#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */ +#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */ +#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */ +#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */ +#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */ +#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */ +#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */ +#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */ +#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */ +#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */ + +/************************************************** + * DMEM_CONTROL Register + **************************************************/ +/* Bit Positions */ +#define ENDM_P 0x00 /* (doesn't really exist) Enable + *Data Memory L1 + */ +#define DMCTL_ENDM_P ENDM_P /* "" (older define) */ + +#define ENDCPLB_P 0x01 /* Enable DCPLBS */ +#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */ +#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */ +#define DMCTL_DMC0_P DMC0_P /* "" (older define) */ +#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */ +#define DMCTL_DMC1_P DMC1_P /* "" (older define) */ +#define DCBS_P 0x04 /* L1 Data Cache Bank Select */ +#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */ +#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */ +#define RDCHK 0x9 /* Enable L1 Parity Check */ + +/* Masks */ +#define ENDM 0x00000001 /* (doesn't really exist) Enable + * Data Memory L1 + */ +#define ENDCPLB 0x00000002 /* Enable DCPLB */ +#define ASRAM_BSRAM 0x00000000 +#define ACACHE_BSRAM 0x00000008 +#define ACACHE_BCACHE 0x0000000C +#define DCBS 0x00000010 /* L1 Data Cache Bank Select */ +#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */ +#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */ + +/* IMEM_CONTROL Register */ +/* Bit Positions */ +#define ENIM_P 0x00 /* Enable L1 Code Memory */ +#define IMCTL_ENIM_P 0x00 /* "" (older define) */ +#define ENICPLB_P 0x01 /* Enable ICPLB */ +#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */ +#define IMC_P 0x02 /* Enable */ +#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as + * cache (0=SRAM) + */ +#define ILOC0_P 0x03 /* Lock Way 0 */ +#define ILOC1_P 0x04 /* Lock Way 1 */ +#define ILOC2_P 0x05 /* Lock Way 2 */ +#define ILOC3_P 0x06 /* Lock Way 3 */ +#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement + * Priority + */ +/* Masks */ +#define ENIM 0x00000001 /* Enable L1 Code Memory */ +#define ENICPLB 0x00000002 /* Enable ICPLB */ +#define IMC 0x00000004 /* Configure L1 code memory as + * cache (0=SRAM) + */ +#define ILOC0 0x00000008 /* Lock Way 0 */ +#define ILOC1 0x00000010 /* Lock Way 1 */ +#define ILOC2 0x00000020 /* Lock Way 2 */ +#define ILOC3 0x00000040 /* Lock Way 3 */ +#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement + * Priority + */ + +/* TCNTL Masks */ +#define TMPWR 0x00000001 /* Timer Low Power Control, + * 0=low power mode, 1=active state + */ +#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */ +#define TAUTORLD 0x00000004 /* Timer auto reload */ +#define TINT 0x00000008 /* Timer generated interrupt 0=no + * interrupt has been generated, + * 1=interrupt has been generated + * (sticky) + */ + +/* DCPLB_DATA and ICPLB_DATA Registers */ +/* Bit Positions */ +#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ +#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry + * locked + */ +#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access + * allowed (user mode) + */ +/* Masks */ +#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ +#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry + * locked + */ +#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access + * allowed (user mode) + */ + +#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ +#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ +#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ +#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ +#ifdef CONFIG_BF60x +#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */ +#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */ +#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */ +#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */ +#endif +#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not + * mapped to L1 + */ +#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high + * priority port + */ +#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable + * in L1 + */ +/* ICPLB_DATA only */ +#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, + * 1=priority for non-replacement + */ +/* DCPLB_DATA only */ +#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write + * access allowed (user mode) + */ +#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write + * access allowed (supervisor mode) + */ +#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ +#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on + * write-through writes, + * 1= allocate cache lines on + * write-through writes. + */ +#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ + +#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR + +/* TBUFCTL Masks */ +#define TBUFPWR 0x0001 +#define TBUFEN 0x0002 +#define TBUFOVF 0x0004 +#define TBUFCMPLP_SINGLE 0x0008 +#define TBUFCMPLP_DOUBLE 0x0010 +#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE) + +/* TBUFSTAT Masks */ +#define TBUFCNT 0x001F + +/* ITEST_COMMAND and DTEST_COMMAND Registers */ +/* Masks */ +#define TEST_READ 0x00000000 /* Read Access */ +#define TEST_WRITE 0x00000002 /* Write Access */ +#define TEST_TAG 0x00000000 /* Access TAG */ +#define TEST_DATA 0x00000004 /* Access DATA */ +#define TEST_DW0 0x00000000 /* Select Double Word 0 */ +#define TEST_DW1 0x00000008 /* Select Double Word 1 */ +#define TEST_DW2 0x00000010 /* Select Double Word 2 */ +#define TEST_DW3 0x00000018 /* Select Double Word 3 */ +#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */ +#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */ +#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */ +#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */ +#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */ +#define TEST_WAY0 0x00000000 /* Access Way0 */ +#define TEST_WAY1 0x04000000 /* Access Way1 */ +/* ITEST_COMMAND only */ +#define TEST_WAY2 0x08000000 /* Access Way2 */ +#define TEST_WAY3 0x0C000000 /* Access Way3 */ +/* DTEST_COMMAND only */ +#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ +#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ + +#endif /* _DEF_LPBLACKFIN_H */ diff --git a/kernel/arch/blackfin/include/asm/delay.h b/kernel/arch/blackfin/include/asm/delay.h new file mode 100644 index 000000000..171d8deb0 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/delay.h @@ -0,0 +1,51 @@ +/* + * delay.h - delay functions + * + * Copyright (c) 2004-2007 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_DELAY_H__ +#define __ASM_DELAY_H__ + +#include <mach/anomaly.h> + +static inline void __delay(unsigned long loops) +{ +__asm__ __volatile__ ( + "LSETUP(1f, 1f) LC0 = %0;" + "1: NOP;" + : + : "a" (loops) + : "LT0", "LB0", "LC0" + ); +} + +#include <linux/param.h> /* needed for HZ */ + +/* + * close approximation borrowed from m68knommu to avoid 64-bit math + */ + +#define HZSCALE (268435456 / (1000000/HZ)) + +static inline unsigned long __to_delay(unsigned long scale) +{ + extern unsigned long loops_per_jiffy; + return (((scale * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6; +} + +static inline void udelay(unsigned long usecs) +{ + __delay(__to_delay(usecs)); +} + +static inline void ndelay(unsigned long nsecs) +{ + __delay(__to_delay(1) * nsecs / 1000); +} + +#define ndelay ndelay + +#endif diff --git a/kernel/arch/blackfin/include/asm/dma-mapping.h b/kernel/arch/blackfin/include/asm/dma-mapping.h new file mode 100644 index 000000000..054d9ec57 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/dma-mapping.h @@ -0,0 +1,167 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_DMA_MAPPING_H +#define _BLACKFIN_DMA_MAPPING_H + +#include <asm/cacheflush.h> +struct scatterlist; + +void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp); +void dma_free_coherent(struct device *dev, size_t size, void *vaddr, + dma_addr_t dma_handle); + +/* + * Now for the API extensions over the pci_ one + */ +#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) +#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) +#define dma_supported(d, m) (1) + +static inline int +dma_set_mask(struct device *dev, u64 dma_mask) +{ + if (!dev->dma_mask || !dma_supported(dev, dma_mask)) + return -EIO; + + *dev->dma_mask = dma_mask; + + return 0; +} + +static inline int +dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +{ + return 0; +} + +extern void +__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir); +static inline void +__dma_sync_inline(dma_addr_t addr, size_t size, enum dma_data_direction dir) +{ + switch (dir) { + case DMA_NONE: + BUG(); + case DMA_TO_DEVICE: /* writeback only */ + flush_dcache_range(addr, addr + size); + break; + case DMA_FROM_DEVICE: /* invalidate only */ + case DMA_BIDIRECTIONAL: /* flush and invalidate */ + /* Blackfin has no dedicated invalidate (it includes a flush) */ + invalidate_dcache_range(addr, addr + size); + break; + } +} +static inline void +_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir) +{ + if (__builtin_constant_p(dir)) + __dma_sync_inline(addr, size, dir); + else + __dma_sync(addr, size, dir); +} + +static inline dma_addr_t +dma_map_single(struct device *dev, void *ptr, size_t size, + enum dma_data_direction dir) +{ + _dma_sync((dma_addr_t)ptr, size, dir); + return (dma_addr_t) ptr; +} + +static inline dma_addr_t +dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir) +{ + return dma_map_single(dev, page_address(page) + offset, size, dir); +} + +static inline void +dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction dir) +{ + BUG_ON(!valid_dma_direction(dir)); +} + +static inline void +dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction dir) +{ + dma_unmap_single(dev, dma_addr, size, dir); +} + +extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir); + +static inline void +dma_unmap_sg(struct device *dev, struct scatterlist *sg, + int nhwentries, enum dma_data_direction dir) +{ + BUG_ON(!valid_dma_direction(dir)); +} + +static inline void +dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t handle, + unsigned long offset, size_t size, + enum dma_data_direction dir) +{ + BUG_ON(!valid_dma_direction(dir)); +} + +static inline void +dma_sync_single_range_for_device(struct device *dev, dma_addr_t handle, + unsigned long offset, size_t size, + enum dma_data_direction dir) +{ + _dma_sync(handle + offset, size, dir); +} + +static inline void +dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size, + enum dma_data_direction dir) +{ + dma_sync_single_range_for_cpu(dev, handle, 0, size, dir); +} + +static inline void +dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size, + enum dma_data_direction dir) +{ + dma_sync_single_range_for_device(dev, handle, 0, size, dir); +} + +static inline void +dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir) +{ + BUG_ON(!valid_dma_direction(dir)); +} + +extern void +dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir); + +static inline void +dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction dir) +{ + _dma_sync((dma_addr_t)vaddr, size, dir); +} + +/* drivers/base/dma-mapping.c */ +extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma, + void *cpu_addr, dma_addr_t dma_addr, size_t size); +extern int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt, + void *cpu_addr, dma_addr_t dma_addr, + size_t size); + +#define dma_mmap_coherent(d, v, c, h, s) dma_common_mmap(d, v, c, h, s) +#define dma_get_sgtable(d, t, v, h, s) dma_common_get_sgtable(d, t, v, h, s) + +#endif /* _BLACKFIN_DMA_MAPPING_H */ diff --git a/kernel/arch/blackfin/include/asm/dma.h b/kernel/arch/blackfin/include/asm/dma.h new file mode 100644 index 000000000..40e9c2bbc --- /dev/null +++ b/kernel/arch/blackfin/include/asm/dma.h @@ -0,0 +1,349 @@ +/* + * dma.h - Blackfin DMA defines/structures/etc... + * + * Copyright 2004-2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_DMA_H_ +#define _BLACKFIN_DMA_H_ + +#include <linux/interrupt.h> +#include <mach/dma.h> +#include <linux/atomic.h> +#include <asm/blackfin.h> +#include <asm/page.h> +#include <asm-generic/dma.h> +#include <asm/bfin_dma.h> + +/*------------------------- + * config reg bits value + *-------------------------*/ +#define DATA_SIZE_8 0 +#define DATA_SIZE_16 1 +#define DATA_SIZE_32 2 +#ifdef CONFIG_BF60x +#define DATA_SIZE_64 3 +#endif + +#define DMA_FLOW_STOP 0 +#define DMA_FLOW_AUTO 1 +#ifdef CONFIG_BF60x +#define DMA_FLOW_LIST 4 +#define DMA_FLOW_ARRAY 5 +#define DMA_FLOW_LIST_DEMAND 6 +#define DMA_FLOW_ARRAY_DEMAND 7 +#else +#define DMA_FLOW_ARRAY 4 +#define DMA_FLOW_SMALL 6 +#define DMA_FLOW_LARGE 7 +#endif + +#define DIMENSION_LINEAR 0 +#define DIMENSION_2D 1 + +#define DIR_READ 0 +#define DIR_WRITE 1 + +#define INTR_DISABLE 0 +#ifdef CONFIG_BF60x +#define INTR_ON_PERI 1 +#endif +#define INTR_ON_BUF 2 +#define INTR_ON_ROW 3 + +#define DMA_NOSYNC_KEEP_DMA_BUF 0 +#define DMA_SYNC_RESTART 1 + +#ifdef DMA_MMR_SIZE_32 +#define DMA_MMR_SIZE_TYPE long +#define DMA_MMR_READ bfin_read32 +#define DMA_MMR_WRITE bfin_write32 +#else +#define DMA_MMR_SIZE_TYPE short +#define DMA_MMR_READ bfin_read16 +#define DMA_MMR_WRITE bfin_write16 +#endif + +struct dma_desc_array { + unsigned long start_addr; + unsigned DMA_MMR_SIZE_TYPE cfg; + unsigned DMA_MMR_SIZE_TYPE x_count; + DMA_MMR_SIZE_TYPE x_modify; +} __attribute__((packed)); + +struct dmasg { + void *next_desc_addr; + unsigned long start_addr; + unsigned DMA_MMR_SIZE_TYPE cfg; + unsigned DMA_MMR_SIZE_TYPE x_count; + DMA_MMR_SIZE_TYPE x_modify; + unsigned DMA_MMR_SIZE_TYPE y_count; + DMA_MMR_SIZE_TYPE y_modify; +} __attribute__((packed)); + +struct dma_register { + void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ + unsigned long start_addr; /* DMA Start address register */ +#ifdef CONFIG_BF60x + unsigned long cfg; /* DMA Configuration register */ + + unsigned long x_count; /* DMA x_count register */ + + long x_modify; /* DMA x_modify register */ + + unsigned long y_count; /* DMA y_count register */ + + long y_modify; /* DMA y_modify register */ + + unsigned long reserved; + unsigned long reserved2; + + void *curr_desc_ptr; /* DMA Current Descriptor Pointer + register */ + void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer + register */ + unsigned long curr_addr_ptr; /* DMA Current Address Pointer + register */ + unsigned long irq_status; /* DMA irq status register */ + + unsigned long curr_x_count; /* DMA Current x-count register */ + + unsigned long curr_y_count; /* DMA Current y-count register */ + + unsigned long reserved3; + + unsigned long bw_limit_count; /* DMA band width limit count register */ + unsigned long curr_bw_limit_count; /* DMA Current band width limit + count register */ + unsigned long bw_monitor_count; /* DMA band width limit count register */ + unsigned long curr_bw_monitor_count; /* DMA Current band width limit + count register */ +#else + unsigned short cfg; /* DMA Configuration register */ + unsigned short dummy1; /* DMA Configuration register */ + + unsigned long reserved; + + unsigned short x_count; /* DMA x_count register */ + unsigned short dummy2; + + short x_modify; /* DMA x_modify register */ + unsigned short dummy3; + + unsigned short y_count; /* DMA y_count register */ + unsigned short dummy4; + + short y_modify; /* DMA y_modify register */ + unsigned short dummy5; + + void *curr_desc_ptr; /* DMA Current Descriptor Pointer + register */ + unsigned long curr_addr_ptr; /* DMA Current Address Pointer + register */ + unsigned short irq_status; /* DMA irq status register */ + unsigned short dummy6; + + unsigned short peripheral_map; /* DMA peripheral map register */ + unsigned short dummy7; + + unsigned short curr_x_count; /* DMA Current x-count register */ + unsigned short dummy8; + + unsigned long reserved2; + + unsigned short curr_y_count; /* DMA Current y-count register */ + unsigned short dummy9; + + unsigned long reserved3; +#endif + +}; + +struct dma_channel { + const char *device_id; + atomic_t chan_status; + volatile struct dma_register *regs; + struct dmasg *sg; /* large mode descriptor */ + unsigned int irq; + void *data; +#ifdef CONFIG_PM + unsigned short saved_peripheral_map; +#endif +}; + +#ifdef CONFIG_PM +int blackfin_dma_suspend(void); +void blackfin_dma_resume(void); +#endif + +/******************************************************************************* +* DMA API's +*******************************************************************************/ +extern struct dma_channel dma_ch[MAX_DMA_CHANNELS]; +extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS]; +extern int channel2irq(unsigned int channel); + +static inline void set_dma_start_addr(unsigned int channel, unsigned long addr) +{ + dma_ch[channel].regs->start_addr = addr; +} +static inline void set_dma_next_desc_addr(unsigned int channel, void *addr) +{ + dma_ch[channel].regs->next_desc_ptr = addr; +} +static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr) +{ + dma_ch[channel].regs->curr_desc_ptr = addr; +} +static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count) +{ + dma_ch[channel].regs->x_count = x_count; +} +static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count) +{ + dma_ch[channel].regs->y_count = y_count; +} +static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify) +{ + dma_ch[channel].regs->x_modify = x_modify; +} +static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify) +{ + dma_ch[channel].regs->y_modify = y_modify; +} +static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config) +{ + dma_ch[channel].regs->cfg = config; +} +static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr) +{ + dma_ch[channel].regs->curr_addr_ptr = addr; +} + +#ifdef CONFIG_BF60x +static inline unsigned long +set_bfin_dma_config2(char direction, char flow_mode, char intr_mode, + char dma_mode, char mem_width, char syncmode, char peri_width) +{ + unsigned long config = 0; + + switch (intr_mode) { + case INTR_ON_BUF: + if (dma_mode == DIMENSION_2D) + config = DI_EN_Y; + else + config = DI_EN_X; + break; + case INTR_ON_ROW: + config = DI_EN_X; + break; + case INTR_ON_PERI: + config = DI_EN_P; + break; + }; + + return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) | + (flow_mode << 12) | (syncmode << 2) | (peri_width << 4); +} +#endif + +static inline unsigned DMA_MMR_SIZE_TYPE +set_bfin_dma_config(char direction, char flow_mode, + char intr_mode, char dma_mode, char mem_width, char syncmode) +{ +#ifdef CONFIG_BF60x + return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode, + mem_width, syncmode, mem_width); +#else + return (direction << 1) | (mem_width << 2) | (dma_mode << 4) | + (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5); +#endif +} + +static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel) +{ + return dma_ch[channel].regs->irq_status; +} +static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel) +{ + return dma_ch[channel].regs->curr_x_count; +} +static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel) +{ + return dma_ch[channel].regs->curr_y_count; +} +static inline void *get_dma_next_desc_ptr(unsigned int channel) +{ + return dma_ch[channel].regs->next_desc_ptr; +} +static inline void *get_dma_curr_desc_ptr(unsigned int channel) +{ + return dma_ch[channel].regs->curr_desc_ptr; +} +static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel) +{ + return dma_ch[channel].regs->cfg; +} +static inline unsigned long get_dma_curr_addr(unsigned int channel) +{ + return dma_ch[channel].regs->curr_addr_ptr; +} + +static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize) +{ + /* Make sure the internal data buffers in the core are drained + * so that the DMA descriptors are completely written when the + * DMA engine goes to fetch them below. + */ + SSYNC(); + + dma_ch[channel].regs->next_desc_ptr = sg; + dma_ch[channel].regs->cfg = + (dma_ch[channel].regs->cfg & ~NDSIZE) | + ((ndsize << NDSIZE_OFFSET) & NDSIZE); +} + +static inline int dma_channel_active(unsigned int channel) +{ + return atomic_read(&dma_ch[channel].chan_status); +} + +static inline void disable_dma(unsigned int channel) +{ + dma_ch[channel].regs->cfg &= ~DMAEN; + SSYNC(); +} +static inline void enable_dma(unsigned int channel) +{ + dma_ch[channel].regs->curr_x_count = 0; + dma_ch[channel].regs->curr_y_count = 0; + dma_ch[channel].regs->cfg |= DMAEN; +} +int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data); + +static inline void dma_disable_irq(unsigned int channel) +{ + disable_irq(dma_ch[channel].irq); +} +static inline void dma_disable_irq_nosync(unsigned int channel) +{ + disable_irq_nosync(dma_ch[channel].irq); +} +static inline void dma_enable_irq(unsigned int channel) +{ + enable_irq(dma_ch[channel].irq); +} +static inline void clear_dma_irqstat(unsigned int channel) +{ + dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ; +} + +void *dma_memcpy(void *dest, const void *src, size_t count); +void *dma_memcpy_nocache(void *dest, const void *src, size_t count); +void *safe_dma_memcpy(void *dest, const void *src, size_t count); +void blackfin_dma_early_init(void); +void early_dma_memcpy(void *dest, const void *src, size_t count); +void early_dma_memcpy_done(void); + +#endif diff --git a/kernel/arch/blackfin/include/asm/dpmc.h b/kernel/arch/blackfin/include/asm/dpmc.h new file mode 100644 index 000000000..2673b1137 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/dpmc.h @@ -0,0 +1,794 @@ +/* + * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver + * + * Copyright (C) 2004-2009 Analog Device Inc. + * + * Licensed under the GPL-2 + */ + +#ifndef _BLACKFIN_DPMC_H_ +#define _BLACKFIN_DPMC_H_ + +#ifdef __ASSEMBLY__ +#define PM_REG0 R7 +#define PM_REG1 R6 +#define PM_REG2 R5 +#define PM_REG3 R4 +#define PM_REG4 R3 +#define PM_REG5 R2 +#define PM_REG6 R1 +#define PM_REG7 R0 +#define PM_REG8 P5 +#define PM_REG9 P4 +#define PM_REG10 P3 +#define PM_REG11 P2 +#define PM_REG12 P1 +#define PM_REG13 P0 + +#define PM_REGSET0 R7:7 +#define PM_REGSET1 R7:6 +#define PM_REGSET2 R7:5 +#define PM_REGSET3 R7:4 +#define PM_REGSET4 R7:3 +#define PM_REGSET5 R7:2 +#define PM_REGSET6 R7:1 +#define PM_REGSET7 R7:0 +#define PM_REGSET8 R7:0, P5:5 +#define PM_REGSET9 R7:0, P5:4 +#define PM_REGSET10 R7:0, P5:3 +#define PM_REGSET11 R7:0, P5:2 +#define PM_REGSET12 R7:0, P5:1 +#define PM_REGSET13 R7:0, P5:0 + +#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))]; +#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n; +#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n); +#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++]; +#define PM_PUSH(n, x) PM_REG##n = [FP++]; +#define PM_POP(n, x) [FP--] = PM_REG##n; +#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE) +#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE) +#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE) +#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE) +#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE) +#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE) + + .macro bfin_init_pm_bench_cycles +#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH + R4 = 0; + CYCLES = R4; + CYCLES2 = R4; + R4 = SYSCFG; + BITSET(R4, 1); + SYSCFG = R4; +#endif + .endm + + .macro bfin_cpu_reg_save + /* + * Save the core regs early so we can blow them away when + * saving/restoring MMR states + */ + [--sp] = (R7:0, P5:0); + [--sp] = fp; + [--sp] = usp; + + [--sp] = i0; + [--sp] = i1; + [--sp] = i2; + [--sp] = i3; + + [--sp] = m0; + [--sp] = m1; + [--sp] = m2; + [--sp] = m3; + + [--sp] = l0; + [--sp] = l1; + [--sp] = l2; + [--sp] = l3; + + [--sp] = b0; + [--sp] = b1; + [--sp] = b2; + [--sp] = b3; + [--sp] = a0.x; + [--sp] = a0.w; + [--sp] = a1.x; + [--sp] = a1.w; + + [--sp] = LC0; + [--sp] = LC1; + [--sp] = LT0; + [--sp] = LT1; + [--sp] = LB0; + [--sp] = LB1; + + /* We can't push RETI directly as that'll change IPEND[4] */ + r7 = RETI; + [--sp] = RETS; + [--sp] = ASTAT; +#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH + [--sp] = CYCLES; + [--sp] = CYCLES2; +#endif + [--sp] = SYSCFG; + [--sp] = RETX; + [--sp] = SEQSTAT; + [--sp] = r7; + + /* Save first func arg in M3 */ + M3 = R0; + .endm + + .macro bfin_cpu_reg_restore + /* Restore Core Registers */ + RETI = [sp++]; + SEQSTAT = [sp++]; + RETX = [sp++]; + SYSCFG = [sp++]; +#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH + CYCLES2 = [sp++]; + CYCLES = [sp++]; +#endif + ASTAT = [sp++]; + RETS = [sp++]; + + LB1 = [sp++]; + LB0 = [sp++]; + LT1 = [sp++]; + LT0 = [sp++]; + LC1 = [sp++]; + LC0 = [sp++]; + + a1.w = [sp++]; + a1.x = [sp++]; + a0.w = [sp++]; + a0.x = [sp++]; + b3 = [sp++]; + b2 = [sp++]; + b1 = [sp++]; + b0 = [sp++]; + + l3 = [sp++]; + l2 = [sp++]; + l1 = [sp++]; + l0 = [sp++]; + + m3 = [sp++]; + m2 = [sp++]; + m1 = [sp++]; + m0 = [sp++]; + + i3 = [sp++]; + i2 = [sp++]; + i1 = [sp++]; + i0 = [sp++]; + + usp = [sp++]; + fp = [sp++]; + (R7:0, P5:0) = [sp++]; + + .endm + + .macro bfin_sys_mmr_save + /* Save system MMRs */ + FP.H = hi(SYSMMR_BASE); + FP.L = lo(SYSMMR_BASE); +#ifdef SIC_IMASK0 + PM_SYS_PUSH(0, SIC_IMASK0) + PM_SYS_PUSH(1, SIC_IMASK1) +# ifdef SIC_IMASK2 + PM_SYS_PUSH(2, SIC_IMASK2) +# endif +#else +# ifdef SIC_IMASK + PM_SYS_PUSH(0, SIC_IMASK) +# endif +#endif + +#ifdef SIC_IAR0 + PM_SYS_PUSH(3, SIC_IAR0) + PM_SYS_PUSH(4, SIC_IAR1) + PM_SYS_PUSH(5, SIC_IAR2) +#endif +#ifdef SIC_IAR3 + PM_SYS_PUSH(6, SIC_IAR3) +#endif +#ifdef SIC_IAR4 + PM_SYS_PUSH(7, SIC_IAR4) + PM_SYS_PUSH(8, SIC_IAR5) + PM_SYS_PUSH(9, SIC_IAR6) +#endif +#ifdef SIC_IAR7 + PM_SYS_PUSH(10, SIC_IAR7) +#endif +#ifdef SIC_IAR8 + PM_SYS_PUSH(11, SIC_IAR8) + PM_SYS_PUSH(12, SIC_IAR9) + PM_SYS_PUSH(13, SIC_IAR10) +#endif + PM_PUSH_SYNC(13) +#ifdef SIC_IAR11 + PM_SYS_PUSH(0, SIC_IAR11) +#endif + +#ifdef SIC_IWR + PM_SYS_PUSH(1, SIC_IWR) +#endif +#ifdef SIC_IWR0 + PM_SYS_PUSH(1, SIC_IWR0) +#endif +#ifdef SIC_IWR1 + PM_SYS_PUSH(2, SIC_IWR1) +#endif +#ifdef SIC_IWR2 + PM_SYS_PUSH(3, SIC_IWR2) +#endif + +#ifdef PINT0_ASSIGN + PM_SYS_PUSH(4, PINT0_MASK_SET) + PM_SYS_PUSH(5, PINT1_MASK_SET) + PM_SYS_PUSH(6, PINT2_MASK_SET) + PM_SYS_PUSH(7, PINT3_MASK_SET) + PM_SYS_PUSH(8, PINT0_ASSIGN) + PM_SYS_PUSH(9, PINT1_ASSIGN) + PM_SYS_PUSH(10, PINT2_ASSIGN) + PM_SYS_PUSH(11, PINT3_ASSIGN) + PM_SYS_PUSH(12, PINT0_INVERT_SET) + PM_SYS_PUSH(13, PINT1_INVERT_SET) + PM_PUSH_SYNC(13) + PM_SYS_PUSH(0, PINT2_INVERT_SET) + PM_SYS_PUSH(1, PINT3_INVERT_SET) + PM_SYS_PUSH(2, PINT0_EDGE_SET) + PM_SYS_PUSH(3, PINT1_EDGE_SET) + PM_SYS_PUSH(4, PINT2_EDGE_SET) + PM_SYS_PUSH(5, PINT3_EDGE_SET) +#endif + +#ifdef SYSCR + PM_SYS_PUSH16(6, SYSCR) +#endif + +#ifdef EBIU_AMGCTL + PM_SYS_PUSH16(7, EBIU_AMGCTL) + PM_SYS_PUSH(8, EBIU_AMBCTL0) + PM_SYS_PUSH(9, EBIU_AMBCTL1) +#endif +#ifdef EBIU_FCTL + PM_SYS_PUSH(10, EBIU_MBSCTL) + PM_SYS_PUSH(11, EBIU_MODE) + PM_SYS_PUSH(12, EBIU_FCTL) + PM_PUSH_SYNC(12) +#else + PM_PUSH_SYNC(9) +#endif + .endm + + + .macro bfin_sys_mmr_restore +/* Restore System MMRs */ + FP.H = hi(SYSMMR_BASE); + FP.L = lo(SYSMMR_BASE); + +#ifdef EBIU_FCTL + PM_POP_SYNC(12) + PM_SYS_POP(12, EBIU_FCTL) + PM_SYS_POP(11, EBIU_MODE) + PM_SYS_POP(10, EBIU_MBSCTL) +#else + PM_POP_SYNC(9) +#endif + +#ifdef EBIU_AMGCTL + PM_SYS_POP(9, EBIU_AMBCTL1) + PM_SYS_POP(8, EBIU_AMBCTL0) + PM_SYS_POP16(7, EBIU_AMGCTL) +#endif + +#ifdef SYSCR + PM_SYS_POP16(6, SYSCR) +#endif + +#ifdef PINT0_ASSIGN + PM_SYS_POP(5, PINT3_EDGE_SET) + PM_SYS_POP(4, PINT2_EDGE_SET) + PM_SYS_POP(3, PINT1_EDGE_SET) + PM_SYS_POP(2, PINT0_EDGE_SET) + PM_SYS_POP(1, PINT3_INVERT_SET) + PM_SYS_POP(0, PINT2_INVERT_SET) + PM_POP_SYNC(13) + PM_SYS_POP(13, PINT1_INVERT_SET) + PM_SYS_POP(12, PINT0_INVERT_SET) + PM_SYS_POP(11, PINT3_ASSIGN) + PM_SYS_POP(10, PINT2_ASSIGN) + PM_SYS_POP(9, PINT1_ASSIGN) + PM_SYS_POP(8, PINT0_ASSIGN) + PM_SYS_POP(7, PINT3_MASK_SET) + PM_SYS_POP(6, PINT2_MASK_SET) + PM_SYS_POP(5, PINT1_MASK_SET) + PM_SYS_POP(4, PINT0_MASK_SET) +#endif + +#ifdef SIC_IWR2 + PM_SYS_POP(3, SIC_IWR2) +#endif +#ifdef SIC_IWR1 + PM_SYS_POP(2, SIC_IWR1) +#endif +#ifdef SIC_IWR0 + PM_SYS_POP(1, SIC_IWR0) +#endif +#ifdef SIC_IWR + PM_SYS_POP(1, SIC_IWR) +#endif + +#ifdef SIC_IAR11 + PM_SYS_POP(0, SIC_IAR11) +#endif + PM_POP_SYNC(13) +#ifdef SIC_IAR8 + PM_SYS_POP(13, SIC_IAR10) + PM_SYS_POP(12, SIC_IAR9) + PM_SYS_POP(11, SIC_IAR8) +#endif +#ifdef SIC_IAR7 + PM_SYS_POP(10, SIC_IAR7) +#endif +#ifdef SIC_IAR6 + PM_SYS_POP(9, SIC_IAR6) + PM_SYS_POP(8, SIC_IAR5) + PM_SYS_POP(7, SIC_IAR4) +#endif +#ifdef SIC_IAR3 + PM_SYS_POP(6, SIC_IAR3) +#endif +#ifdef SIC_IAR0 + PM_SYS_POP(5, SIC_IAR2) + PM_SYS_POP(4, SIC_IAR1) + PM_SYS_POP(3, SIC_IAR0) +#endif +#ifdef SIC_IMASK0 +# ifdef SIC_IMASK2 + PM_SYS_POP(2, SIC_IMASK2) +# endif + PM_SYS_POP(1, SIC_IMASK1) + PM_SYS_POP(0, SIC_IMASK0) +#else +# ifdef SIC_IMASK + PM_SYS_POP(0, SIC_IMASK) +# endif +#endif + .endm + + .macro bfin_core_mmr_save + /* Save Core MMRs */ + I0.H = hi(COREMMR_BASE); + I0.L = lo(COREMMR_BASE); + I1 = I0; + I2 = I0; + I3 = I0; + B0 = I0; + B1 = I0; + B2 = I0; + B3 = I0; + I1.L = lo(DCPLB_ADDR0); + I2.L = lo(DCPLB_DATA0); + I3.L = lo(ICPLB_ADDR0); + B0.L = lo(ICPLB_DATA0); + B1.L = lo(EVT2); + B2.L = lo(IMASK); + B3.L = lo(TCNTL); + + /* Event Vectors */ + FP = B1; + PM_PUSH(0, EVT2) + PM_PUSH(1, EVT3) + FP += 4; /* EVT4 */ + PM_PUSH(2, EVT5) + PM_PUSH(3, EVT6) + PM_PUSH(4, EVT7) + PM_PUSH(5, EVT8) + PM_PUSH_SYNC(5) + + PM_PUSH(0, EVT9) + PM_PUSH(1, EVT10) + PM_PUSH(2, EVT11) + PM_PUSH(3, EVT12) + PM_PUSH(4, EVT13) + PM_PUSH(5, EVT14) + PM_PUSH(6, EVT15) + + /* CEC */ + FP = B2; + PM_PUSH(7, IMASK) + FP += 4; /* IPEND */ + PM_PUSH(8, ILAT) + PM_PUSH(9, IPRIO) + + /* Core Timer */ + FP = B3; + PM_PUSH(10, TCNTL) + PM_PUSH(11, TPERIOD) + PM_PUSH(12, TSCALE) + PM_PUSH(13, TCOUNT) + PM_PUSH_SYNC(13) + + /* Misc non-contiguous registers */ + FP = I0; + PM_CORE_PUSH(0, DMEM_CONTROL); + PM_CORE_PUSH(1, IMEM_CONTROL); + PM_CORE_PUSH(2, TBUFCTL); + PM_PUSH_SYNC(2) + + /* DCPLB Addr */ + FP = I1; + PM_PUSH(0, DCPLB_ADDR0) + PM_PUSH(1, DCPLB_ADDR1) + PM_PUSH(2, DCPLB_ADDR2) + PM_PUSH(3, DCPLB_ADDR3) + PM_PUSH(4, DCPLB_ADDR4) + PM_PUSH(5, DCPLB_ADDR5) + PM_PUSH(6, DCPLB_ADDR6) + PM_PUSH(7, DCPLB_ADDR7) + PM_PUSH(8, DCPLB_ADDR8) + PM_PUSH(9, DCPLB_ADDR9) + PM_PUSH(10, DCPLB_ADDR10) + PM_PUSH(11, DCPLB_ADDR11) + PM_PUSH(12, DCPLB_ADDR12) + PM_PUSH(13, DCPLB_ADDR13) + PM_PUSH_SYNC(13) + PM_PUSH(0, DCPLB_ADDR14) + PM_PUSH(1, DCPLB_ADDR15) + + /* DCPLB Data */ + FP = I2; + PM_PUSH(2, DCPLB_DATA0) + PM_PUSH(3, DCPLB_DATA1) + PM_PUSH(4, DCPLB_DATA2) + PM_PUSH(5, DCPLB_DATA3) + PM_PUSH(6, DCPLB_DATA4) + PM_PUSH(7, DCPLB_DATA5) + PM_PUSH(8, DCPLB_DATA6) + PM_PUSH(9, DCPLB_DATA7) + PM_PUSH(10, DCPLB_DATA8) + PM_PUSH(11, DCPLB_DATA9) + PM_PUSH(12, DCPLB_DATA10) + PM_PUSH(13, DCPLB_DATA11) + PM_PUSH_SYNC(13) + PM_PUSH(0, DCPLB_DATA12) + PM_PUSH(1, DCPLB_DATA13) + PM_PUSH(2, DCPLB_DATA14) + PM_PUSH(3, DCPLB_DATA15) + + /* ICPLB Addr */ + FP = I3; + PM_PUSH(4, ICPLB_ADDR0) + PM_PUSH(5, ICPLB_ADDR1) + PM_PUSH(6, ICPLB_ADDR2) + PM_PUSH(7, ICPLB_ADDR3) + PM_PUSH(8, ICPLB_ADDR4) + PM_PUSH(9, ICPLB_ADDR5) + PM_PUSH(10, ICPLB_ADDR6) + PM_PUSH(11, ICPLB_ADDR7) + PM_PUSH(12, ICPLB_ADDR8) + PM_PUSH(13, ICPLB_ADDR9) + PM_PUSH_SYNC(13) + PM_PUSH(0, ICPLB_ADDR10) + PM_PUSH(1, ICPLB_ADDR11) + PM_PUSH(2, ICPLB_ADDR12) + PM_PUSH(3, ICPLB_ADDR13) + PM_PUSH(4, ICPLB_ADDR14) + PM_PUSH(5, ICPLB_ADDR15) + + /* ICPLB Data */ + FP = B0; + PM_PUSH(6, ICPLB_DATA0) + PM_PUSH(7, ICPLB_DATA1) + PM_PUSH(8, ICPLB_DATA2) + PM_PUSH(9, ICPLB_DATA3) + PM_PUSH(10, ICPLB_DATA4) + PM_PUSH(11, ICPLB_DATA5) + PM_PUSH(12, ICPLB_DATA6) + PM_PUSH(13, ICPLB_DATA7) + PM_PUSH_SYNC(13) + PM_PUSH(0, ICPLB_DATA8) + PM_PUSH(1, ICPLB_DATA9) + PM_PUSH(2, ICPLB_DATA10) + PM_PUSH(3, ICPLB_DATA11) + PM_PUSH(4, ICPLB_DATA12) + PM_PUSH(5, ICPLB_DATA13) + PM_PUSH(6, ICPLB_DATA14) + PM_PUSH(7, ICPLB_DATA15) + PM_PUSH_SYNC(7) + .endm + + .macro bfin_core_mmr_restore + /* Restore Core MMRs */ + I0.H = hi(COREMMR_BASE); + I0.L = lo(COREMMR_BASE); + I1 = I0; + I2 = I0; + I3 = I0; + B0 = I0; + B1 = I0; + B2 = I0; + B3 = I0; + I1.L = lo(DCPLB_ADDR15); + I2.L = lo(DCPLB_DATA15); + I3.L = lo(ICPLB_ADDR15); + B0.L = lo(ICPLB_DATA15); + B1.L = lo(EVT15); + B2.L = lo(IPRIO); + B3.L = lo(TCOUNT); + + /* ICPLB Data */ + FP = B0; + PM_POP_SYNC(7) + PM_POP(7, ICPLB_DATA15) + PM_POP(6, ICPLB_DATA14) + PM_POP(5, ICPLB_DATA13) + PM_POP(4, ICPLB_DATA12) + PM_POP(3, ICPLB_DATA11) + PM_POP(2, ICPLB_DATA10) + PM_POP(1, ICPLB_DATA9) + PM_POP(0, ICPLB_DATA8) + PM_POP_SYNC(13) + PM_POP(13, ICPLB_DATA7) + PM_POP(12, ICPLB_DATA6) + PM_POP(11, ICPLB_DATA5) + PM_POP(10, ICPLB_DATA4) + PM_POP(9, ICPLB_DATA3) + PM_POP(8, ICPLB_DATA2) + PM_POP(7, ICPLB_DATA1) + PM_POP(6, ICPLB_DATA0) + + /* ICPLB Addr */ + FP = I3; + PM_POP(5, ICPLB_ADDR15) + PM_POP(4, ICPLB_ADDR14) + PM_POP(3, ICPLB_ADDR13) + PM_POP(2, ICPLB_ADDR12) + PM_POP(1, ICPLB_ADDR11) + PM_POP(0, ICPLB_ADDR10) + PM_POP_SYNC(13) + PM_POP(13, ICPLB_ADDR9) + PM_POP(12, ICPLB_ADDR8) + PM_POP(11, ICPLB_ADDR7) + PM_POP(10, ICPLB_ADDR6) + PM_POP(9, ICPLB_ADDR5) + PM_POP(8, ICPLB_ADDR4) + PM_POP(7, ICPLB_ADDR3) + PM_POP(6, ICPLB_ADDR2) + PM_POP(5, ICPLB_ADDR1) + PM_POP(4, ICPLB_ADDR0) + + /* DCPLB Data */ + FP = I2; + PM_POP(3, DCPLB_DATA15) + PM_POP(2, DCPLB_DATA14) + PM_POP(1, DCPLB_DATA13) + PM_POP(0, DCPLB_DATA12) + PM_POP_SYNC(13) + PM_POP(13, DCPLB_DATA11) + PM_POP(12, DCPLB_DATA10) + PM_POP(11, DCPLB_DATA9) + PM_POP(10, DCPLB_DATA8) + PM_POP(9, DCPLB_DATA7) + PM_POP(8, DCPLB_DATA6) + PM_POP(7, DCPLB_DATA5) + PM_POP(6, DCPLB_DATA4) + PM_POP(5, DCPLB_DATA3) + PM_POP(4, DCPLB_DATA2) + PM_POP(3, DCPLB_DATA1) + PM_POP(2, DCPLB_DATA0) + + /* DCPLB Addr */ + FP = I1; + PM_POP(1, DCPLB_ADDR15) + PM_POP(0, DCPLB_ADDR14) + PM_POP_SYNC(13) + PM_POP(13, DCPLB_ADDR13) + PM_POP(12, DCPLB_ADDR12) + PM_POP(11, DCPLB_ADDR11) + PM_POP(10, DCPLB_ADDR10) + PM_POP(9, DCPLB_ADDR9) + PM_POP(8, DCPLB_ADDR8) + PM_POP(7, DCPLB_ADDR7) + PM_POP(6, DCPLB_ADDR6) + PM_POP(5, DCPLB_ADDR5) + PM_POP(4, DCPLB_ADDR4) + PM_POP(3, DCPLB_ADDR3) + PM_POP(2, DCPLB_ADDR2) + PM_POP(1, DCPLB_ADDR1) + PM_POP(0, DCPLB_ADDR0) + + + /* Misc non-contiguous registers */ + + /* icache & dcache will enable later + drop IMEM_CONTROL, DMEM_CONTROL pop + */ + FP = I0; + PM_POP_SYNC(2) + PM_CORE_POP(2, TBUFCTL) + PM_CORE_POP(1, IMEM_CONTROL) + PM_CORE_POP(0, DMEM_CONTROL) + + /* Core Timer */ + FP = B3; + R0 = 0x1; + [FP - 0xC] = R0; + + PM_POP_SYNC(13) + FP = B3; + PM_POP(13, TCOUNT) + PM_POP(12, TSCALE) + PM_POP(11, TPERIOD) + PM_POP(10, TCNTL) + + /* CEC */ + FP = B2; + PM_POP(9, IPRIO) + PM_POP(8, ILAT) + FP += -4; /* IPEND */ + PM_POP(7, IMASK) + + /* Event Vectors */ + FP = B1; + PM_POP(6, EVT15) + PM_POP(5, EVT14) + PM_POP(4, EVT13) + PM_POP(3, EVT12) + PM_POP(2, EVT11) + PM_POP(1, EVT10) + PM_POP(0, EVT9) + PM_POP_SYNC(5) + PM_POP(5, EVT8) + PM_POP(4, EVT7) + PM_POP(3, EVT6) + PM_POP(2, EVT5) + FP += -4; /* EVT4 */ + PM_POP(1, EVT3) + PM_POP(0, EVT2) + .endm +#endif + +#include <mach/pll.h> + +/* PLL_CTL Masks */ +#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ +#define PLL_OFF 0x0002 /* PLL Not Powered */ +#define STOPCK 0x0008 /* Core Clock Off */ +#define PDWN 0x0020 /* Enter Deep Sleep Mode */ +#ifdef __ADSPBF539__ +# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */ +# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */ +#else +# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ +# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ +#endif +#define BYPASS 0x0100 /* Bypass the PLL */ +#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ +#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */ +#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ + +/* PLL_DIV Masks */ +#define SSEL 0x000F /* System Select */ +#define CSEL 0x0030 /* Core Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ + +#define CCLK_DIV1 CSEL_DIV1 +#define CCLK_DIV2 CSEL_DIV2 +#define CCLK_DIV4 CSEL_DIV4 +#define CCLK_DIV8 CSEL_DIV8 + +#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ +#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ + +#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */ +#define CANWS 0x0800 /* CAN Wake-Up Status */ +#define USBWS 0x2000 /* USB Wake-Up Status */ +#define KPADWS 0x4000 /* Keypad Wake-Up Status */ +#define ROTWS 0x8000 /* Rotary Wake-Up Status */ +#define GPWS 0x1000 /* General-Purpose Wake-Up Status */ + +/* VR_CTL Masks */ +#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__) +#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ +#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */ +#else +#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ +#endif +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ + +#define GAIN 0x000C /* Voltage Level Gain */ +#define GAIN_5 0x0000 /* GAIN = 5 */ +#define GAIN_10 0x0004 /* GAIN = 1 */ +#define GAIN_20 0x0008 /* GAIN = 2 */ +#define GAIN_50 0x000C /* GAIN = 5 */ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#ifdef __ADSPBF52x__ +#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#else +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ +#endif + +#ifdef CONFIG_BF60x +#define PA15WE 0x00000001 /* Allow Wake-Up from PA15 */ +#define PB15WE 0x00000002 /* Allow Wake-Up from PB15 */ +#define PC15WE 0x00000004 /* Allow Wake-Up from PC15 */ +#define PD06WE 0x00000008 /* Allow Wake-Up from PD06(ETH0_PHYINT) */ +#define PE12WE 0x00000010 /* Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON) */ +#define PG04WE 0x00000020 /* Allow Wake-Up from PG04(CAN0_RX) */ +#define PG13WE 0x00000040 /* Allow Wake-Up from PG13 */ +#define USBWE 0x00000080 /* Allow Wake-Up from (USB) */ +#else +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ +#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ +#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */ +#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */ +#define KPADWE 0x1000 /* Keypad Wake-Up Enable */ +#define ROTWE 0x2000 /* Rotary Wake-Up Enable */ +#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ +#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ + +#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__) +#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ +#else +#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */ +#endif +#endif + +#ifndef __ASSEMBLY__ + +void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); +void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); +void do_hibernate(int wakeup); +void set_dram_srfs(void); +void unset_dram_srfs(void); + +#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16)) + +#ifdef CONFIG_CPU_FREQ +#define CPUFREQ_CPU 0 +#endif +struct bfin_dpmc_platform_data { + const unsigned int *tuple_tab; + unsigned short tabsize; + unsigned short vr_settling_time; /* in us */ +}; + +#endif + +#endif /*_BLACKFIN_DPMC_H_*/ diff --git a/kernel/arch/blackfin/include/asm/early_printk.h b/kernel/arch/blackfin/include/asm/early_printk.h new file mode 100644 index 000000000..68a910db8 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/early_printk.h @@ -0,0 +1,36 @@ +/* + * function prototpyes for early printk + * + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_EARLY_PRINTK_H__ +#define __ASM_EARLY_PRINTK_H__ + +#ifdef CONFIG_EARLY_PRINTK +/* For those that don't include it already */ +#include <linux/console.h> + +extern int setup_early_printk(char *); +extern void enable_shadow_console(void); +extern int shadow_console_enabled(void); +extern void mark_shadow_error(void); +extern void early_shadow_reg(unsigned long reg, unsigned int n); +extern void early_shadow_write(struct console *con, const char *s, + unsigned int n) __attribute__((nonnull(2))); +#define early_shadow_puts(str) early_shadow_write(NULL, str, strlen(str)) +#define early_shadow_stamp() \ + do { \ + early_shadow_puts(__FILE__ " : " __stringify(__LINE__) " ["); \ + early_shadow_puts(__func__); \ + early_shadow_puts("]\n"); \ + } while (0) +#else +#define setup_early_printk(fmt) do { } while (0) +#define enable_shadow_console(fmt) do { } while (0) +#define early_shadow_stamp() do { } while (0) +#endif /* CONFIG_EARLY_PRINTK */ + +#endif /* __ASM_EARLY_PRINTK_H__ */ diff --git a/kernel/arch/blackfin/include/asm/elf.h b/kernel/arch/blackfin/include/asm/elf.h new file mode 100644 index 000000000..d15cb9b5d --- /dev/null +++ b/kernel/arch/blackfin/include/asm/elf.h @@ -0,0 +1,135 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASMBFIN_ELF_H +#define __ASMBFIN_ELF_H + +/* + * ELF register definitions.. + */ + +#include <asm/ptrace.h> +#include <asm/user.h> + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_BFIN_PIC 0x00000001 /* -fpic */ +#define EF_BFIN_FDPIC 0x00000002 /* -mfdpic */ +#define EF_BFIN_CODE_IN_L1 0x00000010 /* --code-in-l1 */ +#define EF_BFIN_DATA_IN_L1 0x00000020 /* --data-in-l1 */ +#define EF_BFIN_CODE_IN_L2 0x00000040 /* --code-in-l2 */ +#define EF_BFIN_DATA_IN_L2 0x00000080 /* --data-in-l2 */ + +#if 1 /* core dumps not supported, but linux/elfcore.h needs these */ +typedef unsigned long elf_greg_t; + +#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t)) +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +typedef struct { } elf_fpregset_t; +#endif + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN) + +#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */) +#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC) + +/* EM_BLACKFIN defined in linux/elf.h */ + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS32 +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_BLACKFIN + +#define ELF_PLAT_INIT(_r) _r->p1 = 0 + +#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr) \ +do { \ + _regs->r7 = 0; \ + _regs->p0 = _exec_map_addr; \ + _regs->p1 = _interp_map_addr; \ + _regs->p2 = _dynamic_addr; \ +} while(0) + +#if 0 +#define CORE_DUMP_USE_REGSET +#endif +#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC +#define ELF_EXEC_PAGESIZE 4096 + +#define R_BFIN_UNUSED0 0 /* relocation type 0 is not defined */ +#define R_BFIN_PCREL5M2 1 /* LSETUP part a */ +#define R_BFIN_UNUSED1 2 /* relocation type 2 is not defined */ +#define R_BFIN_PCREL10 3 /* type 3, if cc jump <target> */ +#define R_BFIN_PCREL12_JUMP 4 /* type 4, jump <target> */ +#define R_BFIN_RIMM16 5 /* type 0x5, rN = <target> */ +#define R_BFIN_LUIMM16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */ +#define R_BFIN_HUIMM16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */ +#define R_BFIN_PCREL12_JUMP_S 8 /* # 0x8 jump.s <target> */ +#define R_BFIN_PCREL24_JUMP_X 9 /* # 0x9 jump.x <target> */ +#define R_BFIN_PCREL24 10 /* # 0xa call <target> , not expandable */ +#define R_BFIN_UNUSEDB 11 /* # 0xb not generated */ +#define R_BFIN_UNUSEDC 12 /* # 0xc not used */ +#define R_BFIN_PCREL24_JUMP_L 13 /* 0xd jump.l <target> */ +#define R_BFIN_PCREL24_CALL_X 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */ +#define R_BFIN_VAR_EQ_SYMB 15 /* 0xf, linker should treat it same as 0x12 */ +#define R_BFIN_BYTE_DATA 16 /* 0x10, .byte var = symbol */ +#define R_BFIN_BYTE2_DATA 17 /* 0x11, .byte2 var = symbol */ +#define R_BFIN_BYTE4_DATA 18 /* 0x12, .byte4 var = symbol and .var var=symbol */ +#define R_BFIN_PCREL11 19 /* 0x13, lsetup part b */ +#define R_BFIN_UNUSED14 20 /* 0x14, undefined */ +#define R_BFIN_UNUSED15 21 /* not generated by VDSP 3.5 */ + +/* arithmetic relocations */ +#define R_BFIN_PUSH 0xE0 +#define R_BFIN_CONST 0xE1 +#define R_BFIN_ADD 0xE2 +#define R_BFIN_SUB 0xE3 +#define R_BFIN_MULT 0xE4 +#define R_BFIN_DIV 0xE5 +#define R_BFIN_MOD 0xE6 +#define R_BFIN_LSHIFT 0xE7 +#define R_BFIN_RSHIFT 0xE8 +#define R_BFIN_AND 0xE9 +#define R_BFIN_OR 0xEA +#define R_BFIN_XOR 0xEB +#define R_BFIN_LAND 0xEC +#define R_BFIN_LOR 0xED +#define R_BFIN_LEN 0xEE +#define R_BFIN_NEG 0xEF +#define R_BFIN_COMP 0xF0 +#define R_BFIN_PAGE 0xF1 +#define R_BFIN_HWPAGE 0xF2 +#define R_BFIN_ADDR 0xF3 + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE 0xD0000000UL + +#define ELF_CORE_COPY_REGS(pr_reg, regs) \ + memcpy((char *) &pr_reg, (char *)regs, \ + sizeof(struct pt_regs)); +#define ELF_CORE_COPY_FPREGS(...) 0 /* Blackfin has no FPU */ + +/* This yields a mask that user programs can use to figure out what + instruction set this cpu supports. */ + +#define ELF_HWCAP (0) + +/* This yields a string that ld.so will use to load implementation + specific libraries for optimization. This is more specific in + intent than poking at uname or /proc/cpuinfo. */ + +#define ELF_PLATFORM (NULL) + +#endif diff --git a/kernel/arch/blackfin/include/asm/entry.h b/kernel/arch/blackfin/include/asm/entry.h new file mode 100644 index 000000000..4104d5783 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/entry.h @@ -0,0 +1,178 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_ENTRY_H +#define __BFIN_ENTRY_H + +#include <asm/setup.h> +#include <asm/page.h> + +#ifdef __ASSEMBLY__ + +#define LFLUSH_I_AND_D 0x00000808 +#define LSIGTRAP 5 + +/* + * NOTE! The single-stepping code assumes that all interrupt handlers + * start by saving SYSCFG on the stack with their first instruction. + */ + +/* This one is used for exceptions, emulation, and NMI. It doesn't push + RETI and doesn't do cli. */ +#define SAVE_ALL_SYS save_context_no_interrupts +/* This is used for all normal interrupts. It saves a minimum of registers + to the stack, loads the IRQ number, and jumps to common code. */ +#ifdef CONFIG_IPIPE +# define LOAD_IPIPE_IPEND \ + P0.l = lo(IPEND); \ + P0.h = hi(IPEND); \ + R1 = [P0]; +#else +# define LOAD_IPIPE_IPEND +#endif + +/* + * Workaround for anomalies 05000283 and 05000315 + */ +#if ANOMALY_05000283 || ANOMALY_05000315 +# define ANOMALY_283_315_WORKAROUND(preg, dreg) \ + cc = dreg == dreg; \ + preg.h = HI(CHIPID); \ + preg.l = LO(CHIPID); \ + if cc jump 1f; \ + dreg.l = W[preg]; \ +1: +#else +# define ANOMALY_283_315_WORKAROUND(preg, dreg) +#endif /* ANOMALY_05000283 || ANOMALY_05000315 */ + +#ifndef CONFIG_EXACT_HWERR +/* As a debugging aid - we save IPEND when DEBUG_KERNEL is on, + * otherwise it is a waste of cycles. + */ +# ifndef CONFIG_DEBUG_KERNEL +#define INTERRUPT_ENTRY(N) \ + [--sp] = SYSCFG; \ + [--sp] = P0; /*orig_p0*/ \ + [--sp] = R0; /*orig_r0*/ \ + [--sp] = (R7:0,P5:0); \ + R0 = (N); \ + LOAD_IPIPE_IPEND \ + jump __common_int_entry; +# else /* CONFIG_DEBUG_KERNEL */ +#define INTERRUPT_ENTRY(N) \ + [--sp] = SYSCFG; \ + [--sp] = P0; /*orig_p0*/ \ + [--sp] = R0; /*orig_r0*/ \ + [--sp] = (R7:0,P5:0); \ + p0.l = lo(IPEND); \ + p0.h = hi(IPEND); \ + r1 = [p0]; \ + R0 = (N); \ + LOAD_IPIPE_IPEND \ + jump __common_int_entry; +# endif /* CONFIG_DEBUG_KERNEL */ + +/* For timer interrupts, we need to save IPEND, since the user_mode + *macro accesses it to determine where to account time. + */ +#define TIMER_INTERRUPT_ENTRY(N) \ + [--sp] = SYSCFG; \ + [--sp] = P0; /*orig_p0*/ \ + [--sp] = R0; /*orig_r0*/ \ + [--sp] = (R7:0,P5:0); \ + p0.l = lo(IPEND); \ + p0.h = hi(IPEND); \ + r1 = [p0]; \ + R0 = (N); \ + jump __common_int_entry; +#else /* CONFIG_EXACT_HWERR is defined */ + +/* if we want hardware error to be exact, we need to do a SSYNC (which forces + * read/writes to complete to the memory controllers), and check to see that + * caused a pending HW error condition. If so, we assume it was caused by user + * space, by setting the same interrupt that we are in (so it goes off again) + * and context restore, and a RTI (without servicing anything). This should + * cause the pending HWERR to fire, and when that is done, this interrupt will + * be re-serviced properly. + * As you can see by the code - we actually need to do two SSYNCS - one to + * make sure the read/writes complete, and another to make sure the hardware + * error is recognized by the core. + * + * The extra nop before the SSYNC is to make sure we work around 05000244, + * since the 283/315 workaround includes a branch to the end + */ +#define INTERRUPT_ENTRY(N) \ + [--sp] = SYSCFG; \ + [--sp] = P0; /*orig_p0*/ \ + [--sp] = R0; /*orig_r0*/ \ + [--sp] = (R7:0,P5:0); \ + R1 = ASTAT; \ + ANOMALY_283_315_WORKAROUND(p0, r0) \ + P0.L = LO(ILAT); \ + P0.H = HI(ILAT); \ + NOP; \ + SSYNC; \ + SSYNC; \ + R0 = [P0]; \ + CC = BITTST(R0, EVT_IVHW_P); \ + IF CC JUMP 1f; \ + ASTAT = R1; \ + p0.l = lo(IPEND); \ + p0.h = hi(IPEND); \ + r1 = [p0]; \ + R0 = (N); \ + LOAD_IPIPE_IPEND \ + jump __common_int_entry; \ +1: ASTAT = R1; \ + RAISE N; \ + (R7:0, P5:0) = [SP++]; \ + SP += 0x8; \ + SYSCFG = [SP++]; \ + CSYNC; \ + RTI; + +#define TIMER_INTERRUPT_ENTRY(N) \ + [--sp] = SYSCFG; \ + [--sp] = P0; /*orig_p0*/ \ + [--sp] = R0; /*orig_r0*/ \ + [--sp] = (R7:0,P5:0); \ + R1 = ASTAT; \ + ANOMALY_283_315_WORKAROUND(p0, r0) \ + P0.L = LO(ILAT); \ + P0.H = HI(ILAT); \ + NOP; \ + SSYNC; \ + SSYNC; \ + R0 = [P0]; \ + CC = BITTST(R0, EVT_IVHW_P); \ + IF CC JUMP 1f; \ + ASTAT = R1; \ + p0.l = lo(IPEND); \ + p0.h = hi(IPEND); \ + r1 = [p0]; \ + R0 = (N); \ + jump __common_int_entry; \ +1: ASTAT = R1; \ + RAISE N; \ + (R7:0, P5:0) = [SP++]; \ + SP += 0x8; \ + SYSCFG = [SP++]; \ + CSYNC; \ + RTI; +#endif /* CONFIG_EXACT_HWERR */ + +/* This one pushes RETI without using CLI. Interrupts are enabled. */ +#define SAVE_CONTEXT_SYSCALL save_context_syscall +#define SAVE_CONTEXT save_context_with_interrupts +#define SAVE_CONTEXT_CPLB save_context_cplb + +#define RESTORE_ALL_SYS restore_context_no_interrupts +#define RESTORE_CONTEXT restore_context_with_interrupts +#define RESTORE_CONTEXT_CPLB restore_context_cplb + +#endif /* __ASSEMBLY__ */ +#endif /* __BFIN_ENTRY_H */ diff --git a/kernel/arch/blackfin/include/asm/exec.h b/kernel/arch/blackfin/include/asm/exec.h new file mode 100644 index 000000000..54c2e1db2 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/exec.h @@ -0,0 +1 @@ +/* define arch_align_stack() here */ diff --git a/kernel/arch/blackfin/include/asm/fixed_code.h b/kernel/arch/blackfin/include/asm/fixed_code.h new file mode 100644 index 000000000..bc330f062 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/fixed_code.h @@ -0,0 +1,30 @@ +/* + * This file defines the fixed addresses where userspace programs + * can find atomic code sequences. + * + * Copyright 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ +#ifndef __BFIN_ASM_FIXED_CODE_H__ +#define __BFIN_ASM_FIXED_CODE_H__ + +#include <uapi/asm/fixed_code.h> + +#ifndef __ASSEMBLY__ +#include <linux/linkage.h> +#include <linux/ptrace.h> +extern asmlinkage void finish_atomic_sections(struct pt_regs *regs); +extern char fixed_code_start; +extern char fixed_code_end; +extern int atomic_xchg32(void); +extern int atomic_cas32(void); +extern int atomic_add32(void); +extern int atomic_sub32(void); +extern int atomic_ior32(void); +extern int atomic_and32(void); +extern int atomic_xor32(void); +extern void safe_user_instruction(void); +extern void sigreturn_stub(void); +#endif +#endif diff --git a/kernel/arch/blackfin/include/asm/flat.h b/kernel/arch/blackfin/include/asm/flat.h new file mode 100644 index 000000000..c1314c56d --- /dev/null +++ b/kernel/arch/blackfin/include/asm/flat.h @@ -0,0 +1,58 @@ +/* + * uClinux flat-format executables + * + * Copyright 2003-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 + */ + +#ifndef __BLACKFIN_FLAT_H__ +#define __BLACKFIN_FLAT_H__ + +#include <asm/unaligned.h> + +#define flat_argvp_envp_on_stack() 0 +#define flat_old_ram_flag(flags) (flags) + +extern unsigned long bfin_get_addr_from_rp (unsigned long *ptr, + unsigned long relval, + unsigned long flags, + unsigned long *persistent); + +extern void bfin_put_addr_at_rp(unsigned long *ptr, unsigned long addr, + unsigned long relval); + +/* The amount by which a relocation can exceed the program image limits + without being regarded as an error. */ + +#define flat_reloc_valid(reloc, size) ((reloc) <= (size)) + +#define flat_get_addr_from_rp(rp, relval, flags, persistent) \ + bfin_get_addr_from_rp(rp, relval, flags, persistent) +#define flat_put_addr_at_rp(rp, val, relval) \ + bfin_put_addr_at_rp(rp, val, relval) + +/* Convert a relocation entry into an address. */ +static inline unsigned long +flat_get_relocate_addr (unsigned long relval) +{ + return relval & 0x03ffffff; /* Mask out top 6 bits */ +} + +static inline int flat_set_persistent(unsigned long relval, + unsigned long *persistent) +{ + int type = (relval >> 26) & 7; + if (type == 3) { + *persistent = relval << 16; + return 1; + } + return 0; +} + +static inline int flat_addr_absolute(unsigned long relval) +{ + return (relval & (1 << 29)) != 0; +} + +#endif /* __BLACKFIN_FLAT_H__ */ diff --git a/kernel/arch/blackfin/include/asm/ftrace.h b/kernel/arch/blackfin/include/asm/ftrace.h new file mode 100644 index 000000000..2f1c3c265 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/ftrace.h @@ -0,0 +1,73 @@ +/* + * Blackfin ftrace code + * + * Copyright 2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BFIN_FTRACE_H__ +#define __ASM_BFIN_FTRACE_H__ + +#define MCOUNT_INSN_SIZE 6 /* sizeof "[++sp] = rets; call __mcount;" */ + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_DYNAMIC_FTRACE + +extern void _mcount(void); +#define MCOUNT_ADDR ((unsigned long)_mcount) + +static inline unsigned long ftrace_call_adjust(unsigned long addr) +{ + return addr; +} + +struct dyn_arch_ftrace { + /* No extra data needed for Blackfin */ +}; + +#endif + +#ifdef CONFIG_FRAME_POINTER +#include <linux/mm.h> + +extern inline void *return_address(unsigned int level) +{ + unsigned long *endstack, *fp, *ret_addr; + unsigned int current_level = 0; + + if (level == 0) + return __builtin_return_address(0); + + fp = (unsigned long *)__builtin_frame_address(0); + endstack = (unsigned long *)PAGE_ALIGN((unsigned long)&level); + + while (((unsigned long)fp & 0x3) == 0 && fp && + (fp + 1) < endstack && current_level < level) { + fp = (unsigned long *)*fp; + current_level++; + } + + if (((unsigned long)fp & 0x3) == 0 && fp && + (fp + 1) < endstack) + ret_addr = (unsigned long *)*(fp + 1); + else + ret_addr = NULL; + + return ret_addr; +} + +#else + +extern inline void *return_address(unsigned int level) +{ + return NULL; +} + +#endif /* CONFIG_FRAME_POINTER */ + +#define ftrace_return_address(n) return_address(n) + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/kernel/arch/blackfin/include/asm/gpio.h b/kernel/arch/blackfin/include/asm/gpio.h new file mode 100644 index 000000000..99d338ca2 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/gpio.h @@ -0,0 +1,214 @@ +/* + * Copyright 2006-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ARCH_BLACKFIN_GPIO_H__ +#define __ARCH_BLACKFIN_GPIO_H__ + +#define gpio_bank(x) ((x) >> 4) +#define gpio_bit(x) (1<<((x) & 0xF)) +#define gpio_sub_n(x) ((x) & 0xF) + +#define GPIO_BANKSIZE 16 +#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE) + +#include <mach/gpio.h> + +#define PERIPHERAL_USAGE 1 +#define GPIO_USAGE 0 + +#ifndef BFIN_GPIO_PINT +# define BFIN_GPIO_PINT 0 +#endif + +#ifndef __ASSEMBLY__ + +#ifndef CONFIG_PINCTRL + +#include <linux/compiler.h> +#include <asm/blackfin.h> +#include <asm/portmux.h> +#include <asm/irq_handler.h> + +/*********************************************************** +* +* FUNCTIONS: Blackfin General Purpose Ports Access Functions +* +* INPUTS/OUTPUTS: +* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS +* +* +* DESCRIPTION: These functions abstract direct register access +* to Blackfin processor General Purpose +* Ports Regsiters +* +* CAUTION: These functions do not belong to the GPIO Driver API +************************************************************* +* MODIFICATION HISTORY : +**************************************************************/ + +void set_gpio_dir(unsigned, unsigned short); +void set_gpio_inen(unsigned, unsigned short); +void set_gpio_polar(unsigned, unsigned short); +void set_gpio_edge(unsigned, unsigned short); +void set_gpio_both(unsigned, unsigned short); +void set_gpio_data(unsigned, unsigned short); +void set_gpio_maska(unsigned, unsigned short); +void set_gpio_maskb(unsigned, unsigned short); +void set_gpio_toggle(unsigned); +void set_gpiop_dir(unsigned, unsigned short); +void set_gpiop_inen(unsigned, unsigned short); +void set_gpiop_polar(unsigned, unsigned short); +void set_gpiop_edge(unsigned, unsigned short); +void set_gpiop_both(unsigned, unsigned short); +void set_gpiop_data(unsigned, unsigned short); +void set_gpiop_maska(unsigned, unsigned short); +void set_gpiop_maskb(unsigned, unsigned short); +unsigned short get_gpio_dir(unsigned); +unsigned short get_gpio_inen(unsigned); +unsigned short get_gpio_polar(unsigned); +unsigned short get_gpio_edge(unsigned); +unsigned short get_gpio_both(unsigned); +unsigned short get_gpio_maska(unsigned); +unsigned short get_gpio_maskb(unsigned); +unsigned short get_gpio_data(unsigned); +unsigned short get_gpiop_dir(unsigned); +unsigned short get_gpiop_inen(unsigned); +unsigned short get_gpiop_polar(unsigned); +unsigned short get_gpiop_edge(unsigned); +unsigned short get_gpiop_both(unsigned); +unsigned short get_gpiop_maska(unsigned); +unsigned short get_gpiop_maskb(unsigned); +unsigned short get_gpiop_data(unsigned); + +struct gpio_port_t { + unsigned short data; + unsigned short dummy1; + unsigned short data_clear; + unsigned short dummy2; + unsigned short data_set; + unsigned short dummy3; + unsigned short toggle; + unsigned short dummy4; + unsigned short maska; + unsigned short dummy5; + unsigned short maska_clear; + unsigned short dummy6; + unsigned short maska_set; + unsigned short dummy7; + unsigned short maska_toggle; + unsigned short dummy8; + unsigned short maskb; + unsigned short dummy9; + unsigned short maskb_clear; + unsigned short dummy10; + unsigned short maskb_set; + unsigned short dummy11; + unsigned short maskb_toggle; + unsigned short dummy12; + unsigned short dir; + unsigned short dummy13; + unsigned short polar; + unsigned short dummy14; + unsigned short edge; + unsigned short dummy15; + unsigned short both; + unsigned short dummy16; + unsigned short inen; +}; + +#ifdef BFIN_SPECIAL_GPIO_BANKS +void bfin_special_gpio_free(unsigned gpio); +int bfin_special_gpio_request(unsigned gpio, const char *label); +# ifdef CONFIG_PM +void bfin_special_gpio_pm_hibernate_restore(void); +void bfin_special_gpio_pm_hibernate_suspend(void); +# endif +#endif + +#ifdef CONFIG_PM +void bfin_gpio_pm_hibernate_restore(void); +void bfin_gpio_pm_hibernate_suspend(void); +int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl); +int bfin_gpio_pm_standby_ctrl(unsigned ctrl); + +static inline int bfin_pm_standby_setup(void) +{ + return bfin_gpio_pm_standby_ctrl(1); +} + +static inline void bfin_pm_standby_restore(void) +{ + bfin_gpio_pm_standby_ctrl(0); +} + + +struct gpio_port_s { + unsigned short data; + unsigned short maska; + unsigned short maskb; + unsigned short dir; + unsigned short polar; + unsigned short edge; + unsigned short both; + unsigned short inen; + + unsigned short fer; + unsigned short reserved; + unsigned short mux; +}; +#endif /*CONFIG_PM*/ + +/*********************************************************** +* +* FUNCTIONS: Blackfin GPIO Driver +* +* INPUTS/OUTPUTS: +* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS +* +* +* DESCRIPTION: Blackfin GPIO Driver API +* +* CAUTION: +************************************************************* +* MODIFICATION HISTORY : +**************************************************************/ +int bfin_gpio_irq_request(unsigned gpio, const char *label); +void bfin_gpio_irq_free(unsigned gpio); +void bfin_gpio_irq_prepare(unsigned gpio); + +static inline int irq_to_gpio(unsigned irq) +{ + return irq - GPIO_IRQ_BASE; +} +#endif /* CONFIG_PINCTRL */ + +#include <asm/irq.h> +#include <asm/errno.h> + +#include <asm-generic/gpio.h> /* cansleep wrappers */ + +static inline int gpio_get_value(unsigned int gpio) +{ + return __gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned int gpio, int value) +{ + __gpio_set_value(gpio, value); +} + +static inline int gpio_cansleep(unsigned int gpio) +{ + return __gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return __gpio_to_irq(gpio); +} +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_BLACKFIN_GPIO_H__ */ diff --git a/kernel/arch/blackfin/include/asm/gptimers.h b/kernel/arch/blackfin/include/asm/gptimers.h new file mode 100644 index 000000000..381e3d621 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/gptimers.h @@ -0,0 +1,337 @@ +/* + * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * Copyright (C) 2005 John DeHority + * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de) + * + * Licensed under the GPL-2. + */ + +#ifndef _BLACKFIN_TIMERS_H_ +#define _BLACKFIN_TIMERS_H_ + +#include <linux/types.h> +#include <asm/blackfin.h> + +/* + * BF51x/BF52x/BF537: 8 timers: + */ +#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || defined(BF537_FAMILY) +# define MAX_BLACKFIN_GPTIMERS 8 +# define TIMER0_GROUP_REG TIMER_ENABLE +#endif +/* + * BF54x: 11 timers (BF542: 8 timers): + */ +#if defined(CONFIG_BF54x) +# ifdef CONFIG_BF542 +# define MAX_BLACKFIN_GPTIMERS 8 +# else +# define MAX_BLACKFIN_GPTIMERS 11 +# define TIMER8_GROUP_REG TIMER_ENABLE1 +# define TIMER_GROUP2 1 +# endif +# define TIMER0_GROUP_REG TIMER_ENABLE0 +#endif +/* + * BF561: 12 timers: + */ +#if defined(CONFIG_BF561) +# define MAX_BLACKFIN_GPTIMERS 12 +# define TIMER0_GROUP_REG TMRS8_ENABLE +# define TIMER8_GROUP_REG TMRS4_ENABLE +# define TIMER_GROUP2 1 +#endif +/* + * BF609: 8 timers: + */ +#if defined(CONFIG_BF60x) +# define MAX_BLACKFIN_GPTIMERS 8 +# define TIMER0_GROUP_REG TIMER_RUN +#endif +/* + * All others: 3 timers: + */ +#define TIMER_GROUP1 0 +#if !defined(MAX_BLACKFIN_GPTIMERS) +# define MAX_BLACKFIN_GPTIMERS 3 +# define TIMER0_GROUP_REG TIMER_ENABLE +#endif + +#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1) +#define BFIN_TIMER_OCTET(x) ((x) >> 3) + +/* used in masks for timer_enable() and timer_disable() */ +#define TIMER0bit 0x0001 /* 0001b */ +#define TIMER1bit 0x0002 /* 0010b */ +#define TIMER2bit 0x0004 /* 0100b */ +#define TIMER3bit 0x0008 +#define TIMER4bit 0x0010 +#define TIMER5bit 0x0020 +#define TIMER6bit 0x0040 +#define TIMER7bit 0x0080 +#define TIMER8bit 0x0100 +#define TIMER9bit 0x0200 +#define TIMER10bit 0x0400 +#define TIMER11bit 0x0800 + +#define TIMER0_id 0 +#define TIMER1_id 1 +#define TIMER2_id 2 +#define TIMER3_id 3 +#define TIMER4_id 4 +#define TIMER5_id 5 +#define TIMER6_id 6 +#define TIMER7_id 7 +#define TIMER8_id 8 +#define TIMER9_id 9 +#define TIMER10_id 10 +#define TIMER11_id 11 + +/* associated timers for ppi framesync: */ + +#if defined(CONFIG_BF561) +# define FS0_1_TIMER_ID TIMER8_id +# define FS0_2_TIMER_ID TIMER9_id +# define FS1_1_TIMER_ID TIMER10_id +# define FS1_2_TIMER_ID TIMER11_id +# define FS0_1_TIMER_BIT TIMER8bit +# define FS0_2_TIMER_BIT TIMER9bit +# define FS1_1_TIMER_BIT TIMER10bit +# define FS1_2_TIMER_BIT TIMER11bit +# undef FS1_TIMER_ID +# undef FS2_TIMER_ID +# undef FS1_TIMER_BIT +# undef FS2_TIMER_BIT +#else +# define FS1_TIMER_ID TIMER0_id +# define FS2_TIMER_ID TIMER1_id +# define FS1_TIMER_BIT TIMER0bit +# define FS2_TIMER_BIT TIMER1bit +#endif + +#ifdef CONFIG_BF60x +/* + * Timer Configuration Register Bits + */ +#define TIMER_EMU_RUN 0x8000 +#define TIMER_BPER_EN 0x4000 +#define TIMER_BWID_EN 0x2000 +#define TIMER_BDLY_EN 0x1000 +#define TIMER_OUT_DIS 0x0800 +#define TIMER_TIN_SEL 0x0400 +#define TIMER_CLK_SEL 0x0300 +#define TIMER_CLK_SCLK 0x0000 +#define TIMER_CLK_ALT_CLK0 0x0100 +#define TIMER_CLK_ALT_CLK1 0x0300 +#define TIMER_PULSE_HI 0x0080 +#define TIMER_SLAVE_TRIG 0x0040 +#define TIMER_IRQ_MODE 0x0030 +#define TIMER_IRQ_ACT_EDGE 0x0000 +#define TIMER_IRQ_DLY 0x0010 +#define TIMER_IRQ_WID_DLY 0x0020 +#define TIMER_IRQ_PER 0x0030 +#define TIMER_MODE 0x000f +#define TIMER_MODE_WDOG_P 0x0008 +#define TIMER_MODE_WDOG_W 0x0009 +#define TIMER_MODE_PWM_CONT 0x000c +#define TIMER_MODE_PWM 0x000d +#define TIMER_MODE_WDTH 0x000a +#define TIMER_MODE_WDTH_D 0x000b +#define TIMER_MODE_EXT_CLK 0x000e +#define TIMER_MODE_PININT 0x000f + +/* + * Timer Status Register Bits + */ +#define TIMER_STATUS_TIMIL0 0x0001 +#define TIMER_STATUS_TIMIL1 0x0002 +#define TIMER_STATUS_TIMIL2 0x0004 +#define TIMER_STATUS_TIMIL3 0x0008 +#define TIMER_STATUS_TIMIL4 0x0010 +#define TIMER_STATUS_TIMIL5 0x0020 +#define TIMER_STATUS_TIMIL6 0x0040 +#define TIMER_STATUS_TIMIL7 0x0080 + +#define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */ +#define TIMER_STATUS_TOVF1 0x0002 +#define TIMER_STATUS_TOVF2 0x0004 +#define TIMER_STATUS_TOVF3 0x0008 +#define TIMER_STATUS_TOVF4 0x0010 +#define TIMER_STATUS_TOVF5 0x0020 +#define TIMER_STATUS_TOVF6 0x0040 +#define TIMER_STATUS_TOVF7 0x0080 + +/* + * Timer Slave Enable Status : write 1 to clear + */ +#define TIMER_STATUS_TRUN0 0x0001 +#define TIMER_STATUS_TRUN1 0x0002 +#define TIMER_STATUS_TRUN2 0x0004 +#define TIMER_STATUS_TRUN3 0x0008 +#define TIMER_STATUS_TRUN4 0x0010 +#define TIMER_STATUS_TRUN5 0x0020 +#define TIMER_STATUS_TRUN6 0x0040 +#define TIMER_STATUS_TRUN7 0x0080 + +#else + +/* + * Timer Configuration Register Bits + */ +#define TIMER_ERR 0xC000 +#define TIMER_ERR_OVFL 0x4000 +#define TIMER_ERR_PROG_PER 0x8000 +#define TIMER_ERR_PROG_PW 0xC000 +#define TIMER_EMU_RUN 0x0200 +#define TIMER_TOGGLE_HI 0x0100 +#define TIMER_CLK_SEL 0x0080 +#define TIMER_OUT_DIS 0x0040 +#define TIMER_TIN_SEL 0x0020 +#define TIMER_IRQ_ENA 0x0010 +#define TIMER_PERIOD_CNT 0x0008 +#define TIMER_PULSE_HI 0x0004 +#define TIMER_MODE 0x0003 +#define TIMER_MODE_PWM 0x0001 +#define TIMER_MODE_WDTH 0x0002 +#define TIMER_MODE_EXT_CLK 0x0003 + +/* + * Timer Status Register Bits + */ +#define TIMER_STATUS_TIMIL0 0x0001 +#define TIMER_STATUS_TIMIL1 0x0002 +#define TIMER_STATUS_TIMIL2 0x0004 +#define TIMER_STATUS_TIMIL3 0x00000008 +#define TIMER_STATUS_TIMIL4 0x00010000 +#define TIMER_STATUS_TIMIL5 0x00020000 +#define TIMER_STATUS_TIMIL6 0x00040000 +#define TIMER_STATUS_TIMIL7 0x00080000 +#define TIMER_STATUS_TIMIL8 0x0001 +#define TIMER_STATUS_TIMIL9 0x0002 +#define TIMER_STATUS_TIMIL10 0x0004 +#define TIMER_STATUS_TIMIL11 0x0008 + +#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */ +#define TIMER_STATUS_TOVF1 0x0020 +#define TIMER_STATUS_TOVF2 0x0040 +#define TIMER_STATUS_TOVF3 0x00000080 +#define TIMER_STATUS_TOVF4 0x00100000 +#define TIMER_STATUS_TOVF5 0x00200000 +#define TIMER_STATUS_TOVF6 0x00400000 +#define TIMER_STATUS_TOVF7 0x00800000 +#define TIMER_STATUS_TOVF8 0x0010 +#define TIMER_STATUS_TOVF9 0x0020 +#define TIMER_STATUS_TOVF10 0x0040 +#define TIMER_STATUS_TOVF11 0x0080 + +/* + * Timer Slave Enable Status : write 1 to clear + */ +#define TIMER_STATUS_TRUN0 0x1000 +#define TIMER_STATUS_TRUN1 0x2000 +#define TIMER_STATUS_TRUN2 0x4000 +#define TIMER_STATUS_TRUN3 0x00008000 +#define TIMER_STATUS_TRUN4 0x10000000 +#define TIMER_STATUS_TRUN5 0x20000000 +#define TIMER_STATUS_TRUN6 0x40000000 +#define TIMER_STATUS_TRUN7 0x80000000 +#define TIMER_STATUS_TRUN 0xF000F000 +#define TIMER_STATUS_TRUN8 0x1000 +#define TIMER_STATUS_TRUN9 0x2000 +#define TIMER_STATUS_TRUN10 0x4000 +#define TIMER_STATUS_TRUN11 0x8000 + +#endif + +/* The actual gptimer API */ + +void set_gptimer_pwidth(unsigned int timer_id, uint32_t width); +uint32_t get_gptimer_pwidth(unsigned int timer_id); +void set_gptimer_period(unsigned int timer_id, uint32_t period); +uint32_t get_gptimer_period(unsigned int timer_id); +#ifdef CONFIG_BF60x +void set_gptimer_delay(unsigned int timer_id, uint32_t delay); +uint32_t get_gptimer_delay(unsigned int timer_id); +#endif +uint32_t get_gptimer_count(unsigned int timer_id); +int get_gptimer_intr(unsigned int timer_id); +void clear_gptimer_intr(unsigned int timer_id); +int get_gptimer_over(unsigned int timer_id); +void clear_gptimer_over(unsigned int timer_id); +void set_gptimer_config(unsigned int timer_id, uint16_t config); +uint16_t get_gptimer_config(unsigned int timer_id); +int get_gptimer_run(unsigned int timer_id); +void set_gptimer_pulse_hi(unsigned int timer_id); +void clear_gptimer_pulse_hi(unsigned int timer_id); +void enable_gptimers(uint16_t mask); +void disable_gptimers(uint16_t mask); +void disable_gptimers_sync(uint16_t mask); +uint16_t get_enabled_gptimers(void); +uint32_t get_gptimer_status(unsigned int group); +void set_gptimer_status(unsigned int group, uint32_t value); + +static inline void enable_gptimer(unsigned int timer_id) +{ + enable_gptimers(1 << timer_id); +} + +static inline void disable_gptimer(unsigned int timer_id) +{ + disable_gptimers(1 << timer_id); +} + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m + +/* + * bfin timer registers layout + */ +struct bfin_gptimer_regs { + __BFP(config); + u32 counter; + u32 period; + u32 width; +#ifdef CONFIG_BF60x + u32 delay; +#endif +}; + +/* + * bfin group timer registers layout + */ +#ifndef CONFIG_BF60x +struct bfin_gptimer_group_regs { + __BFP(enable); + __BFP(disable); + u32 status; +}; +#else +struct bfin_gptimer_group_regs { + __BFP(run); + __BFP(enable); + __BFP(disable); + __BFP(stop_cfg); + __BFP(stop_cfg_set); + __BFP(stop_cfg_clr); + __BFP(data_imsk); + __BFP(stat_imsk); + __BFP(tr_msk); + __BFP(tr_ie); + __BFP(data_ilat); + __BFP(stat_ilat); + __BFP(err_status); + __BFP(bcast_per); + __BFP(bcast_wid); + __BFP(bcast_dly); + +}; +#endif + +#undef __BFP + +#endif diff --git a/kernel/arch/blackfin/include/asm/hardirq.h b/kernel/arch/blackfin/include/asm/hardirq.h new file mode 100644 index 000000000..58b54a6d5 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/hardirq.h @@ -0,0 +1,17 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_HARDIRQ_H +#define __BFIN_HARDIRQ_H + +#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1 + +extern void ack_bad_irq(unsigned int irq); +#define ack_bad_irq ack_bad_irq + +#include <asm-generic/hardirq.h> + +#endif diff --git a/kernel/arch/blackfin/include/asm/io.h b/kernel/arch/blackfin/include/asm/io.h new file mode 100644 index 000000000..6abebe82d --- /dev/null +++ b/kernel/arch/blackfin/include/asm/io.h @@ -0,0 +1,49 @@ +/* + * Copyright 2004-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BFIN_IO_H +#define _BFIN_IO_H + +#include <linux/compiler.h> +#include <linux/types.h> +#include <asm/byteorder.h> +#include <asm/def_LPBlackfin.h> + +#define __raw_readb bfin_read8 +#define __raw_readw bfin_read16 +#define __raw_readl bfin_read32 +#define __raw_writeb(val, addr) bfin_write8(addr, val) +#define __raw_writew(val, addr) bfin_write16(addr, val) +#define __raw_writel(val, addr) bfin_write32(addr, val) + +extern void outsb(unsigned long port, const void *addr, unsigned long count); +extern void outsw(unsigned long port, const void *addr, unsigned long count); +extern void outsw_8(unsigned long port, const void *addr, unsigned long count); +extern void outsl(unsigned long port, const void *addr, unsigned long count); +#define outsb outsb +#define outsw outsw +#define outsl outsl + +extern void insb(unsigned long port, void *addr, unsigned long count); +extern void insw(unsigned long port, void *addr, unsigned long count); +extern void insw_8(unsigned long port, void *addr, unsigned long count); +extern void insl(unsigned long port, void *addr, unsigned long count); +extern void insl_16(unsigned long port, void *addr, unsigned long count); +#define insb insb +#define insw insw +#define insl insl + +/** + * I/O write barrier + * + * Ensure ordering of I/O space writes. This will make sure that writes + * following the barrier will arrive after all previous writes. + */ +#define mmiowb() do { SSYNC(); wmb(); } while (0) + +#include <asm-generic/io.h> + +#endif diff --git a/kernel/arch/blackfin/include/asm/ipipe.h b/kernel/arch/blackfin/include/asm/ipipe.h new file mode 100644 index 000000000..fe1160fbf --- /dev/null +++ b/kernel/arch/blackfin/include/asm/ipipe.h @@ -0,0 +1,209 @@ +/* -*- linux-c -*- + * include/asm-blackfin/ipipe.h + * + * Copyright (C) 2002-2007 Philippe Gerum. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139, + * USA; either version 2 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef __ASM_BLACKFIN_IPIPE_H +#define __ASM_BLACKFIN_IPIPE_H + +#ifdef CONFIG_IPIPE + +#include <linux/cpumask.h> +#include <linux/list.h> +#include <linux/threads.h> +#include <linux/irq.h> +#include <linux/ipipe_percpu.h> +#include <asm/ptrace.h> +#include <asm/irq.h> +#include <asm/bitops.h> +#include <linux/atomic.h> +#include <asm/traps.h> +#include <asm/bitsperlong.h> + +#define IPIPE_ARCH_STRING "1.16-01" +#define IPIPE_MAJOR_NUMBER 1 +#define IPIPE_MINOR_NUMBER 16 +#define IPIPE_PATCH_NUMBER 1 + +#ifdef CONFIG_SMP +#error "I-pipe/blackfin: SMP not implemented" +#else /* !CONFIG_SMP */ +#define ipipe_processor_id() 0 +#endif /* CONFIG_SMP */ + +#define prepare_arch_switch(next) \ +do { \ + ipipe_schedule_notify(current, next); \ + hard_local_irq_disable(); \ +} while (0) + +#define task_hijacked(p) \ + ({ \ + int __x__ = __ipipe_root_domain_p; \ + if (__x__) \ + hard_local_irq_enable(); \ + !__x__; \ + }) + +struct ipipe_domain; + +struct ipipe_sysinfo { + int sys_nr_cpus; /* Number of CPUs on board */ + int sys_hrtimer_irq; /* hrtimer device IRQ */ + u64 sys_hrtimer_freq; /* hrtimer device frequency */ + u64 sys_hrclock_freq; /* hrclock device frequency */ + u64 sys_cpu_freq; /* CPU frequency (Hz) */ +}; + +#define ipipe_read_tsc(t) \ + ({ \ + unsigned long __cy2; \ + __asm__ __volatile__ ("1: %0 = CYCLES2\n" \ + "%1 = CYCLES\n" \ + "%2 = CYCLES2\n" \ + "CC = %2 == %0\n" \ + "if ! CC jump 1b\n" \ + : "=d,a" (((unsigned long *)&t)[1]), \ + "=d,a" (((unsigned long *)&t)[0]), \ + "=d,a" (__cy2) \ + : /*no input*/ : "CC"); \ + t; \ + }) + +#define ipipe_cpu_freq() __ipipe_core_clock +#define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale) +#define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1) + +/* Private interface -- Internal use only */ + +#define __ipipe_check_platform() do { } while (0) + +#define __ipipe_init_platform() do { } while (0) + +extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1]; + +extern unsigned long __ipipe_irq_lvmask; + +extern struct ipipe_domain ipipe_root; + +/* enable/disable_irqdesc _must_ be used in pairs. */ + +void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, + unsigned irq); + +void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, + unsigned irq); + +#define __ipipe_enable_irq(irq) \ + do { \ + struct irq_desc *desc = irq_to_desc(irq); \ + struct irq_chip *chip = get_irq_desc_chip(desc); \ + chip->irq_unmask(&desc->irq_data); \ + } while (0) + +#define __ipipe_disable_irq(irq) \ + do { \ + struct irq_desc *desc = irq_to_desc(irq); \ + struct irq_chip *chip = get_irq_desc_chip(desc); \ + chip->irq_mask(&desc->irq_data); \ + } while (0) + +static inline int __ipipe_check_tickdev(const char *devname) +{ + return 1; +} + +void __ipipe_enable_pipeline(void); + +#define __ipipe_hook_critical_ipi(ipd) do { } while (0) + +void ___ipipe_sync_pipeline(void); + +void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); + +int __ipipe_get_irq_priority(unsigned int irq); + +void __ipipe_serial_debug(const char *fmt, ...); + +asmlinkage void __ipipe_call_irqtail(unsigned long addr); + +DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs); + +extern unsigned long __ipipe_core_clock; + +extern unsigned long __ipipe_freq_scale; + +extern unsigned long __ipipe_irq_tail_hook; + +static inline unsigned long __ipipe_ffnz(unsigned long ul) +{ + return ffs(ul) - 1; +} + +#define __ipipe_do_root_xirq(ipd, irq) \ + ((ipd)->irqs[irq].handler(irq, raw_cpu_ptr(&__ipipe_tick_regs))) + +#define __ipipe_run_irqtail(irq) /* Must be a macro */ \ + do { \ + unsigned long __pending; \ + CSYNC(); \ + __pending = bfin_read_IPEND(); \ + if (__pending & 0x8000) { \ + __pending &= ~0x8010; \ + if (__pending && (__pending & (__pending - 1)) == 0) \ + __ipipe_call_irqtail(__ipipe_irq_tail_hook); \ + } \ + } while (0) + +#define __ipipe_syscall_watched_p(p, sc) \ + (ipipe_notifier_enabled_p(p) || (unsigned long)sc >= NR_syscalls) + +#ifdef CONFIG_BF561 +#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) +#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val) +#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val) +#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS() +#elif defined(CONFIG_BF54x) +#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val) +#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val) +#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val) +#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val) +#endif + +#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0) + +#else /* !CONFIG_IPIPE */ + +#define task_hijacked(p) 0 +#define ipipe_trap_notify(t, r) 0 +#define __ipipe_root_tick_p(regs) 1 + +#endif /* !CONFIG_IPIPE */ + +#ifdef CONFIG_TICKSOURCE_CORETMR +#define IRQ_SYSTMR IRQ_CORETMR +#define IRQ_PRIOTMR IRQ_CORETMR +#else +#define IRQ_SYSTMR IRQ_TIMER0 +#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 +#endif + +#define ipipe_update_tick_evtdev(evtdev) do { } while (0) + +#endif /* !__ASM_BLACKFIN_IPIPE_H */ diff --git a/kernel/arch/blackfin/include/asm/ipipe_base.h b/kernel/arch/blackfin/include/asm/ipipe_base.h new file mode 100644 index 000000000..84a4ffd36 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/ipipe_base.h @@ -0,0 +1,75 @@ +/* -*- linux-c -*- + * include/asm-blackfin/ipipe_base.h + * + * Copyright (C) 2007 Philippe Gerum. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139, + * USA; either version 2 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef __ASM_BLACKFIN_IPIPE_BASE_H +#define __ASM_BLACKFIN_IPIPE_BASE_H + +#ifdef CONFIG_IPIPE + +#include <asm/bitsperlong.h> +#include <mach/irq.h> + +#define IPIPE_NR_XIRQS NR_IRQS + +/* Blackfin-specific, per-cpu pipeline status */ +#define IPIPE_SYNCDEFER_FLAG 15 +#define IPIPE_SYNCDEFER_MASK (1L << IPIPE_SYNCDEFER_MASK) + + /* Blackfin traps -- i.e. exception vector numbers */ +#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */ +/* Pseudo-vectors used for kernel events */ +#define IPIPE_FIRST_EVENT IPIPE_NR_FAULTS +#define IPIPE_EVENT_SYSCALL (IPIPE_FIRST_EVENT) +#define IPIPE_EVENT_SCHEDULE (IPIPE_FIRST_EVENT + 1) +#define IPIPE_EVENT_SIGWAKE (IPIPE_FIRST_EVENT + 2) +#define IPIPE_EVENT_SETSCHED (IPIPE_FIRST_EVENT + 3) +#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4) +#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5) +#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6) +#define IPIPE_EVENT_RETURN (IPIPE_FIRST_EVENT + 7) +#define IPIPE_LAST_EVENT IPIPE_EVENT_RETURN +#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1) + +#define IPIPE_TIMER_IRQ IRQ_CORETMR + +#define __IPIPE_FEATURE_SYSINFO_V2 1 + +#ifndef __ASSEMBLY__ + +extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ + +void __ipipe_stall_root(void); + +unsigned long __ipipe_test_and_stall_root(void); + +unsigned long __ipipe_test_root(void); + +void __ipipe_lock_root(void); + +void __ipipe_unlock_root(void); + +#endif /* !__ASSEMBLY__ */ + +#define __IPIPE_FEATURE_SYSINFO_V2 1 + +#endif /* CONFIG_IPIPE */ + +#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */ diff --git a/kernel/arch/blackfin/include/asm/irq.h b/kernel/arch/blackfin/include/asm/irq.h new file mode 100644 index 000000000..89de539ed --- /dev/null +++ b/kernel/arch/blackfin/include/asm/irq.h @@ -0,0 +1,41 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * 2003 HuTao + * 2002 Arcturus Networks Inc. (www.arcturusnetworks.com + * Ted Ma <mated@sympatico.ca> + * + * Licensed under the GPL-2 + */ + +#ifndef _BFIN_IRQ_H_ +#define _BFIN_IRQ_H_ + +#include <linux/irqflags.h> + +/* IRQs that may be used by external irq_chip controllers */ +#define NR_SPARE_IRQS 32 + +#include <mach/anomaly.h> + +/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ +#include <mach/irq.h> + +#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) +# define NOP_PAD_ANOMALY_05000244 "nop; nop;" +#else +# define NOP_PAD_ANOMALY_05000244 +#endif + +#define idle_with_irq_disabled() \ + __asm__ __volatile__( \ + NOP_PAD_ANOMALY_05000244 \ + ".align 8;" \ + "sti %0;" \ + "idle;" \ + : \ + : "d" (bfin_irq_flags) \ + ) + +#include <asm-generic/irq.h> + +#endif /* _BFIN_IRQ_H_ */ diff --git a/kernel/arch/blackfin/include/asm/irq_handler.h b/kernel/arch/blackfin/include/asm/irq_handler.h new file mode 100644 index 000000000..4b2a99279 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/irq_handler.h @@ -0,0 +1,66 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _IRQ_HANDLER_H +#define _IRQ_HANDLER_H + +#include <linux/types.h> +#include <linux/linkage.h> +#include <mach/irq.h> + +/* init functions only */ +extern int init_arch_irq(void); +extern void init_exception_vectors(void); +extern void program_IAR(void); +#ifdef init_mach_irq +extern void init_mach_irq(void); +#else +# define init_mach_irq() +#endif + +/* BASE LEVEL interrupt handler routines */ +asmlinkage void evt_exception(void); +asmlinkage void trap(void); +asmlinkage void evt_ivhw(void); +asmlinkage void evt_timer(void); +asmlinkage void evt_nmi(void); +asmlinkage void evt_evt7(void); +asmlinkage void evt_evt8(void); +asmlinkage void evt_evt9(void); +asmlinkage void evt_evt10(void); +asmlinkage void evt_evt11(void); +asmlinkage void evt_evt12(void); +asmlinkage void evt_evt13(void); +asmlinkage void evt_evt14(void); +asmlinkage void evt_soft_int1(void); +asmlinkage void evt_system_call(void); +asmlinkage void init_exception_buff(void); +asmlinkage void trap_c(struct pt_regs *fp); +asmlinkage void ex_replaceable(void); +asmlinkage void early_trap(void); + +extern void *ex_table[]; +extern void return_from_exception(void); + +extern int bfin_request_exception(unsigned int exception, void (*handler)(void)); +extern int bfin_free_exception(unsigned int exception, void (*handler)(void)); + +extern asmlinkage void lower_to_irq14(void); +extern asmlinkage void bfin_return_from_exception(void); +extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); +extern int bfin_internal_set_wake(unsigned int irq, unsigned int state); + +struct irq_data; +extern void bfin_handle_irq(unsigned irq); +extern void bfin_ack_noop(struct irq_data *); +extern void bfin_internal_mask_irq(unsigned int irq); +extern void bfin_internal_unmask_irq(unsigned int irq); + +struct irq_desc; +extern void bfin_demux_mac_status_irq(unsigned int, struct irq_desc *); +extern void bfin_demux_gpio_irq(unsigned int, struct irq_desc *); + +#endif diff --git a/kernel/arch/blackfin/include/asm/irqflags.h b/kernel/arch/blackfin/include/asm/irqflags.h new file mode 100644 index 000000000..07aff230a --- /dev/null +++ b/kernel/arch/blackfin/include/asm/irqflags.h @@ -0,0 +1,289 @@ +/* + * interface to Blackfin CEC + * + * Copyright 2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BFIN_IRQFLAGS_H__ +#define __ASM_BFIN_IRQFLAGS_H__ + +#include <mach/blackfin.h> + +#ifdef CONFIG_SMP +# include <asm/pda.h> +# include <asm/processor.h> +# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask +#else +extern unsigned long bfin_irq_flags; +#endif + +static inline notrace void bfin_sti(unsigned long flags) +{ + asm volatile("sti %0;" : : "d" (flags)); +} + +static inline notrace unsigned long bfin_cli(void) +{ + unsigned long flags; + asm volatile("cli %0;" : "=d" (flags)); + return flags; +} + +#ifdef CONFIG_DEBUG_HWERR +# define bfin_no_irqs 0x3f +#else +# define bfin_no_irqs 0x1f +#endif + +/*****************************************************************************/ +/* + * Hard, untraced CPU interrupt flag manipulation and access. + */ +static inline notrace void __hard_local_irq_disable(void) +{ + bfin_cli(); +} + +static inline notrace void __hard_local_irq_enable(void) +{ + bfin_sti(bfin_irq_flags); +} + +static inline notrace unsigned long hard_local_save_flags(void) +{ + return bfin_read_IMASK(); +} + +static inline notrace unsigned long __hard_local_irq_save(void) +{ + unsigned long flags; + flags = bfin_cli(); +#ifdef CONFIG_DEBUG_HWERR + bfin_sti(0x3f); +#endif + return flags; +} + +static inline notrace int hard_irqs_disabled_flags(unsigned long flags) +{ +#ifdef CONFIG_BF60x + return (flags & IMASK_IVG11) == 0; +#else + return (flags & ~0x3f) == 0; +#endif +} + +static inline notrace int hard_irqs_disabled(void) +{ + unsigned long flags = hard_local_save_flags(); + return hard_irqs_disabled_flags(flags); +} + +static inline notrace void __hard_local_irq_restore(unsigned long flags) +{ + if (!hard_irqs_disabled_flags(flags)) + __hard_local_irq_enable(); +} + +/*****************************************************************************/ +/* + * Interrupt pipe handling. + */ +#ifdef CONFIG_IPIPE + +#include <linux/compiler.h> +#include <linux/ipipe_trace.h> +/* + * Way too many inter-deps between low-level headers in this port, so + * we redeclare the required bits we cannot pick from + * <asm/ipipe_base.h> to prevent circular dependencies. + */ +void __ipipe_stall_root(void); +void __ipipe_unstall_root(void); +unsigned long __ipipe_test_root(void); +unsigned long __ipipe_test_and_stall_root(void); +void __ipipe_restore_root(unsigned long flags); + +#ifdef CONFIG_IPIPE_DEBUG_CONTEXT +struct ipipe_domain; +extern struct ipipe_domain ipipe_root; +void ipipe_check_context(struct ipipe_domain *ipd); +#define __check_irqop_context(ipd) ipipe_check_context(&ipipe_root) +#else /* !CONFIG_IPIPE_DEBUG_CONTEXT */ +#define __check_irqop_context(ipd) do { } while (0) +#endif /* !CONFIG_IPIPE_DEBUG_CONTEXT */ + +/* + * Interrupt pipe interface to linux/irqflags.h. + */ +static inline notrace void arch_local_irq_disable(void) +{ + __check_irqop_context(); + __ipipe_stall_root(); + barrier(); +} + +static inline notrace void arch_local_irq_enable(void) +{ + barrier(); + __check_irqop_context(); + __ipipe_unstall_root(); +} + +static inline notrace unsigned long arch_local_save_flags(void) +{ + return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; +} + +static inline notrace int arch_irqs_disabled_flags(unsigned long flags) +{ + return flags == bfin_no_irqs; +} + +static inline notrace unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + + __check_irqop_context(); + flags = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; + barrier(); + + return flags; +} + +static inline notrace void arch_local_irq_restore(unsigned long flags) +{ + __check_irqop_context(); + __ipipe_restore_root(flags == bfin_no_irqs); +} + +static inline notrace unsigned long arch_mangle_irq_bits(int virt, unsigned long real) +{ + /* + * Merge virtual and real interrupt mask bits into a single + * 32bit word. + */ + return (real & ~(1 << 31)) | ((virt != 0) << 31); +} + +static inline notrace int arch_demangle_irq_bits(unsigned long *x) +{ + int virt = (*x & (1 << 31)) != 0; + *x &= ~(1L << 31); + return virt; +} + +/* + * Interface to various arch routines that may be traced. + */ +#ifdef CONFIG_IPIPE_TRACE_IRQSOFF +static inline notrace void hard_local_irq_disable(void) +{ + if (!hard_irqs_disabled()) { + __hard_local_irq_disable(); + ipipe_trace_begin(0x80000000); + } +} + +static inline notrace void hard_local_irq_enable(void) +{ + if (hard_irqs_disabled()) { + ipipe_trace_end(0x80000000); + __hard_local_irq_enable(); + } +} + +static inline notrace unsigned long hard_local_irq_save(void) +{ + unsigned long flags = hard_local_save_flags(); + if (!hard_irqs_disabled_flags(flags)) { + __hard_local_irq_disable(); + ipipe_trace_begin(0x80000001); + } + return flags; +} + +static inline notrace void hard_local_irq_restore(unsigned long flags) +{ + if (!hard_irqs_disabled_flags(flags)) { + ipipe_trace_end(0x80000001); + __hard_local_irq_enable(); + } +} + +#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */ +# define hard_local_irq_disable() __hard_local_irq_disable() +# define hard_local_irq_enable() __hard_local_irq_enable() +# define hard_local_irq_save() __hard_local_irq_save() +# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags) +#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */ + +#define hard_local_irq_save_cond() hard_local_irq_save() +#define hard_local_irq_restore_cond(flags) hard_local_irq_restore(flags) + +#else /* !CONFIG_IPIPE */ + +/* + * Direct interface to linux/irqflags.h. + */ +#define arch_local_save_flags() hard_local_save_flags() +#define arch_local_irq_save() __hard_local_irq_save() +#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags) +#define arch_local_irq_enable() __hard_local_irq_enable() +#define arch_local_irq_disable() __hard_local_irq_disable() +#define arch_irqs_disabled_flags(flags) hard_irqs_disabled_flags(flags) +#define arch_irqs_disabled() hard_irqs_disabled() + +/* + * Interface to various arch routines that may be traced. + */ +#define hard_local_irq_save() __hard_local_irq_save() +#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags) +#define hard_local_irq_enable() __hard_local_irq_enable() +#define hard_local_irq_disable() __hard_local_irq_disable() +#define hard_local_irq_save_cond() hard_local_save_flags() +#define hard_local_irq_restore_cond(flags) do { (void)(flags); } while (0) + +#endif /* !CONFIG_IPIPE */ + +#ifdef CONFIG_SMP +#define hard_local_irq_save_smp() hard_local_irq_save() +#define hard_local_irq_restore_smp(flags) hard_local_irq_restore(flags) +#else +#define hard_local_irq_save_smp() hard_local_save_flags() +#define hard_local_irq_restore_smp(flags) do { (void)(flags); } while (0) +#endif + +/* + * Remap the arch-neutral IRQ state manipulation macros to the + * blackfin-specific hard_local_irq_* API. + */ +#define local_irq_save_hw(flags) \ + do { \ + (flags) = hard_local_irq_save(); \ + } while (0) +#define local_irq_restore_hw(flags) \ + do { \ + hard_local_irq_restore(flags); \ + } while (0) +#define local_irq_disable_hw() \ + do { \ + hard_local_irq_disable(); \ + } while (0) +#define local_irq_enable_hw() \ + do { \ + hard_local_irq_enable(); \ + } while (0) +#define local_irq_save_hw_notrace(flags) \ + do { \ + (flags) = __hard_local_irq_save(); \ + } while (0) +#define local_irq_restore_hw_notrace(flags) \ + do { \ + __hard_local_irq_restore(flags); \ + } while (0) + +#define irqs_disabled_hw() hard_irqs_disabled() + +#endif diff --git a/kernel/arch/blackfin/include/asm/kgdb.h b/kernel/arch/blackfin/include/asm/kgdb.h new file mode 100644 index 000000000..2703ddeeb --- /dev/null +++ b/kernel/arch/blackfin/include/asm/kgdb.h @@ -0,0 +1,169 @@ +/* Blackfin KGDB header + * + * Copyright 2005-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BLACKFIN_KGDB_H__ +#define __ASM_BLACKFIN_KGDB_H__ + +#include <linux/ptrace.h> + +/* + * BUFMAX defines the maximum number of characters in inbound/outbound buffers. + * At least NUMREGBYTES*2 are needed for register packets. + * Longer buffer is needed to list all threads. + */ +#define BUFMAX 2048 + +/* + * Note that this register image is different from + * the register image that Linux produces at interrupt time. + * + * Linux's register image is defined by struct pt_regs in ptrace.h. + */ +enum regnames { + /* Core Registers */ + BFIN_R0 = 0, + BFIN_R1, + BFIN_R2, + BFIN_R3, + BFIN_R4, + BFIN_R5, + BFIN_R6, + BFIN_R7, + BFIN_P0, + BFIN_P1, + BFIN_P2, + BFIN_P3, + BFIN_P4, + BFIN_P5, + BFIN_SP, + BFIN_FP, + BFIN_I0, + BFIN_I1, + BFIN_I2, + BFIN_I3, + BFIN_M0, + BFIN_M1, + BFIN_M2, + BFIN_M3, + BFIN_B0, + BFIN_B1, + BFIN_B2, + BFIN_B3, + BFIN_L0, + BFIN_L1, + BFIN_L2, + BFIN_L3, + BFIN_A0_DOT_X, + BFIN_A0_DOT_W, + BFIN_A1_DOT_X, + BFIN_A1_DOT_W, + BFIN_ASTAT, + BFIN_RETS, + BFIN_LC0, + BFIN_LT0, + BFIN_LB0, + BFIN_LC1, + BFIN_LT1, + BFIN_LB1, + BFIN_CYCLES, + BFIN_CYCLES2, + BFIN_USP, + BFIN_SEQSTAT, + BFIN_SYSCFG, + BFIN_RETI, + BFIN_RETX, + BFIN_RETN, + BFIN_RETE, + + /* Pseudo Registers */ + BFIN_PC, + BFIN_CC, + BFIN_EXTRA1, /* Address of .text section. */ + BFIN_EXTRA2, /* Address of .data section. */ + BFIN_EXTRA3, /* Address of .bss section. */ + BFIN_FDPIC_EXEC, + BFIN_FDPIC_INTERP, + + /* MMRs */ + BFIN_IPEND, + + /* LAST ENTRY SHOULD NOT BE CHANGED. */ + BFIN_NUM_REGS /* The number of all registers. */ +}; + +/* Number of bytes of registers. */ +#define NUMREGBYTES BFIN_NUM_REGS*4 + +static inline void arch_kgdb_breakpoint(void) +{ + asm("EXCPT 2;"); +} +#define BREAK_INSTR_SIZE 2 +#ifdef CONFIG_SMP +# define CACHE_FLUSH_IS_SAFE 0 +#else +# define CACHE_FLUSH_IS_SAFE 1 +#endif +#define GDB_ADJUSTS_BREAK_OFFSET +#define GDB_SKIP_HW_WATCH_TEST +#define HW_INST_WATCHPOINT_NUM 6 +#define HW_WATCHPOINT_NUM 8 +#define TYPE_INST_WATCHPOINT 0 +#define TYPE_DATA_WATCHPOINT 1 + +/* Instruction watchpoint address control register bits mask */ +#define WPPWR 0x1 +#define WPIREN01 0x2 +#define WPIRINV01 0x4 +#define WPIAEN0 0x8 +#define WPIAEN1 0x10 +#define WPICNTEN0 0x20 +#define WPICNTEN1 0x40 +#define EMUSW0 0x80 +#define EMUSW1 0x100 +#define WPIREN23 0x200 +#define WPIRINV23 0x400 +#define WPIAEN2 0x800 +#define WPIAEN3 0x1000 +#define WPICNTEN2 0x2000 +#define WPICNTEN3 0x4000 +#define EMUSW2 0x8000 +#define EMUSW3 0x10000 +#define WPIREN45 0x20000 +#define WPIRINV45 0x40000 +#define WPIAEN4 0x80000 +#define WPIAEN5 0x100000 +#define WPICNTEN4 0x200000 +#define WPICNTEN5 0x400000 +#define EMUSW4 0x800000 +#define EMUSW5 0x1000000 +#define WPAND 0x2000000 + +/* Data watchpoint address control register bits mask */ +#define WPDREN01 0x1 +#define WPDRINV01 0x2 +#define WPDAEN0 0x4 +#define WPDAEN1 0x8 +#define WPDCNTEN0 0x10 +#define WPDCNTEN1 0x20 + +#define WPDSRC0 0xc0 +#define WPDACC0_OFFSET 8 +#define WPDSRC1 0xc00 +#define WPDACC1_OFFSET 12 + +/* Watchpoint status register bits mask */ +#define STATIA0 0x1 +#define STATIA1 0x2 +#define STATIA2 0x4 +#define STATIA3 0x8 +#define STATIA4 0x10 +#define STATIA5 0x20 +#define STATDA0 0x40 +#define STATDA1 0x80 + +#endif diff --git a/kernel/arch/blackfin/include/asm/l1layout.h b/kernel/arch/blackfin/include/asm/l1layout.h new file mode 100644 index 000000000..c87e68647 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/l1layout.h @@ -0,0 +1,37 @@ +/* + * Defines a layout of L1 scratchpad memory that userspace can rely on. + * + * Copyright 2006-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _L1LAYOUT_H_ +#define _L1LAYOUT_H_ + +#include <asm/blackfin.h> + +#ifndef CONFIG_SMP +#ifndef __ASSEMBLY__ + +/* Data that is "mapped" into the process VM at the start of the L1 scratch + memory, so that each process can access it at a fixed address. Used for + stack checking. */ +struct l1_scratch_task_info +{ + /* Points to the start of the stack. */ + void *stack_start; + /* Not updated by the kernel; a user process can modify this to + keep track of the lowest address of the stack pointer during its + runtime. */ + void *lowest_sp; +}; + +/* A pointer to the structure in memory. */ +#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)\ + get_l1_scratch_start()) + +#endif +#endif + +#endif diff --git a/kernel/arch/blackfin/include/asm/linkage.h b/kernel/arch/blackfin/include/asm/linkage.h new file mode 100644 index 000000000..f7d6d47a0 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/linkage.h @@ -0,0 +1,13 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +#define __ALIGN .align 4 +#define __ALIGN_STR ".align 4" + +#endif diff --git a/kernel/arch/blackfin/include/asm/mem_init.h b/kernel/arch/blackfin/include/asm/mem_init.h new file mode 100644 index 000000000..c865b33ee --- /dev/null +++ b/kernel/arch/blackfin/include/asm/mem_init.h @@ -0,0 +1,500 @@ +/* + * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory + * + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __MEM_INIT_H__ +#define __MEM_INIT_H__ + +#if defined(EBIU_SDGCTL) +#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ + defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ + defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ + defined(CONFIG_MEM_MT48LC32M8A2_75) || \ + defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \ + defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ + defined(CONFIG_MEM_MT48LC32M8A2_75) +#if (CONFIG_SCLK_HZ > 119402985) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_7 +#define SDRAM_tRAS_num 7 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_6 +#define SDRAM_tRAS_num 6 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_5 +#define SDRAM_tRAS_num 5 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_4 +#define SDRAM_tRAS_num 4 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_3 +#define SDRAM_tRAS_num 3 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) +#define SDRAM_tRP TRP_1 +#define SDRAM_tRP_num 1 +#define SDRAM_tRAS TRAS_4 +#define SDRAM_tRAS_num 4 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) +#define SDRAM_tRP TRP_1 +#define SDRAM_tRP_num 1 +#define SDRAM_tRAS TRAS_3 +#define SDRAM_tRAS_num 3 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) +#define SDRAM_tRP TRP_1 +#define SDRAM_tRP_num 1 +#define SDRAM_tRAS TRAS_2 +#define SDRAM_tRAS_num 2 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ <= 29850746) +#define SDRAM_tRP TRP_1 +#define SDRAM_tRP_num 1 +#define SDRAM_tRAS TRAS_1 +#define SDRAM_tRAS_num 1 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#endif + +/* + * The BF526-EZ-Board changed SDRAM chips between revisions, + * so we use below timings to accommodate both. + */ +#if defined(CONFIG_MEM_MT48H32M16LFCJ_75) +#if (CONFIG_SCLK_HZ > 119402985) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_8 +#define SDRAM_tRAS_num 8 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_7 +#define SDRAM_tRAS_num 7 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_6 +#define SDRAM_tRAS_num 6 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_5 +#define SDRAM_tRAS_num 5 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_4 +#define SDRAM_tRAS_num 4 +#define SDRAM_tRCD TRCD_2 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_4 +#define SDRAM_tRAS_num 4 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) +#define SDRAM_tRP TRP_2 +#define SDRAM_tRP_num 2 +#define SDRAM_tRAS TRAS_3 +#define SDRAM_tRAS_num 3 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) +#define SDRAM_tRP TRP_1 +#define SDRAM_tRP_num 1 +#define SDRAM_tRAS TRAS_3 +#define SDRAM_tRAS_num 3 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#if (CONFIG_SCLK_HZ <= 29850746) +#define SDRAM_tRP TRP_1 +#define SDRAM_tRP_num 1 +#define SDRAM_tRAS TRAS_2 +#define SDRAM_tRAS_num 2 +#define SDRAM_tRCD TRCD_1 +#define SDRAM_tWR TWR_2 +#endif +#endif + +#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ + defined(CONFIG_MEM_MT48LC8M32B2B5_7) + /*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ +#define SDRAM_CL CL_3 +#endif + +#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \ + defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ + defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ + defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ + defined(CONFIG_MEM_MT48LC32M8A2_75) + /*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +#define SDRAM_CL CL_3 +#endif + +#if defined(CONFIG_MEM_MT48H32M16LFCJ_75) + /*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +#define SDRAM_CL CL_2 +#endif + + +#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC +/* Equation from section 17 (p17-46) of BF533 HRM */ +#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) + +/* Enable SCLK Out */ +#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) +#else +#define mem_SDRRC CONFIG_MEM_SDRRC +#define mem_SDGCTL CONFIG_MEM_SDGCTL +#endif +#endif + + +#if defined(EBIU_DDRCTL0) +#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1) +#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000) +#define DDR_CLK_HZ(x) (1000*1000*1000/x) + +#if defined(CONFIG_MEM_MT46V32M16_6T) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 +#define DDR_MAX_tCK 13 + +#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60)) +#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42)) +#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) +#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72)) +#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) + +#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) +#define DDR_tWTR DDR_TWTR(1) +#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12)) +#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) +#endif + +#if defined(CONFIG_MEM_MT46V32M16_5B) +#define DDR_SIZE DEVSZ_512 +#define DDR_WIDTH DEVWD_16 +#define DDR_MAX_tCK 13 + +#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55)) +#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40)) +#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15)) +#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70)) +#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800)) + +#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15)) +#define DDR_tWTR DDR_TWTR(2) +#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10)) +#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) +#endif + +#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK)) +# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)." +#elif(CONFIG_SCLK_HZ <= 133333333) +# define DDR_CL CL_2 +#else +# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)." +#endif + +#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC +#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI) +#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \ + | DDR_tMRD | DDR_tWR | DDR_tRCD) +#define mem_DDRCTL2 DDR_CL +#else +#define mem_DDRCTL0 CONFIG_MEM_DDRCTL0 +#define mem_DDRCTL1 CONFIG_MEM_DDRCTL1 +#define mem_DDRCTL2 CONFIG_MEM_DDRCTL2 +#endif +#endif + +#if defined CONFIG_CLKIN_HALF +#define CLKIN_HALF 1 +#else +#define CLKIN_HALF 0 +#endif + +#if defined CONFIG_PLL_BYPASS +#define PLL_BYPASS 1 +#else +#define PLL_BYPASS 0 +#endif + +#ifdef CONFIG_BF60x + +/* DMC status bits */ +#define IDLE 0x1 +#define MEMINITDONE 0x4 +#define SRACK 0x8 +#define PDACK 0x10 +#define DPDACK 0x20 +#define DLLCALDONE 0x2000 +#define PENDREF 0xF0000 +#define PHYRDPHASE 0xF00000 +#define PHYRDPHASE_OFFSET 20 + +/* DMC control bits */ +#define LPDDR 0x2 +#define INIT 0x4 +#define SRREQ 0x8 +#define PDREQ 0x10 +#define DPDREQ 0x20 +#define PREC 0x40 +#define ADDRMODE 0x100 +#define RDTOWR 0xE00 +#define PPREF 0x1000 +#define DLLCAL 0x2000 + +/* DMC DLL control bits */ +#define DLLCALRDCNT 0xFF +#define DATACYC 0xF00 +#define DATACYC_OFFSET 8 + +/* CGU Divisor bits */ +#define CSEL_OFFSET 0 +#define S0SEL_OFFSET 5 +#define SYSSEL_OFFSET 8 +#define S1SEL_OFFSET 13 +#define DSEL_OFFSET 16 +#define OSEL_OFFSET 22 +#define ALGN 0x20000000 +#define UPDT 0x40000000 +#define LOCK 0x80000000 + +/* CGU Status bits */ +#define PLLEN 0x1 +#define PLLBP 0x2 +#define PLOCK 0x4 +#define CLKSALGN 0x8 + +/* CGU Control bits */ +#define MSEL_MASK 0x7F00 +#define DF_MASK 0x1 + +struct ddr_config { + u32 ddr_clk; + u32 dmc_ddrctl; + u32 dmc_effctl; + u32 dmc_ddrcfg; + u32 dmc_ddrtr0; + u32 dmc_ddrtr1; + u32 dmc_ddrtr2; + u32 dmc_ddrmr; + u32 dmc_ddrmr1; +}; + +#if defined(CONFIG_MEM_MT47H64M16) +static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = { + [0] = { + .ddr_clk = 125, + .dmc_ddrctl = 0x00000904, + .dmc_effctl = 0x004400C0, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20705212, + .dmc_ddrtr1 = 0x201003CF, + .dmc_ddrtr2 = 0x00320107, + .dmc_ddrmr = 0x00000422, + .dmc_ddrmr1 = 0x4, + }, + [1] = { + .ddr_clk = 133, + .dmc_ddrctl = 0x00000904, + .dmc_effctl = 0x004400C0, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20806313, + .dmc_ddrtr1 = 0x2013040D, + .dmc_ddrtr2 = 0x00320108, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [2] = { + .ddr_clk = 150, + .dmc_ddrctl = 0x00000904, + .dmc_effctl = 0x004400C0, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20A07323, + .dmc_ddrtr1 = 0x20160492, + .dmc_ddrtr2 = 0x00320209, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [3] = { + .ddr_clk = 166, + .dmc_ddrctl = 0x00000904, + .dmc_effctl = 0x004400C0, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20A07323, + .dmc_ddrtr1 = 0x2016050E, + .dmc_ddrtr2 = 0x00320209, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [4] = { + .ddr_clk = 200, + .dmc_ddrctl = 0x00000904, + .dmc_effctl = 0x004400C0, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20a07323, + .dmc_ddrtr1 = 0x2016050f, + .dmc_ddrtr2 = 0x00320509, + .dmc_ddrmr = 0x00000632, + .dmc_ddrmr1 = 0x4, + }, + [5] = { + .ddr_clk = 225, + .dmc_ddrctl = 0x00000904, + .dmc_effctl = 0x004400C0, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20E0A424, + .dmc_ddrtr1 = 0x302006DB, + .dmc_ddrtr2 = 0x0032020D, + .dmc_ddrmr = 0x00000842, + .dmc_ddrmr1 = 0x4, + }, + [6] = { + .ddr_clk = 250, + .dmc_ddrctl = 0x00000904, + .dmc_effctl = 0x004400C0, + .dmc_ddrcfg = 0x00000422, + .dmc_ddrtr0 = 0x20E0A424, + .dmc_ddrtr1 = 0x3020079E, + .dmc_ddrtr2 = 0x0032050D, + .dmc_ddrmr = 0x00000842, + .dmc_ddrmr1 = 0x4, + }, +}; +#endif + +static inline void dmc_enter_self_refresh(void) +{ + if (bfin_read_DMC0_STAT() & MEMINITDONE) { + bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ); + while (!(bfin_read_DMC0_STAT() & SRACK)) + continue; + } +} + +static inline void dmc_exit_self_refresh(void) +{ + if (bfin_read_DMC0_STAT() & MEMINITDONE) { + bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ); + while (bfin_read_DMC0_STAT() & SRACK) + continue; + } +} + +static inline void init_cgu(u32 cgu_div, u32 cgu_ctl) +{ + dmc_enter_self_refresh(); + + /* Don't set the same value of MSEL and DF to CGU_CTL */ + if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK)) + != cgu_ctl) { + bfin_write32(CGU0_DIV, cgu_div); + bfin_write32(CGU0_CTL, cgu_ctl); + while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) || + !(bfin_read32(CGU0_STAT) & PLOCK)) + continue; + } + + bfin_write32(CGU0_DIV, cgu_div | UPDT); + while (bfin_read32(CGU0_STAT) & CLKSALGN) + continue; + + dmc_exit_self_refresh(); +} + +static inline void init_dmc(u32 dmc_clk) +{ + int i, dlldatacycle, dll_ctl; + + for (i = 0; i < 7; i++) { + if (ddr_config_table[i].ddr_clk == dmc_clk) { + bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg); + bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0); + bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1); + bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2); + bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr); + bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1); + bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl); + bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl); + break; + } + } + + while (!(bfin_read_DMC0_STAT() & MEMINITDONE)) + continue; + + dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET; + dll_ctl = bfin_read_DMC0_DLLCTL(); + dll_ctl &= ~DATACYC; + bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET)); + + while (!(bfin_read_DMC0_STAT() & DLLCALDONE)) + continue; +} +#endif + +#endif /*__MEM_INIT_H__*/ + diff --git a/kernel/arch/blackfin/include/asm/mem_map.h b/kernel/arch/blackfin/include/asm/mem_map.h new file mode 100644 index 000000000..5e21627c9 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/mem_map.h @@ -0,0 +1,84 @@ +/* + * Common Blackfin memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_MEM_MAP_H__ +#define __BFIN_MEM_MAP_H__ + +#include <mach/mem_map.h> + +/* Every Blackfin so far has MMRs like this */ +#ifndef COREMMR_BASE +# define COREMMR_BASE 0xFFE00000 +#endif +#ifndef SYSMMR_BASE +# define SYSMMR_BASE 0xFFC00000 +#endif + +/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */ +#ifndef L1_SCRATCH_START +# define L1_SCRATCH_START 0xFFB00000 +# define L1_SCRATCH_LENGTH 0x1000 +#endif + +/* Most parts lack on-chip L2 SRAM */ +#ifndef L2_START +# define L2_START 0 +# define L2_LENGTH 0 +#endif + +/* Most parts lack on-chip L1 ROM */ +#ifndef L1_ROM_START +# define L1_ROM_START 0 +# define L1_ROM_LENGTH 0 +#endif + +/* Allow wonky SMP ports to override this */ +#ifndef GET_PDA_SAFE +# define GET_PDA_SAFE(preg) \ + preg.l = _cpu_pda; \ + preg.h = _cpu_pda; +# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) + +# ifndef __ASSEMBLY__ + +static inline unsigned long get_l1_scratch_start_cpu(int cpu) +{ + return L1_SCRATCH_START; +} +static inline unsigned long get_l1_code_start_cpu(int cpu) +{ + return L1_CODE_START; +} +static inline unsigned long get_l1_data_a_start_cpu(int cpu) +{ + return L1_DATA_A_START; +} +static inline unsigned long get_l1_data_b_start_cpu(int cpu) +{ + return L1_DATA_B_START; +} +static inline unsigned long get_l1_scratch_start(void) +{ + return get_l1_scratch_start_cpu(0); +} +static inline unsigned long get_l1_code_start(void) +{ + return get_l1_code_start_cpu(0); +} +static inline unsigned long get_l1_data_a_start(void) +{ + return get_l1_data_a_start_cpu(0); +} +static inline unsigned long get_l1_data_b_start(void) +{ + return get_l1_data_b_start_cpu(0); +} + +# endif /* __ASSEMBLY__ */ +#endif /* !GET_PDA_SAFE */ + +#endif diff --git a/kernel/arch/blackfin/include/asm/mmu.h b/kernel/arch/blackfin/include/asm/mmu.h new file mode 100644 index 000000000..26f6b70b1 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/mmu.h @@ -0,0 +1,36 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * 2002 David McCullough <davidm@snapgear.com> + * + * Licensed under the GPL-2. + */ + +#ifndef __MMU_H +#define __MMU_H + +struct sram_list_struct { + struct sram_list_struct *next; + void *addr; + size_t length; +}; + +typedef struct { + unsigned long end_brk; + unsigned long stack_start; + + /* Points to the location in SDRAM where the L1 stack is normally + saved, or NULL if the stack is always in SDRAM. */ + void *l1_stack_save; + + struct sram_list_struct *sram_list; + +#ifdef CONFIG_BINFMT_ELF_FDPIC + unsigned long exec_fdpic_loadmap; + unsigned long interp_fdpic_loadmap; +#endif +#ifdef CONFIG_MPU + unsigned long *page_rwx_mask; +#endif +} mm_context_t; + +#endif diff --git a/kernel/arch/blackfin/include/asm/mmu_context.h b/kernel/arch/blackfin/include/asm/mmu_context.h new file mode 100644 index 000000000..15b16d3e8 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/mmu_context.h @@ -0,0 +1,216 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BLACKFIN_MMU_CONTEXT_H__ +#define __BLACKFIN_MMU_CONTEXT_H__ + +#include <linux/slab.h> +#include <linux/sched.h> +#include <asm/setup.h> +#include <asm/page.h> +#include <asm/pgalloc.h> +#include <asm/cplbinit.h> +#include <asm/sections.h> + +/* Note: L1 stacks are CPU-private things, so we bluntly disable this + feature in SMP mode, and use the per-CPU scratch SRAM bank only to + store the PDA instead. */ + +extern void *current_l1_stack_save; +extern int nr_l1stack_tasks; +extern void *l1_stack_base; +extern unsigned long l1_stack_len; + +extern int l1sram_free(const void*); +extern void *l1sram_alloc_max(void*); + +static inline void free_l1stack(void) +{ + nr_l1stack_tasks--; + if (nr_l1stack_tasks == 0) { + l1sram_free(l1_stack_base); + l1_stack_base = NULL; + l1_stack_len = 0; + } +} + +static inline unsigned long +alloc_l1stack(unsigned long length, unsigned long *stack_base) +{ + if (nr_l1stack_tasks == 0) { + l1_stack_base = l1sram_alloc_max(&l1_stack_len); + if (!l1_stack_base) + return 0; + } + + if (l1_stack_len < length) { + if (nr_l1stack_tasks == 0) + l1sram_free(l1_stack_base); + return 0; + } + *stack_base = (unsigned long)l1_stack_base; + nr_l1stack_tasks++; + return l1_stack_len; +} + +static inline int +activate_l1stack(struct mm_struct *mm, unsigned long sp_base) +{ + if (current_l1_stack_save) + memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len); + mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base; + memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len); + return 1; +} + +#define deactivate_mm(tsk,mm) do { } while (0) + +#define activate_mm(prev, next) switch_mm(prev, next, NULL) + +static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, + struct task_struct *tsk) +{ +#ifdef CONFIG_MPU + unsigned int cpu = smp_processor_id(); +#endif + if (prev_mm == next_mm) + return; +#ifdef CONFIG_MPU + if (prev_mm->context.page_rwx_mask == current_rwx_mask[cpu]) { + flush_switched_cplbs(cpu); + set_mask_dcplbs(next_mm->context.page_rwx_mask, cpu); + } +#endif + +#ifdef CONFIG_APP_STACK_L1 + /* L1 stack switching. */ + if (!next_mm->context.l1_stack_save) + return; + if (next_mm->context.l1_stack_save == current_l1_stack_save) + return; + if (current_l1_stack_save) { + memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len); + } + current_l1_stack_save = next_mm->context.l1_stack_save; + memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len); +#endif +} + +#ifdef CONFIG_IPIPE +#define lock_mm_switch(flags) flags = hard_local_irq_save_cond() +#define unlock_mm_switch(flags) hard_local_irq_restore_cond(flags) +#else +#define lock_mm_switch(flags) do { (void)(flags); } while (0) +#define unlock_mm_switch(flags) do { (void)(flags); } while (0) +#endif /* CONFIG_IPIPE */ + +#ifdef CONFIG_MPU +static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) +{ + unsigned long flags; + lock_mm_switch(flags); + __switch_mm(prev, next, tsk); + unlock_mm_switch(flags); +} + +static inline void protect_page(struct mm_struct *mm, unsigned long addr, + unsigned long flags) +{ + unsigned long *mask = mm->context.page_rwx_mask; + unsigned long page; + unsigned long idx; + unsigned long bit; + + if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)) + page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> 12; + else + page = addr >> 12; + idx = page >> 5; + bit = 1 << (page & 31); + + if (flags & VM_READ) + mask[idx] |= bit; + else + mask[idx] &= ~bit; + mask += page_mask_nelts; + if (flags & VM_WRITE) + mask[idx] |= bit; + else + mask[idx] &= ~bit; + mask += page_mask_nelts; + if (flags & VM_EXEC) + mask[idx] |= bit; + else + mask[idx] &= ~bit; +} + +static inline void update_protections(struct mm_struct *mm) +{ + unsigned int cpu = smp_processor_id(); + if (mm->context.page_rwx_mask == current_rwx_mask[cpu]) { + flush_switched_cplbs(cpu); + set_mask_dcplbs(mm->context.page_rwx_mask, cpu); + } +} +#else /* !CONFIG_MPU */ +static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) +{ + __switch_mm(prev, next, tsk); +} +#endif + +static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) +{ +} + +/* Called when creating a new context during fork() or execve(). */ +static inline int +init_new_context(struct task_struct *tsk, struct mm_struct *mm) +{ +#ifdef CONFIG_MPU + unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order); + mm->context.page_rwx_mask = (unsigned long *)p; + memset(mm->context.page_rwx_mask, 0, + page_mask_nelts * 3 * sizeof(long)); +#endif + return 0; +} + +static inline void destroy_context(struct mm_struct *mm) +{ + struct sram_list_struct *tmp; +#ifdef CONFIG_MPU + unsigned int cpu = smp_processor_id(); +#endif + +#ifdef CONFIG_APP_STACK_L1 + if (current_l1_stack_save == mm->context.l1_stack_save) + current_l1_stack_save = 0; + if (mm->context.l1_stack_save) + free_l1stack(); +#endif + + while ((tmp = mm->context.sram_list)) { + mm->context.sram_list = tmp->next; + sram_free(tmp->addr); + kfree(tmp); + } +#ifdef CONFIG_MPU + if (current_rwx_mask[cpu] == mm->context.page_rwx_mask) + current_rwx_mask[cpu] = NULL; + free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order); +#endif +} + +#define ipipe_mm_switch_protect(flags) \ + flags = hard_local_irq_save_cond() + +#define ipipe_mm_switch_unprotect(flags) \ + hard_local_irq_restore_cond(flags) + +#endif diff --git a/kernel/arch/blackfin/include/asm/module.h b/kernel/arch/blackfin/include/asm/module.h new file mode 100644 index 000000000..231a149b3 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/module.h @@ -0,0 +1,22 @@ +/* + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_BFIN_MODULE_H +#define _ASM_BFIN_MODULE_H + +#include <asm-generic/module.h> + +struct mod_arch_specific { + Elf_Shdr *text_l1; + Elf_Shdr *data_a_l1; + Elf_Shdr *bss_a_l1; + Elf_Shdr *data_b_l1; + Elf_Shdr *bss_b_l1; + Elf_Shdr *text_l2; + Elf_Shdr *data_l2; + Elf_Shdr *bss_l2; +}; +#endif /* _ASM_BFIN_MODULE_H */ diff --git a/kernel/arch/blackfin/include/asm/nand.h b/kernel/arch/blackfin/include/asm/nand.h new file mode 100644 index 000000000..256c50d8d --- /dev/null +++ b/kernel/arch/blackfin/include/asm/nand.h @@ -0,0 +1,40 @@ +/* + * BF5XX - NAND flash controller platform_device info + * + * Copyright 2007-2008 Analog Devices, Inc. + * + * Licensed under the GPL-2 + */ + +/* struct bf5xx_nand_platform + * + * define a interface between platform board specific code and + * bf54x NFC driver. + * + * nr_partitions = number of partitions pointed to be partitoons (or zero) + * partitions = mtd partition list + */ + +#define NFC_PG_SIZE_OFFSET 9 + +#define NFC_NWIDTH_8 0 +#define NFC_NWIDTH_16 1 +#define NFC_NWIDTH_OFFSET 8 + +#define NFC_RDDLY_OFFSET 4 +#define NFC_WRDLY_OFFSET 0 + +#define NFC_STAT_NBUSY 1 + +struct bf5xx_nand_platform { + /* NAND chip information */ + unsigned short data_width; + + /* RD/WR strobe delay timing information, all times in SCLK cycles */ + unsigned short rd_dly; + unsigned short wr_dly; + + /* NAND MTD partition information */ + int nr_partitions; + struct mtd_partition *partitions; +}; diff --git a/kernel/arch/blackfin/include/asm/nmi.h b/kernel/arch/blackfin/include/asm/nmi.h new file mode 100644 index 000000000..b9caac4fc --- /dev/null +++ b/kernel/arch/blackfin/include/asm/nmi.h @@ -0,0 +1,12 @@ +/* + * Copyright 2010 Analog Devices Inc. + * + * Licensed under the GPL-2 + */ + +#ifndef _BFIN_NMI_H_ +#define _BFIN_NMI_H_ + +#include <linux/nmi.h> + +#endif diff --git a/kernel/arch/blackfin/include/asm/page.h b/kernel/arch/blackfin/include/asm/page.h new file mode 100644 index 000000000..b93474d5b --- /dev/null +++ b/kernel/arch/blackfin/include/asm/page.h @@ -0,0 +1,22 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_PAGE_H +#define _BLACKFIN_PAGE_H + +#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT) +#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT) + +#define VM_DATA_DEFAULT_FLAGS \ + (VM_READ | VM_WRITE | \ + ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + +#include <asm-generic/page.h> +#include <asm-generic/memory_model.h> +#include <asm-generic/getorder.h> + +#endif diff --git a/kernel/arch/blackfin/include/asm/page_offset.h b/kernel/arch/blackfin/include/asm/page_offset.h new file mode 100644 index 000000000..d06a89b89 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/page_offset.h @@ -0,0 +1,11 @@ +/* + * This handles the memory map + * + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifdef CONFIG_BLACKFIN +#define PAGE_OFFSET_RAW 0x00000000 +#endif diff --git a/kernel/arch/blackfin/include/asm/pci.h b/kernel/arch/blackfin/include/asm/pci.h new file mode 100644 index 000000000..c737909fb --- /dev/null +++ b/kernel/arch/blackfin/include/asm/pci.h @@ -0,0 +1,13 @@ +/* Changed from asm-m68k version, Lineo Inc. May 2001 */ + +#ifndef _ASM_BFIN_PCI_H +#define _ASM_BFIN_PCI_H + +#include <asm/scatterlist.h> +#include <asm-generic/pci-dma-compat.h> +#include <asm-generic/pci.h> + +#define PCIBIOS_MIN_IO 0x00001000 +#define PCIBIOS_MIN_MEM 0x10000000 + +#endif /* _ASM_BFIN_PCI_H */ diff --git a/kernel/arch/blackfin/include/asm/pda.h b/kernel/arch/blackfin/include/asm/pda.h new file mode 100644 index 000000000..68d6f6618 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/pda.h @@ -0,0 +1,73 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * Philippe Gerum <rpm@xenomai.org> + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_BLACKFIN_PDA_H +#define _ASM_BLACKFIN_PDA_H + +#include <mach/anomaly.h> + +#ifndef __ASSEMBLY__ + +struct blackfin_pda { /* Per-processor Data Area */ +#ifdef CONFIG_SMP + struct blackfin_pda *next; +#endif + + unsigned long syscfg; +#ifdef CONFIG_SMP + unsigned long imask; /* Current IMASK value */ +#endif + + unsigned long *ipdt; /* Start of switchable I-CPLB table */ + unsigned long *ipdt_swapcount; /* Number of swaps in ipdt */ + unsigned long *dpdt; /* Start of switchable D-CPLB table */ + unsigned long *dpdt_swapcount; /* Number of swaps in dpdt */ + + /* + * Single instructions can have multiple faults, which + * need to be handled by traps.c, in irq5. We store + * the exception cause to ensure we don't miss a + * double fault condition + */ + unsigned long ex_iptr; + unsigned long ex_optr; + unsigned long ex_buf[4]; + unsigned long ex_imask; /* Saved imask from exception */ + unsigned long ex_ipend; /* Saved IPEND from exception */ + unsigned long *ex_stack; /* Exception stack space */ + +#ifdef ANOMALY_05000261 + unsigned long last_cplb_fault_retx; +#endif + unsigned long dcplb_fault_addr; + unsigned long icplb_fault_addr; + unsigned long retx; + unsigned long seqstat; + unsigned int __nmi_count; /* number of times NMI asserted on this CPU */ +#ifdef CONFIG_DEBUG_DOUBLEFAULT + unsigned long dcplb_doublefault_addr; + unsigned long icplb_doublefault_addr; + unsigned long retx_doublefault; + unsigned long seqstat_doublefault; +#endif +}; + +struct blackfin_initial_pda { + void *retx; +#ifdef CONFIG_DEBUG_DOUBLEFAULT + void *dcplb_doublefault_addr; + void *icplb_doublefault_addr; + void *retx_doublefault; + unsigned seqstat_doublefault; +#endif +}; + +extern struct blackfin_pda cpu_pda[]; + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_BLACKFIN_PDA_H */ diff --git a/kernel/arch/blackfin/include/asm/perf_event.h b/kernel/arch/blackfin/include/asm/perf_event.h new file mode 100644 index 000000000..3d2b17163 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/perf_event.h @@ -0,0 +1 @@ +#define MAX_HWEVENTS 2 diff --git a/kernel/arch/blackfin/include/asm/pgtable.h b/kernel/arch/blackfin/include/asm/pgtable.h new file mode 100644 index 000000000..b88a1558b --- /dev/null +++ b/kernel/arch/blackfin/include/asm/pgtable.h @@ -0,0 +1,102 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_PGTABLE_H +#define _BLACKFIN_PGTABLE_H + +#include <asm-generic/4level-fixup.h> + +#include <asm/page.h> +#include <asm/def_LPBlackfin.h> + +typedef pte_t *pte_addr_t; +/* +* Trivial page table functions. +*/ +#define pgd_present(pgd) (1) +#define pgd_none(pgd) (0) +#define pgd_bad(pgd) (0) +#define pgd_clear(pgdp) +#define kern_addr_valid(addr) (1) + +#define pmd_offset(a, b) ((void *)0) +#define pmd_none(x) (!pmd_val(x)) +#define pmd_present(x) (pmd_val(x)) +#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) +#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK) + +#define kern_addr_valid(addr) (1) + +#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */ +#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */ +#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */ +#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */ +#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */ +#define pgprot_noncached(prot) (prot) + +extern void paging_init(void); + +#define __swp_type(x) (0) +#define __swp_offset(x) (0) +#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) + +#define set_pte(pteptr, pteval) (*(pteptr) = pteval) +#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) + +/* + * Page assess control based on Blackfin CPLB management + */ +#define _PAGE_RD (CPLB_USER_RD) +#define _PAGE_WR (CPLB_USER_WR) +#define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR) +#define _PAGE_ACCESSED CPLB_ALL_ACCESS +#define _PAGE_DIRTY (CPLB_DIRTY) + +#define PTE_BIT_FUNC(fn, op) \ + static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; } + +PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD); +PTE_BIT_FUNC(mkread, |= _PAGE_RD); +PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR); +PTE_BIT_FUNC(mkwrite, |= _PAGE_WR); +PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER); +PTE_BIT_FUNC(mkexec, |= _PAGE_USER); +PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY); +PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY); +PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED); +PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED); + +/* + * ZERO_PAGE is a global shared page that is always zero: used + * for zero-mapped memory areas etc.. + */ +#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page) +extern char empty_zero_page[]; + +#define swapper_pg_dir ((pgd_t *) 0) +/* + * No page table caches to initialise. + */ +#define pgtable_cache_init() do { } while (0) + +/* + * All 32bit addresses are effectively valid for vmalloc... + * Sort of meaningless for non-VM targets. + */ +#define VMALLOC_START 0 +#define VMALLOC_END 0xffffffff + +/* provide a special get_unmapped_area for framebuffer mmaps of nommu */ +extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, + unsigned long, unsigned long, + unsigned long); +#define HAVE_ARCH_FB_UNMAPPED_AREA + +#include <asm-generic/pgtable.h> + +#endif /* _BLACKFIN_PGTABLE_H */ diff --git a/kernel/arch/blackfin/include/asm/pm.h b/kernel/arch/blackfin/include/asm/pm.h new file mode 100644 index 000000000..f72239bf3 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/pm.h @@ -0,0 +1,31 @@ +/* + * Blackfin bf609 power management + * + * Copyright 2011 Analog Devices Inc. + * + * Licensed under the GPL-2 + */ + +#ifndef __PM_H__ +#define __PM_H__ + +#include <linux/suspend.h> + +struct bfin_cpu_pm_fns { + void (*save)(unsigned long *); + void (*restore)(unsigned long *); + int (*valid)(suspend_state_t state); + void (*enter)(suspend_state_t state); + int (*prepare)(void); + void (*finish)(void); +}; + +extern struct bfin_cpu_pm_fns *bfin_cpu_pm; + +# ifdef CONFIG_BFIN_COREB +void bfin_coreb_start(void); +void bfin_coreb_stop(void); +void bfin_coreb_reset(void); +# endif + +#endif diff --git a/kernel/arch/blackfin/include/asm/portmux.h b/kernel/arch/blackfin/include/asm/portmux.h new file mode 100644 index 000000000..c8f093941 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/portmux.h @@ -0,0 +1,1204 @@ +/* + * Common header file for Blackfin family of processors + * + * Copyright 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _PORTMUX_H_ +#define _PORTMUX_H_ + +#define P_IDENT(x) ((x) & 0x1FF) +#define P_FUNCT(x) (((x) & 0x3) << 9) +#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3) +#define P_DEFINED 0x8000 +#define P_UNDEF 0x4000 +#define P_MAYSHARE 0x2000 +#define P_DONTCARE 0x1000 + +#ifdef CONFIG_PINCTRL +int bfin_internal_set_wake(unsigned int irq, unsigned int state); + +#define gpio_pint_regs bfin_pint_regs +#define adi_internal_set_wake bfin_internal_set_wake + +#define peripheral_request(per, label) (0) +#define peripheral_free(per) +#define peripheral_request_list(per, label) (0) +#define peripheral_free_list(per) +#else +int peripheral_request(unsigned short per, const char *label); +void peripheral_free(unsigned short per); +int peripheral_request_list(const unsigned short per[], const char *label); +void peripheral_free_list(const unsigned short per[]); +#endif + +#include <linux/err.h> +#include <linux/pinctrl/pinctrl.h> +#include <mach/portmux.h> +#include <mach/gpio.h> + +#ifndef P_SPORT2_TFS +#define P_SPORT2_TFS P_UNDEF +#endif + +#ifndef P_SPORT2_DTSEC +#define P_SPORT2_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT2_DTPRI +#define P_SPORT2_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT2_TSCLK +#define P_SPORT2_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT2_RFS +#define P_SPORT2_RFS P_UNDEF +#endif + +#ifndef P_SPORT2_DRSEC +#define P_SPORT2_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT2_DRPRI +#define P_SPORT2_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT2_RSCLK +#define P_SPORT2_RSCLK P_UNDEF +#endif + +#ifndef P_SPORT3_TFS +#define P_SPORT3_TFS P_UNDEF +#endif + +#ifndef P_SPORT3_DTSEC +#define P_SPORT3_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT3_DTPRI +#define P_SPORT3_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT3_TSCLK +#define P_SPORT3_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT3_RFS +#define P_SPORT3_RFS P_UNDEF +#endif + +#ifndef P_SPORT3_DRSEC +#define P_SPORT3_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT3_DRPRI +#define P_SPORT3_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT3_RSCLK +#define P_SPORT3_RSCLK P_UNDEF +#endif + +#ifndef P_TMR4 +#define P_TMR4 P_UNDEF +#endif + +#ifndef P_TMR5 +#define P_TMR5 P_UNDEF +#endif + +#ifndef P_TMR6 +#define P_TMR6 P_UNDEF +#endif + +#ifndef P_TMR7 +#define P_TMR7 P_UNDEF +#endif + +#ifndef P_TWI1_SCL +#define P_TWI1_SCL P_UNDEF +#endif + +#ifndef P_TWI1_SDA +#define P_TWI1_SDA P_UNDEF +#endif + +#ifndef P_UART3_RTS +#define P_UART3_RTS P_UNDEF +#endif + +#ifndef P_UART3_CTS +#define P_UART3_CTS P_UNDEF +#endif + +#ifndef P_UART2_TX +#define P_UART2_TX P_UNDEF +#endif + +#ifndef P_UART2_RX +#define P_UART2_RX P_UNDEF +#endif + +#ifndef P_UART3_TX +#define P_UART3_TX P_UNDEF +#endif + +#ifndef P_UART3_RX +#define P_UART3_RX P_UNDEF +#endif + +#ifndef P_SPI2_SS +#define P_SPI2_SS P_UNDEF +#endif + +#ifndef P_SPI2_SSEL1 +#define P_SPI2_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL2 +#define P_SPI2_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL3 +#define P_SPI2_SSEL3 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL4 +#define P_SPI2_SSEL4 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL5 +#define P_SPI2_SSEL5 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL6 +#define P_SPI2_SSEL6 P_UNDEF +#endif + +#ifndef P_SPI2_SSEL7 +#define P_SPI2_SSEL7 P_UNDEF +#endif + +#ifndef P_SPI2_SCK +#define P_SPI2_SCK P_UNDEF +#endif + +#ifndef P_SPI2_MOSI +#define P_SPI2_MOSI P_UNDEF +#endif + +#ifndef P_SPI2_MISO +#define P_SPI2_MISO P_UNDEF +#endif + +#ifndef P_TMR0 +#define P_TMR0 P_UNDEF +#endif + +#ifndef P_TMR1 +#define P_TMR1 P_UNDEF +#endif + +#ifndef P_TMR2 +#define P_TMR2 P_UNDEF +#endif + +#ifndef P_TMR3 +#define P_TMR3 P_UNDEF +#endif + +#ifndef P_SPORT0_TFS +#define P_SPORT0_TFS P_UNDEF +#endif + +#ifndef P_SPORT0_DTSEC +#define P_SPORT0_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT0_DTPRI +#define P_SPORT0_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT0_TSCLK +#define P_SPORT0_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT0_RFS +#define P_SPORT0_RFS P_UNDEF +#endif + +#ifndef P_SPORT0_DRSEC +#define P_SPORT0_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT0_DRPRI +#define P_SPORT0_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT0_RSCLK +#define P_SPORT0_RSCLK P_UNDEF +#endif + +#ifndef P_SD_D0 +#define P_SD_D0 P_UNDEF +#endif + +#ifndef P_SD_D1 +#define P_SD_D1 P_UNDEF +#endif + +#ifndef P_SD_D2 +#define P_SD_D2 P_UNDEF +#endif + +#ifndef P_SD_D3 +#define P_SD_D3 P_UNDEF +#endif + +#ifndef P_SD_CLK +#define P_SD_CLK P_UNDEF +#endif + +#ifndef P_SD_CMD +#define P_SD_CMD P_UNDEF +#endif + +#ifndef P_MMCLK +#define P_MMCLK P_UNDEF +#endif + +#ifndef P_MBCLK +#define P_MBCLK P_UNDEF +#endif + +#ifndef P_PPI1_D0 +#define P_PPI1_D0 P_UNDEF +#endif + +#ifndef P_PPI1_D1 +#define P_PPI1_D1 P_UNDEF +#endif + +#ifndef P_PPI1_D2 +#define P_PPI1_D2 P_UNDEF +#endif + +#ifndef P_PPI1_D3 +#define P_PPI1_D3 P_UNDEF +#endif + +#ifndef P_PPI1_D4 +#define P_PPI1_D4 P_UNDEF +#endif + +#ifndef P_PPI1_D5 +#define P_PPI1_D5 P_UNDEF +#endif + +#ifndef P_PPI1_D6 +#define P_PPI1_D6 P_UNDEF +#endif + +#ifndef P_PPI1_D7 +#define P_PPI1_D7 P_UNDEF +#endif + +#ifndef P_PPI1_D8 +#define P_PPI1_D8 P_UNDEF +#endif + +#ifndef P_PPI1_D9 +#define P_PPI1_D9 P_UNDEF +#endif + +#ifndef P_PPI1_D10 +#define P_PPI1_D10 P_UNDEF +#endif + +#ifndef P_PPI1_D11 +#define P_PPI1_D11 P_UNDEF +#endif + +#ifndef P_PPI1_D12 +#define P_PPI1_D12 P_UNDEF +#endif + +#ifndef P_PPI1_D13 +#define P_PPI1_D13 P_UNDEF +#endif + +#ifndef P_PPI1_D14 +#define P_PPI1_D14 P_UNDEF +#endif + +#ifndef P_PPI1_D15 +#define P_PPI1_D15 P_UNDEF +#endif + +#ifndef P_HOST_D8 +#define P_HOST_D8 P_UNDEF +#endif + +#ifndef P_HOST_D9 +#define P_HOST_D9 P_UNDEF +#endif + +#ifndef P_HOST_D10 +#define P_HOST_D10 P_UNDEF +#endif + +#ifndef P_HOST_D11 +#define P_HOST_D11 P_UNDEF +#endif + +#ifndef P_HOST_D12 +#define P_HOST_D12 P_UNDEF +#endif + +#ifndef P_HOST_D13 +#define P_HOST_D13 P_UNDEF +#endif + +#ifndef P_HOST_D14 +#define P_HOST_D14 P_UNDEF +#endif + +#ifndef P_HOST_D15 +#define P_HOST_D15 P_UNDEF +#endif + +#ifndef P_HOST_D0 +#define P_HOST_D0 P_UNDEF +#endif + +#ifndef P_HOST_D1 +#define P_HOST_D1 P_UNDEF +#endif + +#ifndef P_HOST_D2 +#define P_HOST_D2 P_UNDEF +#endif + +#ifndef P_HOST_D3 +#define P_HOST_D3 P_UNDEF +#endif + +#ifndef P_HOST_D4 +#define P_HOST_D4 P_UNDEF +#endif + +#ifndef P_HOST_D5 +#define P_HOST_D5 P_UNDEF +#endif + +#ifndef P_HOST_D6 +#define P_HOST_D6 P_UNDEF +#endif + +#ifndef P_HOST_D7 +#define P_HOST_D7 P_UNDEF +#endif + +#ifndef P_SPORT1_TFS +#define P_SPORT1_TFS P_UNDEF +#endif + +#ifndef P_SPORT1_DTSEC +#define P_SPORT1_DTSEC P_UNDEF +#endif + +#ifndef P_SPORT1_DTPRI +#define P_SPORT1_DTPRI P_UNDEF +#endif + +#ifndef P_SPORT1_TSCLK +#define P_SPORT1_TSCLK P_UNDEF +#endif + +#ifndef P_SPORT1_RFS +#define P_SPORT1_RFS P_UNDEF +#endif + +#ifndef P_SPORT1_DRSEC +#define P_SPORT1_DRSEC P_UNDEF +#endif + +#ifndef P_SPORT1_DRPRI +#define P_SPORT1_DRPRI P_UNDEF +#endif + +#ifndef P_SPORT1_RSCLK +#define P_SPORT1_RSCLK P_UNDEF +#endif + +#ifndef P_PPI2_D0 +#define P_PPI2_D0 P_UNDEF +#endif + +#ifndef P_PPI2_D1 +#define P_PPI2_D1 P_UNDEF +#endif + +#ifndef P_PPI2_D2 +#define P_PPI2_D2 P_UNDEF +#endif + +#ifndef P_PPI2_D3 +#define P_PPI2_D3 P_UNDEF +#endif + +#ifndef P_PPI2_D4 +#define P_PPI2_D4 P_UNDEF +#endif + +#ifndef P_PPI2_D5 +#define P_PPI2_D5 P_UNDEF +#endif + +#ifndef P_PPI2_D6 +#define P_PPI2_D6 P_UNDEF +#endif + +#ifndef P_PPI2_D7 +#define P_PPI2_D7 P_UNDEF +#endif + +#ifndef P_PPI0_D18 +#define P_PPI0_D18 P_UNDEF +#endif + +#ifndef P_PPI0_D19 +#define P_PPI0_D19 P_UNDEF +#endif + +#ifndef P_PPI0_D20 +#define P_PPI0_D20 P_UNDEF +#endif + +#ifndef P_PPI0_D21 +#define P_PPI0_D21 P_UNDEF +#endif + +#ifndef P_PPI0_D22 +#define P_PPI0_D22 P_UNDEF +#endif + +#ifndef P_PPI0_D23 +#define P_PPI0_D23 P_UNDEF +#endif + +#ifndef P_KEY_ROW0 +#define P_KEY_ROW0 P_UNDEF +#endif + +#ifndef P_KEY_ROW1 +#define P_KEY_ROW1 P_UNDEF +#endif + +#ifndef P_KEY_ROW2 +#define P_KEY_ROW2 P_UNDEF +#endif + +#ifndef P_KEY_ROW3 +#define P_KEY_ROW3 P_UNDEF +#endif + +#ifndef P_KEY_COL0 +#define P_KEY_COL0 P_UNDEF +#endif + +#ifndef P_KEY_COL1 +#define P_KEY_COL1 P_UNDEF +#endif + +#ifndef P_KEY_COL2 +#define P_KEY_COL2 P_UNDEF +#endif + +#ifndef P_KEY_COL3 +#define P_KEY_COL3 P_UNDEF +#endif + +#ifndef P_SPI0_SCK +#define P_SPI0_SCK P_UNDEF +#endif + +#ifndef P_SPI0_MISO +#define P_SPI0_MISO P_UNDEF +#endif + +#ifndef P_SPI0_MOSI +#define P_SPI0_MOSI P_UNDEF +#endif + +#ifndef P_SPI0_SS +#define P_SPI0_SS P_UNDEF +#endif + +#ifndef P_SPI0_SSEL1 +#define P_SPI0_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL2 +#define P_SPI0_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL3 +#define P_SPI0_SSEL3 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL4 +#define P_SPI0_SSEL4 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL5 +#define P_SPI0_SSEL5 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL6 +#define P_SPI0_SSEL6 P_UNDEF +#endif + +#ifndef P_SPI0_SSEL7 +#define P_SPI0_SSEL7 P_UNDEF +#endif + +#ifndef P_UART0_TX +#define P_UART0_TX P_UNDEF +#endif + +#ifndef P_UART0_RX +#define P_UART0_RX P_UNDEF +#endif + +#ifndef P_UART1_RTS +#define P_UART1_RTS P_UNDEF +#endif + +#ifndef P_UART1_CTS +#define P_UART1_CTS P_UNDEF +#endif + +#ifndef P_PPI1_CLK +#define P_PPI1_CLK P_UNDEF +#endif + +#ifndef P_PPI1_FS1 +#define P_PPI1_FS1 P_UNDEF +#endif + +#ifndef P_PPI1_FS2 +#define P_PPI1_FS2 P_UNDEF +#endif + +#ifndef P_TWI0_SCL +#define P_TWI0_SCL P_UNDEF +#endif + +#ifndef P_TWI0_SDA +#define P_TWI0_SDA P_UNDEF +#endif + +#ifndef P_KEY_COL7 +#define P_KEY_COL7 P_UNDEF +#endif + +#ifndef P_KEY_ROW6 +#define P_KEY_ROW6 P_UNDEF +#endif + +#ifndef P_KEY_COL6 +#define P_KEY_COL6 P_UNDEF +#endif + +#ifndef P_KEY_ROW5 +#define P_KEY_ROW5 P_UNDEF +#endif + +#ifndef P_KEY_COL5 +#define P_KEY_COL5 P_UNDEF +#endif + +#ifndef P_KEY_ROW4 +#define P_KEY_ROW4 P_UNDEF +#endif + +#ifndef P_KEY_COL4 +#define P_KEY_COL4 P_UNDEF +#endif + +#ifndef P_KEY_ROW7 +#define P_KEY_ROW7 P_UNDEF +#endif + +#ifndef P_PPI0_D0 +#define P_PPI0_D0 P_UNDEF +#endif + +#ifndef P_PPI0_D1 +#define P_PPI0_D1 P_UNDEF +#endif + +#ifndef P_PPI0_D2 +#define P_PPI0_D2 P_UNDEF +#endif + +#ifndef P_PPI0_D3 +#define P_PPI0_D3 P_UNDEF +#endif + +#ifndef P_PPI0_D4 +#define P_PPI0_D4 P_UNDEF +#endif + +#ifndef P_PPI0_D5 +#define P_PPI0_D5 P_UNDEF +#endif + +#ifndef P_PPI0_D6 +#define P_PPI0_D6 P_UNDEF +#endif + +#ifndef P_PPI0_D7 +#define P_PPI0_D7 P_UNDEF +#endif + +#ifndef P_PPI0_D8 +#define P_PPI0_D8 P_UNDEF +#endif + +#ifndef P_PPI0_D9 +#define P_PPI0_D9 P_UNDEF +#endif + +#ifndef P_PPI0_D10 +#define P_PPI0_D10 P_UNDEF +#endif + +#ifndef P_PPI0_D11 +#define P_PPI0_D11 P_UNDEF +#endif + +#ifndef P_PPI0_D12 +#define P_PPI0_D12 P_UNDEF +#endif + +#ifndef P_PPI0_D13 +#define P_PPI0_D13 P_UNDEF +#endif + +#ifndef P_PPI0_D14 +#define P_PPI0_D14 P_UNDEF +#endif + +#ifndef P_PPI0_D15 +#define P_PPI0_D15 P_UNDEF +#endif + +#ifndef P_ATAPI_D0A +#define P_ATAPI_D0A P_UNDEF +#endif + +#ifndef P_ATAPI_D1A +#define P_ATAPI_D1A P_UNDEF +#endif + +#ifndef P_ATAPI_D2A +#define P_ATAPI_D2A P_UNDEF +#endif + +#ifndef P_ATAPI_D3A +#define P_ATAPI_D3A P_UNDEF +#endif + +#ifndef P_ATAPI_D4A +#define P_ATAPI_D4A P_UNDEF +#endif + +#ifndef P_ATAPI_D5A +#define P_ATAPI_D5A P_UNDEF +#endif + +#ifndef P_ATAPI_D6A +#define P_ATAPI_D6A P_UNDEF +#endif + +#ifndef P_ATAPI_D7A +#define P_ATAPI_D7A P_UNDEF +#endif + +#ifndef P_ATAPI_D8A +#define P_ATAPI_D8A P_UNDEF +#endif + +#ifndef P_ATAPI_D9A +#define P_ATAPI_D9A P_UNDEF +#endif + +#ifndef P_ATAPI_D10A +#define P_ATAPI_D10A P_UNDEF +#endif + +#ifndef P_ATAPI_D11A +#define P_ATAPI_D11A P_UNDEF +#endif + +#ifndef P_ATAPI_D12A +#define P_ATAPI_D12A P_UNDEF +#endif + +#ifndef P_ATAPI_D13A +#define P_ATAPI_D13A P_UNDEF +#endif + +#ifndef P_ATAPI_D14A +#define P_ATAPI_D14A P_UNDEF +#endif + +#ifndef P_ATAPI_D15A +#define P_ATAPI_D15A P_UNDEF +#endif + +#ifndef P_PPI0_CLK +#define P_PPI0_CLK P_UNDEF +#endif + +#ifndef P_PPI0_FS1 +#define P_PPI0_FS1 P_UNDEF +#endif + +#ifndef P_PPI0_FS2 +#define P_PPI0_FS2 P_UNDEF +#endif + +#ifndef P_PPI0_D16 +#define P_PPI0_D16 P_UNDEF +#endif + +#ifndef P_PPI0_D17 +#define P_PPI0_D17 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL1 +#define P_SPI1_SSEL1 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL2 +#define P_SPI1_SSEL2 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL3 +#define P_SPI1_SSEL3 P_UNDEF +#endif + + +#ifndef P_SPI1_SSEL4 +#define P_SPI1_SSEL4 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL5 +#define P_SPI1_SSEL5 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL6 +#define P_SPI1_SSEL6 P_UNDEF +#endif + +#ifndef P_SPI1_SSEL7 +#define P_SPI1_SSEL7 P_UNDEF +#endif + +#ifndef P_SPI1_SCK +#define P_SPI1_SCK P_UNDEF +#endif + +#ifndef P_SPI1_MISO +#define P_SPI1_MISO P_UNDEF +#endif + +#ifndef P_SPI1_MOSI +#define P_SPI1_MOSI P_UNDEF +#endif + +#ifndef P_SPI1_SS +#define P_SPI1_SS P_UNDEF +#endif + +#ifndef P_CAN0_TX +#define P_CAN0_TX P_UNDEF +#endif + +#ifndef P_CAN0_RX +#define P_CAN0_RX P_UNDEF +#endif + +#ifndef P_CAN1_TX +#define P_CAN1_TX P_UNDEF +#endif + +#ifndef P_CAN1_RX +#define P_CAN1_RX P_UNDEF +#endif + +#ifndef P_ATAPI_A0A +#define P_ATAPI_A0A P_UNDEF +#endif + +#ifndef P_ATAPI_A1A +#define P_ATAPI_A1A P_UNDEF +#endif + +#ifndef P_ATAPI_A2A +#define P_ATAPI_A2A P_UNDEF +#endif + +#ifndef P_HOST_CE +#define P_HOST_CE P_UNDEF +#endif + +#ifndef P_HOST_RD +#define P_HOST_RD P_UNDEF +#endif + +#ifndef P_HOST_WR +#define P_HOST_WR P_UNDEF +#endif + +#ifndef P_MTXONB +#define P_MTXONB P_UNDEF +#endif + +#ifndef P_PPI2_FS2 +#define P_PPI2_FS2 P_UNDEF +#endif + +#ifndef P_PPI2_FS1 +#define P_PPI2_FS1 P_UNDEF +#endif + +#ifndef P_PPI2_CLK +#define P_PPI2_CLK P_UNDEF +#endif + +#ifndef P_CNT_CZM +#define P_CNT_CZM P_UNDEF +#endif + +#ifndef P_UART1_TX +#define P_UART1_TX P_UNDEF +#endif + +#ifndef P_UART1_RX +#define P_UART1_RX P_UNDEF +#endif + +#ifndef P_ATAPI_RESET +#define P_ATAPI_RESET P_UNDEF +#endif + +#ifndef P_HOST_ADDR +#define P_HOST_ADDR P_UNDEF +#endif + +#ifndef P_HOST_ACK +#define P_HOST_ACK P_UNDEF +#endif + +#ifndef P_MTX +#define P_MTX P_UNDEF +#endif + +#ifndef P_MRX +#define P_MRX P_UNDEF +#endif + +#ifndef P_MRXONB +#define P_MRXONB P_UNDEF +#endif + +#ifndef P_A4 +#define P_A4 P_UNDEF +#endif + +#ifndef P_A5 +#define P_A5 P_UNDEF +#endif + +#ifndef P_A6 +#define P_A6 P_UNDEF +#endif + +#ifndef P_A7 +#define P_A7 P_UNDEF +#endif + +#ifndef P_A8 +#define P_A8 P_UNDEF +#endif + +#ifndef P_A9 +#define P_A9 P_UNDEF +#endif + +#ifndef P_PPI1_FS3 +#define P_PPI1_FS3 P_UNDEF +#endif + +#ifndef P_PPI2_FS3 +#define P_PPI2_FS3 P_UNDEF +#endif + +#ifndef P_TMR8 +#define P_TMR8 P_UNDEF +#endif + +#ifndef P_TMR9 +#define P_TMR9 P_UNDEF +#endif + +#ifndef P_TMR10 +#define P_TMR10 P_UNDEF +#endif +#ifndef P_TMR11 +#define P_TMR11 P_UNDEF +#endif + +#ifndef P_DMAR0 +#define P_DMAR0 P_UNDEF +#endif + +#ifndef P_DMAR1 +#define P_DMAR1 P_UNDEF +#endif + +#ifndef P_PPI0_FS3 +#define P_PPI0_FS3 P_UNDEF +#endif + +#ifndef P_CNT_CDG +#define P_CNT_CDG P_UNDEF +#endif + +#ifndef P_CNT_CUD +#define P_CNT_CUD P_UNDEF +#endif + +#ifndef P_A10 +#define P_A10 P_UNDEF +#endif + +#ifndef P_A11 +#define P_A11 P_UNDEF +#endif + +#ifndef P_A12 +#define P_A12 P_UNDEF +#endif + +#ifndef P_A13 +#define P_A13 P_UNDEF +#endif + +#ifndef P_A14 +#define P_A14 P_UNDEF +#endif + +#ifndef P_A15 +#define P_A15 P_UNDEF +#endif + +#ifndef P_A16 +#define P_A16 P_UNDEF +#endif + +#ifndef P_A17 +#define P_A17 P_UNDEF +#endif + +#ifndef P_A18 +#define P_A18 P_UNDEF +#endif + +#ifndef P_A19 +#define P_A19 P_UNDEF +#endif + +#ifndef P_A20 +#define P_A20 P_UNDEF +#endif + +#ifndef P_A21 +#define P_A21 P_UNDEF +#endif + +#ifndef P_A22 +#define P_A22 P_UNDEF +#endif + +#ifndef P_A23 +#define P_A23 P_UNDEF +#endif + +#ifndef P_A24 +#define P_A24 P_UNDEF +#endif + +#ifndef P_A25 +#define P_A25 P_UNDEF +#endif + +#ifndef P_NOR_CLK +#define P_NOR_CLK P_UNDEF +#endif + +#ifndef P_TMRCLK +#define P_TMRCLK P_UNDEF +#endif + +#ifndef P_AMC_ARDY_NOR_WAIT +#define P_AMC_ARDY_NOR_WAIT P_UNDEF +#endif + +#ifndef P_NAND_CE +#define P_NAND_CE P_UNDEF +#endif + +#ifndef P_NAND_RB +#define P_NAND_RB P_UNDEF +#endif + +#ifndef P_ATAPI_DIOR +#define P_ATAPI_DIOR P_UNDEF +#endif + +#ifndef P_ATAPI_DIOW +#define P_ATAPI_DIOW P_UNDEF +#endif + +#ifndef P_ATAPI_CS0 +#define P_ATAPI_CS0 P_UNDEF +#endif + +#ifndef P_ATAPI_CS1 +#define P_ATAPI_CS1 P_UNDEF +#endif + +#ifndef P_ATAPI_DMACK +#define P_ATAPI_DMACK P_UNDEF +#endif + +#ifndef P_ATAPI_DMARQ +#define P_ATAPI_DMARQ P_UNDEF +#endif + +#ifndef P_ATAPI_INTRQ +#define P_ATAPI_INTRQ P_UNDEF +#endif + +#ifndef P_ATAPI_IORDY +#define P_ATAPI_IORDY P_UNDEF +#endif + +#ifndef P_AMC_BR +#define P_AMC_BR P_UNDEF +#endif + +#ifndef P_AMC_BG +#define P_AMC_BG P_UNDEF +#endif + +#ifndef P_AMC_BGH +#define P_AMC_BGH P_UNDEF +#endif + +/* EMAC */ + +#ifndef P_MII0_ETxD0 +#define P_MII0_ETxD0 P_UNDEF +#endif + +#ifndef P_MII0_ETxD1 +#define P_MII0_ETxD1 P_UNDEF +#endif + +#ifndef P_MII0_ETxD2 +#define P_MII0_ETxD2 P_UNDEF +#endif + +#ifndef P_MII0_ETxD3 +#define P_MII0_ETxD3 P_UNDEF +#endif + +#ifndef P_MII0_ETxEN +#define P_MII0_ETxEN P_UNDEF +#endif + +#ifndef P_MII0_TxCLK +#define P_MII0_TxCLK P_UNDEF +#endif + +#ifndef P_MII0_PHYINT +#define P_MII0_PHYINT P_UNDEF +#endif + +#ifndef P_MII0_COL +#define P_MII0_COL P_UNDEF +#endif + +#ifndef P_MII0_ERxD0 +#define P_MII0_ERxD0 P_UNDEF +#endif + +#ifndef P_MII0_ERxD1 +#define P_MII0_ERxD1 P_UNDEF +#endif + +#ifndef P_MII0_ERxD2 +#define P_MII0_ERxD2 P_UNDEF +#endif + +#ifndef P_MII0_ERxD3 +#define P_MII0_ERxD3 P_UNDEF +#endif + +#ifndef P_MII0_ERxDV +#define P_MII0_ERxDV P_UNDEF +#endif + +#ifndef P_MII0_ERxCLK +#define P_MII0_ERxCLK P_UNDEF +#endif + +#ifndef P_MII0_ERxER +#define P_MII0_ERxER P_UNDEF +#endif + +#ifndef P_MII0_CRS +#define P_MII0_CRS P_UNDEF +#endif + +#ifndef P_RMII0_REF_CLK +#define P_RMII0_REF_CLK P_UNDEF +#endif + +#ifndef P_RMII0_MDINT +#define P_RMII0_MDINT P_UNDEF +#endif + +#ifndef P_RMII0_CRS_DV +#define P_RMII0_CRS_DV P_UNDEF +#endif + +#ifndef P_MDC +#define P_MDC P_UNDEF +#endif + +#ifndef P_MDIO +#define P_MDIO P_UNDEF +#endif + +#endif /* _PORTMUX_H_ */ diff --git a/kernel/arch/blackfin/include/asm/processor.h b/kernel/arch/blackfin/include/asm/processor.h new file mode 100644 index 000000000..7acd46653 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/processor.h @@ -0,0 +1,158 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BFIN_PROCESSOR_H +#define __ASM_BFIN_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#include <asm/ptrace.h> +#include <mach/blackfin.h> + +static inline unsigned long rdusp(void) +{ + unsigned long usp; + + __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp)); + return usp; +} + +static inline void wrusp(unsigned long usp) +{ + __asm__ __volatile__("usp = %0;\n\t"::"da"(usp)); +} + +static inline unsigned long __get_SP(void) +{ + unsigned long sp; + + __asm__ __volatile__("%0 = sp;\n\t" : "=da"(sp)); + return sp; +} + +/* + * User space process size: 1st byte beyond user address space. + * Fairly meaningless on nommu. Parts of user programs can be scattered + * in a lot of places, so just disable this by setting it to 0xFFFFFFFF. + */ +#define TASK_SIZE 0xFFFFFFFF + +#ifdef __KERNEL__ +#define STACK_TOP TASK_SIZE +#endif + +#define TASK_UNMAPPED_BASE 0 + +struct thread_struct { + unsigned long ksp; /* kernel stack pointer */ + unsigned long usp; /* user stack pointer */ + unsigned short seqstat; /* saved status register */ + unsigned long esp0; /* points to SR of stack frame pt_regs */ + unsigned long pc; /* instruction pointer */ + void * debuggerinfo; +}; + +#define INIT_THREAD { \ + sizeof(init_stack) + (unsigned long) init_stack, 0, \ + PS_S, 0, 0 \ +} + +extern void start_thread(struct pt_regs *regs, unsigned long new_ip, + unsigned long new_sp); + +/* Forward declaration, a strange C thing */ +struct task_struct; + +/* Free all resources held by a thread. */ +static inline void release_thread(struct task_struct *dead_task) +{ +} + +/* + * Free current thread data structures etc.. + */ +static inline void exit_thread(void) +{ +} + +/* + * Return saved PC of a blocked thread. + */ +#define thread_saved_pc(tsk) (tsk->thread.pc) + +unsigned long get_wchan(struct task_struct *p); + +#define KSTK_EIP(tsk) \ + ({ \ + unsigned long eip = 0; \ + if ((tsk)->thread.esp0 > PAGE_SIZE && \ + MAP_NR((tsk)->thread.esp0) < max_mapnr) \ + eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \ + eip; }) +#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) + +#define cpu_relax() smp_mb() +#define cpu_relax_lowlatency() cpu_relax() + +/* Get the Silicon Revision of the chip */ +static inline uint32_t __pure bfin_revid(void) +{ + /* Always use CHIPID, to work around ANOMALY_05000234 */ + uint32_t revid = (bfin_read_CHIPID() & CHIPID_VERSION) >> 28; + +#ifdef _BOOTROM_GET_DXE_ADDRESS_TWI + /* + * ANOMALY_05000364 + * Incorrect Revision Number in DSPID Register + */ + if (ANOMALY_05000364 && + bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI) == 0x2796) + revid = 1; +#endif + + return revid; +} + +static inline uint16_t __pure bfin_cpuid(void) +{ + return (bfin_read_CHIPID() & CHIPID_FAMILY) >> 12; +} + +static inline uint32_t __pure bfin_dspid(void) +{ + return bfin_read_DSPID(); +} + +#define blackfin_core_id() (bfin_dspid() & 0xff) + +static inline uint32_t __pure bfin_compiled_revid(void) +{ +#if defined(CONFIG_BF_REV_0_0) + return 0; +#elif defined(CONFIG_BF_REV_0_1) + return 1; +#elif defined(CONFIG_BF_REV_0_2) + return 2; +#elif defined(CONFIG_BF_REV_0_3) + return 3; +#elif defined(CONFIG_BF_REV_0_4) + return 4; +#elif defined(CONFIG_BF_REV_0_5) + return 5; +#elif defined(CONFIG_BF_REV_0_6) + return 6; +#elif defined(CONFIG_BF_REV_ANY) + return 0xffff; +#else + return -1; +#endif +} + +#endif diff --git a/kernel/arch/blackfin/include/asm/pseudo_instructions.h b/kernel/arch/blackfin/include/asm/pseudo_instructions.h new file mode 100644 index 000000000..b00adfa08 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/pseudo_instructions.h @@ -0,0 +1,18 @@ +/* + * header file for pseudo instructions + * + * Copyright 2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_PSEUDO_ +#define _BLACKFIN_PSEUDO_ + +#include <linux/types.h> +#include <asm/ptrace.h> + +extern bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode); +extern bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode); + +#endif diff --git a/kernel/arch/blackfin/include/asm/ptrace.h b/kernel/arch/blackfin/include/asm/ptrace.h new file mode 100644 index 000000000..c00491594 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/ptrace.h @@ -0,0 +1,42 @@ +/* + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ +#ifndef _BFIN_PTRACE_H +#define _BFIN_PTRACE_H + +#include <uapi/asm/ptrace.h> + +#ifndef __ASSEMBLY__ + +/* user_mode returns true if only one bit is set in IPEND, other than the + master interrupt enable. */ +#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1))) + +#define arch_has_single_step() (1) +/* common code demands this function */ +#define ptrace_disable(child) user_disable_single_step(child) +#define current_user_stack_pointer() rdusp() + +extern int is_user_addr_valid(struct task_struct *child, + unsigned long start, unsigned long len); + +/* + * Get the address of the live pt_regs for the specified task. + * These are saved onto the top kernel stack when the process + * is not running. + * + * Note: if a user thread is execve'd from kernel space, the + * kernel stack will not be empty on entry to the kernel, so + * ptracing these tasks will fail. + */ +#define task_pt_regs(task) \ + (struct pt_regs *) \ + ((unsigned long)task_stack_page(task) + \ + (THREAD_SIZE - sizeof(struct pt_regs))) + +#include <asm-generic/ptrace.h> + +#endif /* __ASSEMBLY__ */ +#endif /* _BFIN_PTRACE_H */ diff --git a/kernel/arch/blackfin/include/asm/reboot.h b/kernel/arch/blackfin/include/asm/reboot.h new file mode 100644 index 000000000..ae1e36329 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/reboot.h @@ -0,0 +1,20 @@ +/* + * reboot.h - shutdown/reboot header + * + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_REBOOT_H__ +#define __ASM_REBOOT_H__ + +/* optional board specific hooks */ +extern void native_machine_restart(char *cmd); +extern void native_machine_halt(void); +extern void native_machine_power_off(void); + +/* common reboot workarounds */ +extern void bfin_reset_boot_spi_cs(unsigned short pin); + +#endif diff --git a/kernel/arch/blackfin/include/asm/rwlock.h b/kernel/arch/blackfin/include/asm/rwlock.h new file mode 100644 index 000000000..4a724b378 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/rwlock.h @@ -0,0 +1,6 @@ +#ifndef _ASM_BLACKFIN_RWLOCK_H +#define _ASM_BLACKFIN_RWLOCK_H + +#define RW_LOCK_BIAS 0x01000000 + +#endif diff --git a/kernel/arch/blackfin/include/asm/scb.h b/kernel/arch/blackfin/include/asm/scb.h new file mode 100644 index 000000000..a294cc0d1 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/scb.h @@ -0,0 +1,21 @@ +/* + * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority + * + * Copyright 2012 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#define SCB_SLOT_OFFSET 24 +#define SCB_MI_MAX_SLOT 32 + +struct scb_mi_prio { + unsigned long scb_mi_arbr; + unsigned long scb_mi_arbw; + unsigned char scb_mi_slots; + unsigned char scb_mi_prio[SCB_MI_MAX_SLOT]; +}; + +extern struct scb_mi_prio scb_data[]; + +extern void init_scb(void); diff --git a/kernel/arch/blackfin/include/asm/sections.h b/kernel/arch/blackfin/include/asm/sections.h new file mode 100644 index 000000000..fbd408475 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/sections.h @@ -0,0 +1,67 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_SECTIONS_H +#define _BLACKFIN_SECTIONS_H + +/* only used when MTD_UCLINUX */ +extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size; + +extern unsigned long _ramstart, _ramend, _rambase; +extern unsigned long memory_start, memory_end, physical_mem_end; + +/* + * The weak markings on the lengths might seem weird, but this is required + * in order to make gcc accept the fact that these may actually have a value + * of 0 (since they aren't actually addresses, but sizes of sections). + */ +extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[]; +extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[], + _data_l1_lma[], __weak _data_l1_len[]; +#ifdef CONFIG_ROMKERNEL +extern char _data_lma[], _data_len[], _sinitdata[], _einitdata[], _init_data_lma[], _init_data_len[]; +#endif +extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[], + _data_b_l1_lma[], __weak _data_b_l1_len[]; +extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], + _sbss_l2[], _ebss_l2[], _l2_lma[], __weak _l2_len[]; + +#include <asm/mem_map.h> + +/* Blackfin systems have discontinuous memory map and no virtualized memory */ +static inline int arch_is_kernel_text(unsigned long addr) +{ + return + (L1_CODE_LENGTH && + addr >= (unsigned long)_stext_l1 && + addr < (unsigned long)_etext_l1) + || + (L2_LENGTH && + addr >= (unsigned long)_stext_l2 && + addr < (unsigned long)_etext_l2); +} +#define arch_is_kernel_text(addr) arch_is_kernel_text(addr) + +static inline int arch_is_kernel_data(unsigned long addr) +{ + return + (L1_DATA_A_LENGTH && + addr >= (unsigned long)_sdata_l1 && + addr < (unsigned long)_ebss_l1) + || + (L1_DATA_B_LENGTH && + addr >= (unsigned long)_sdata_b_l1 && + addr < (unsigned long)_ebss_b_l1) + || + (L2_LENGTH && + addr >= (unsigned long)_sdata_l2 && + addr < (unsigned long)_ebss_l2); +} +#define arch_is_kernel_data(addr) arch_is_kernel_data(addr) + +#include <asm-generic/sections.h> + +#endif diff --git a/kernel/arch/blackfin/include/asm/segment.h b/kernel/arch/blackfin/include/asm/segment.h new file mode 100644 index 000000000..f8e1984ff --- /dev/null +++ b/kernel/arch/blackfin/include/asm/segment.h @@ -0,0 +1,13 @@ +/* + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BFIN_SEGMENT_H +#define _BFIN_SEGMENT_H + +#define KERNEL_DS (0x5) +#define USER_DS (0x1) + +#endif /* _BFIN_SEGMENT_H */ diff --git a/kernel/arch/blackfin/include/asm/smp.h b/kernel/arch/blackfin/include/asm/smp.h new file mode 100644 index 000000000..9631598dc --- /dev/null +++ b/kernel/arch/blackfin/include/asm/smp.h @@ -0,0 +1,54 @@ +/* + * Copyright 2007-2009 Analog Devices Inc. + * Philippe Gerum <rpm@xenomai.org> + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BLACKFIN_SMP_H +#define __ASM_BLACKFIN_SMP_H + +#include <linux/kernel.h> +#include <linux/threads.h> +#include <linux/cpumask.h> +#include <linux/cache.h> +#include <asm/blackfin.h> +#include <mach/smp.h> + +#define raw_smp_processor_id() blackfin_core_id() + +extern void bfin_relocate_coreb_l1_mem(void); +extern void arch_send_call_function_single_ipi(int cpu); +extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); + +#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1) +asmlinkage void blackfin_icache_flush_range_l1(unsigned long *ptr); +extern unsigned long blackfin_iflush_l1_entry[NR_CPUS]; +#endif + +struct corelock_slot { + int lock; +}; +extern struct corelock_slot corelock; + +#ifdef __ARCH_SYNC_CORE_ICACHE +extern unsigned long icache_invld_count[NR_CPUS]; +#endif +#ifdef __ARCH_SYNC_CORE_DCACHE +extern unsigned long dcache_invld_count[NR_CPUS]; +#endif + +void smp_icache_flush_range_others(unsigned long start, + unsigned long end); +#ifdef CONFIG_HOTPLUG_CPU +void coreb_die(void); +void cpu_die(void); +void platform_cpu_die(void); +int __cpu_disable(void); +int __cpu_die(unsigned int cpu); +#endif + +void smp_timer_broadcast(const struct cpumask *mask); + + +#endif /* !__ASM_BLACKFIN_SMP_H */ diff --git a/kernel/arch/blackfin/include/asm/spinlock.h b/kernel/arch/blackfin/include/asm/spinlock.h new file mode 100644 index 000000000..490c7caa0 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/spinlock.h @@ -0,0 +1,105 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_SPINLOCK_H +#define __BFIN_SPINLOCK_H + +#ifndef CONFIG_SMP +# include <asm-generic/spinlock.h> +#else + +#include <linux/atomic.h> + +asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr); +asmlinkage void __raw_spin_lock_asm(volatile int *ptr); +asmlinkage int __raw_spin_trylock_asm(volatile int *ptr); +asmlinkage void __raw_spin_unlock_asm(volatile int *ptr); +asmlinkage void __raw_read_lock_asm(volatile int *ptr); +asmlinkage int __raw_read_trylock_asm(volatile int *ptr); +asmlinkage void __raw_read_unlock_asm(volatile int *ptr); +asmlinkage void __raw_write_lock_asm(volatile int *ptr); +asmlinkage int __raw_write_trylock_asm(volatile int *ptr); +asmlinkage void __raw_write_unlock_asm(volatile int *ptr); + +static inline int arch_spin_is_locked(arch_spinlock_t *lock) +{ + return __raw_spin_is_locked_asm(&lock->lock); +} + +static inline void arch_spin_lock(arch_spinlock_t *lock) +{ + __raw_spin_lock_asm(&lock->lock); +} + +#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) + +static inline int arch_spin_trylock(arch_spinlock_t *lock) +{ + return __raw_spin_trylock_asm(&lock->lock); +} + +static inline void arch_spin_unlock(arch_spinlock_t *lock) +{ + __raw_spin_unlock_asm(&lock->lock); +} + +static inline void arch_spin_unlock_wait(arch_spinlock_t *lock) +{ + while (arch_spin_is_locked(lock)) + cpu_relax(); +} + +static inline int arch_read_can_lock(arch_rwlock_t *rw) +{ + return __raw_uncached_fetch_asm(&rw->lock) > 0; +} + +static inline int arch_write_can_lock(arch_rwlock_t *rw) +{ + return __raw_uncached_fetch_asm(&rw->lock) == RW_LOCK_BIAS; +} + +static inline void arch_read_lock(arch_rwlock_t *rw) +{ + __raw_read_lock_asm(&rw->lock); +} + +#define arch_read_lock_flags(lock, flags) arch_read_lock(lock) + +static inline int arch_read_trylock(arch_rwlock_t *rw) +{ + return __raw_read_trylock_asm(&rw->lock); +} + +static inline void arch_read_unlock(arch_rwlock_t *rw) +{ + __raw_read_unlock_asm(&rw->lock); +} + +static inline void arch_write_lock(arch_rwlock_t *rw) +{ + __raw_write_lock_asm(&rw->lock); +} + +#define arch_write_lock_flags(lock, flags) arch_write_lock(lock) + +static inline int arch_write_trylock(arch_rwlock_t *rw) +{ + return __raw_write_trylock_asm(&rw->lock); +} + +static inline void arch_write_unlock(arch_rwlock_t *rw) +{ + __raw_write_unlock_asm(&rw->lock); +} + +#define arch_spin_relax(lock) cpu_relax() +#define arch_read_relax(lock) cpu_relax() +#define arch_write_relax(lock) cpu_relax() + +#endif + +#endif /* !__BFIN_SPINLOCK_H */ diff --git a/kernel/arch/blackfin/include/asm/spinlock_types.h b/kernel/arch/blackfin/include/asm/spinlock_types.h new file mode 100644 index 000000000..1a33608c9 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/spinlock_types.h @@ -0,0 +1,28 @@ +/* + * Copyright 2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_SPINLOCK_TYPES_H +#define __ASM_SPINLOCK_TYPES_H + +#ifndef __LINUX_SPINLOCK_TYPES_H +# error "please don't include this file directly" +#endif + +#include <asm/rwlock.h> + +typedef struct { + volatile unsigned int lock; +} arch_spinlock_t; + +#define __ARCH_SPIN_LOCK_UNLOCKED { 0 } + +typedef struct { + volatile unsigned int lock; +} arch_rwlock_t; + +#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS } + +#endif diff --git a/kernel/arch/blackfin/include/asm/string.h b/kernel/arch/blackfin/include/asm/string.h new file mode 100644 index 000000000..423c099aa --- /dev/null +++ b/kernel/arch/blackfin/include/asm/string.h @@ -0,0 +1,38 @@ +/* + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_STRING_H_ +#define _BLACKFIN_STRING_H_ + +#include <linux/types.h> + +#ifdef __KERNEL__ /* only set these up for kernel code */ + +#define __HAVE_ARCH_STRCPY +extern char *strcpy(char *dest, const char *src); + +#define __HAVE_ARCH_STRNCPY +extern char *strncpy(char *dest, const char *src, size_t n); + +#define __HAVE_ARCH_STRCMP +extern int strcmp(const char *cs, const char *ct); + +#define __HAVE_ARCH_STRNCMP +extern int strncmp(const char *cs, const char *ct, size_t count); + +#define __HAVE_ARCH_MEMSET +extern void *memset(void *s, int c, size_t count); +#define __HAVE_ARCH_MEMCPY +extern void *memcpy(void *d, const void *s, size_t count); +#define __HAVE_ARCH_MEMCMP +extern int memcmp(const void *, const void *, __kernel_size_t); +#define __HAVE_ARCH_MEMCHR +extern void *memchr(const void *s, int c, size_t n); +#define __HAVE_ARCH_MEMMOVE +extern void *memmove(void *dest, const void *src, size_t count); + +#endif /*__KERNEL__*/ +#endif /* _BLACKFIN_STRING_H_ */ diff --git a/kernel/arch/blackfin/include/asm/switch_to.h b/kernel/arch/blackfin/include/asm/switch_to.h new file mode 100644 index 000000000..aaf671be9 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/switch_to.h @@ -0,0 +1,39 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * Tony Kou (tonyko@lineo.ca) + * + * Licensed under the GPL-2 or later + */ + +#ifndef _BLACKFIN_SWITCH_TO_H +#define _BLACKFIN_SWITCH_TO_H + +#define prepare_to_switch() do { } while(0) + +/* + * switch_to(n) should switch tasks to task ptr, first checking that + * ptr isn't the current task, in which case it does nothing. + */ + +#include <asm/l1layout.h> +#include <asm/mem_map.h> + +asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next); + +#ifndef CONFIG_SMP +#define switch_to(prev,next,last) \ +do { \ + memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \ + sizeof *L1_SCRATCH_TASK_INFO); \ + memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \ + sizeof *L1_SCRATCH_TASK_INFO); \ + (last) = resume (prev, next); \ +} while (0) +#else +#define switch_to(prev, next, last) \ +do { \ + (last) = resume(prev, next); \ +} while (0) +#endif + +#endif /* _BLACKFIN_SWITCH_TO_H */ diff --git a/kernel/arch/blackfin/include/asm/syscall.h b/kernel/arch/blackfin/include/asm/syscall.h new file mode 100644 index 000000000..4921a4815 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/syscall.h @@ -0,0 +1,96 @@ +/* + * Magic syscall break down functions + * + * Copyright 2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BLACKFIN_SYSCALL_H__ +#define __ASM_BLACKFIN_SYSCALL_H__ + +/* + * Blackfin syscalls are simple: + * enter: + * p0: syscall number + * r{0,1,2,3,4,5}: syscall args 0,1,2,3,4,5 + * exit: + * r0: return/error value + */ + +#include <linux/err.h> +#include <linux/sched.h> +#include <asm/ptrace.h> + +static inline long +syscall_get_nr(struct task_struct *task, struct pt_regs *regs) +{ + return regs->p0; +} + +static inline void +syscall_rollback(struct task_struct *task, struct pt_regs *regs) +{ + regs->p0 = regs->orig_p0; +} + +static inline long +syscall_get_error(struct task_struct *task, struct pt_regs *regs) +{ + return IS_ERR_VALUE(regs->r0) ? regs->r0 : 0; +} + +static inline long +syscall_get_return_value(struct task_struct *task, struct pt_regs *regs) +{ + return regs->r0; +} + +static inline void +syscall_set_return_value(struct task_struct *task, struct pt_regs *regs, + int error, long val) +{ + regs->r0 = error ? -error : val; +} + +/** + * syscall_get_arguments() + * @task: unused + * @regs: the register layout to extract syscall arguments from + * @i: first syscall argument to extract + * @n: number of syscall arguments to extract + * @args: array to return the syscall arguments in + * + * args[0] gets i'th argument, args[n - 1] gets the i+n-1'th argument + */ +static inline void +syscall_get_arguments(struct task_struct *task, struct pt_regs *regs, + unsigned int i, unsigned int n, unsigned long *args) +{ + /* + * Assume the ptrace layout doesn't change -- r5 is first in memory, + * then r4, ..., then r0. So we simply reverse the ptrace register + * array in memory to store into the args array. + */ + long *aregs = ®s->r0 - i; + + BUG_ON(i > 5 || i + n > 6); + + while (n--) + *args++ = *aregs--; +} + +/* See syscall_get_arguments() comments */ +static inline void +syscall_set_arguments(struct task_struct *task, struct pt_regs *regs, + unsigned int i, unsigned int n, const unsigned long *args) +{ + long *aregs = ®s->r0 - i; + + BUG_ON(i > 5 || i + n > 6); + + while (n--) + *aregs-- = *args++; +} + +#endif diff --git a/kernel/arch/blackfin/include/asm/thread_info.h b/kernel/arch/blackfin/include/asm/thread_info.h new file mode 100644 index 000000000..2966b9385 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/thread_info.h @@ -0,0 +1,100 @@ +/* + * Copyright 2004-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_THREAD_INFO_H +#define _ASM_THREAD_INFO_H + +#include <asm/page.h> +#include <asm/entry.h> +#include <asm/l1layout.h> +#include <linux/compiler.h> + +#ifdef __KERNEL__ + +/* Thread Align Mask to reach to the top of the stack + * for any process + */ +#define ALIGN_PAGE_MASK 0xffffe000 + +/* + * Size of kernel stack for each process. This must be a power of 2... + */ +#define THREAD_SIZE_ORDER 1 +#define THREAD_SIZE 8192 /* 2 pages */ +#define STACK_WARN (THREAD_SIZE/8) + +#ifndef __ASSEMBLY__ + +typedef unsigned long mm_segment_t; + +/* + * low level task data. + * If you change this, change the TI_* offsets below to match. + */ + +struct thread_info { + struct task_struct *task; /* main task structure */ + unsigned long flags; /* low level flags */ + int cpu; /* cpu we're on */ + int preempt_count; /* 0 => preemptable, <0 => BUG */ + mm_segment_t addr_limit; /* address limit */ +#ifndef CONFIG_SMP + struct l1_scratch_task_info l1_task_info; +#endif +}; + +/* + * macros/functions for gaining access to the thread information structure + */ +#define INIT_THREAD_INFO(tsk) \ +{ \ + .task = &tsk, \ + .flags = 0, \ + .cpu = 0, \ + .preempt_count = INIT_PREEMPT_COUNT, \ +} +#define init_thread_info (init_thread_union.thread_info) +#define init_stack (init_thread_union.stack) + +/* Given a task stack pointer, you can find its corresponding + * thread_info structure just by masking it to the THREAD_SIZE + * boundary (currently 8K as you can see above). + */ +__attribute_const__ +static inline struct thread_info *current_thread_info(void) +{ + struct thread_info *ti; + __asm__("%0 = sp;" : "=da"(ti)); + return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1)); +} + +#endif /* __ASSEMBLY__ */ + +/* + * thread information flag bit numbers + */ +#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_MEMDIE 4 /* is terminating due to OOM killer */ +#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ +#define TIF_IRQ_SYNC 7 /* sync pipeline stage */ +#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */ +#define TIF_SINGLESTEP 9 + +/* as above, but as bit values */ +#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) +#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) +#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) +#define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC) +#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) +#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) + +#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ + +#endif /* __KERNEL__ */ + +#endif /* _ASM_THREAD_INFO_H */ diff --git a/kernel/arch/blackfin/include/asm/time.h b/kernel/arch/blackfin/include/asm/time.h new file mode 100644 index 000000000..9ca7db844 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/time.h @@ -0,0 +1,46 @@ +/* + * asm-blackfin/time.h: + * + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_BLACKFIN_TIME_H +#define _ASM_BLACKFIN_TIME_H + +/* + * The way that the Blackfin core timer works is: + * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE) + * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT) + * + * If you take the fastest clock (1ns, or 1GHz to make the math work easier) + * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter + * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need + * to use TSCALE, and program it to zero (which is pass CCLK through). + * If you feel like using it, try to keep HZ * TIMESCALE to some + * value that divides easy (like power of 2). + */ + +#ifndef CONFIG_CPU_FREQ +# define TIME_SCALE 1 +#else +/* + * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . + * Whenever we change the Core Clock frequency changes we immediately + * adjust the Core Timer Presale Register. This way we don't lose time. + */ +#define TIME_SCALE 4 + +# ifdef CONFIG_CYCLES_CLOCKSOURCE +extern unsigned long long __bfin_cycles_off; +extern unsigned int __bfin_cycles_mod; +# endif +#endif + +#if defined(CONFIG_TICKSOURCE_CORETMR) +extern void bfin_coretmr_init(void); +extern void bfin_coretmr_clockevent_init(void); +#endif + +#endif diff --git a/kernel/arch/blackfin/include/asm/timex.h b/kernel/arch/blackfin/include/asm/timex.h new file mode 100644 index 000000000..248aeb066 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/timex.h @@ -0,0 +1,23 @@ +/* + * asm-blackfin/timex.h: cpu cycles! + * + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_BLACKFIN_TIMEX_H +#define _ASM_BLACKFIN_TIMEX_H + +#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */ + +typedef unsigned long long cycles_t; + +static inline cycles_t get_cycles(void) +{ + unsigned long tmp, tmp2; + __asm__ __volatile__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2)); + return tmp | ((cycles_t)tmp2 << 32); +} + +#endif diff --git a/kernel/arch/blackfin/include/asm/tlb.h b/kernel/arch/blackfin/include/asm/tlb.h new file mode 100644 index 000000000..a74ae08af --- /dev/null +++ b/kernel/arch/blackfin/include/asm/tlb.h @@ -0,0 +1,22 @@ +/* + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_TLB_H +#define _BLACKFIN_TLB_H + +#define tlb_start_vma(tlb, vma) do { } while (0) +#define tlb_end_vma(tlb, vma) do { } while (0) +#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) + +/* + * .. because we flush the whole mm when it + * fills up. + */ +#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) + +#include <asm-generic/tlb.h> + +#endif /* _BLACKFIN_TLB_H */ diff --git a/kernel/arch/blackfin/include/asm/tlbflush.h b/kernel/arch/blackfin/include/asm/tlbflush.h new file mode 100644 index 000000000..7c368682c --- /dev/null +++ b/kernel/arch/blackfin/include/asm/tlbflush.h @@ -0,0 +1,2 @@ +#include <asm-generic/tlbflush.h> +#define flush_tlb_kernel_range(s, e) do { } while (0) diff --git a/kernel/arch/blackfin/include/asm/trace.h b/kernel/arch/blackfin/include/asm/trace.h new file mode 100644 index 000000000..33589a29b --- /dev/null +++ b/kernel/arch/blackfin/include/asm/trace.h @@ -0,0 +1,106 @@ +/* + * header file for hardware trace functions + * + * Copyright 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_TRACE_ +#define _BLACKFIN_TRACE_ + +/* Normally, we use ON, but you can't turn on software expansion until + * interrupts subsystem is ready + */ + +#define BFIN_TRACE_INIT ((CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION << 4) | 0x03) +#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND +#define BFIN_TRACE_ON (BFIN_TRACE_INIT | (CONFIG_DEBUG_BFIN_HWTRACE_EXPAND << 2)) +#else +#define BFIN_TRACE_ON (BFIN_TRACE_INIT) +#endif + +#ifndef __ASSEMBLY__ +extern unsigned long trace_buff_offset; +extern unsigned long software_trace_buff[]; +#if defined(CONFIG_DEBUG_VERBOSE) +extern void decode_address(char *buf, unsigned long address); +extern bool get_instruction(unsigned int *val, unsigned short *address); +#else +static inline void decode_address(char *buf, unsigned long address) { } +static inline bool get_instruction(unsigned int *val, unsigned short *address) { return false; } +#endif + +/* Trace Macros for C files */ + +#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON + +#define trace_buffer_init() bfin_write_TBUFCTL(BFIN_TRACE_INIT) + +#define trace_buffer_save(x) \ + do { \ + (x) = bfin_read_TBUFCTL(); \ + bfin_write_TBUFCTL((x) & ~TBUFEN); \ + } while (0) + +#define trace_buffer_restore(x) \ + do { \ + bfin_write_TBUFCTL((x)); \ + } while (0) +#else /* DEBUG_BFIN_HWTRACE_ON */ + +#define trace_buffer_save(x) +#define trace_buffer_restore(x) +#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ + +#else +/* Trace Macros for Assembly files */ + +#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON + +#define trace_buffer_stop(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = 0x1; \ + [preg] = dreg; + +#define trace_buffer_init(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = BFIN_TRACE_INIT; \ + [preg] = dreg; + +#define trace_buffer_save(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = [preg]; \ + [--sp] = dreg; \ + dreg = 0x1; \ + [preg] = dreg; + +#define trace_buffer_restore(preg, dreg) \ + preg.L = LO(TBUFCTL); \ + preg.H = HI(TBUFCTL); \ + dreg = [sp++]; \ + [preg] = dreg; + +#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ + +#define trace_buffer_stop(preg, dreg) +#define trace_buffer_init(preg, dreg) +#define trace_buffer_save(preg, dreg) +#define trace_buffer_restore(preg, dreg) + +#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */ + +#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE +# define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg) +# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg) +#else +# define DEBUG_HWTRACE_SAVE(preg, dreg) +# define DEBUG_HWTRACE_RESTORE(preg, dreg) +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* _BLACKFIN_TRACE_ */ diff --git a/kernel/arch/blackfin/include/asm/traps.h b/kernel/arch/blackfin/include/asm/traps.h new file mode 100644 index 000000000..cec771b81 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/traps.h @@ -0,0 +1,131 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * 2001 Lineo, Inc + * Tony Kou + * 1993 Hamish Macdonald + * + * Licensed under the GPL-2 + */ + +#ifndef _BFIN_TRAPS_H +#define _BFIN_TRAPS_H + +#define VEC_SYS (0) +#define VEC_EXCPT01 (1) +#define VEC_EXCPT02 (2) +#define VEC_EXCPT03 (3) +#define VEC_EXCPT04 (4) +#define VEC_EXCPT05 (5) +#define VEC_EXCPT06 (6) +#define VEC_EXCPT07 (7) +#define VEC_EXCPT08 (8) +#define VEC_EXCPT09 (9) +#define VEC_EXCPT10 (10) +#define VEC_EXCPT11 (11) +#define VEC_EXCPT12 (12) +#define VEC_EXCPT13 (13) +#define VEC_EXCPT14 (14) +#define VEC_EXCPT15 (15) +#define VEC_STEP (16) +#define VEC_OVFLOW (17) +#define VEC_UNDEF_I (33) +#define VEC_ILGAL_I (34) +#define VEC_CPLB_VL (35) +#define VEC_MISALI_D (36) +#define VEC_UNCOV (37) +#define VEC_CPLB_M (38) +#define VEC_CPLB_MHIT (39) +#define VEC_WATCH (40) +#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */ +#define VEC_MISALI_I (42) +#define VEC_CPLB_I_VL (43) +#define VEC_CPLB_I_M (44) +#define VEC_CPLB_I_MHIT (45) +#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ +/* The hardware reserves (63) for future use - we use it to tell our + * normal exception handling code we have a hardware error + */ +#define VEC_HWERR (63) + +#ifndef __ASSEMBLY__ + +#define HWC_x2(level) \ + "System MMR Error\n" \ + level " - An error occurred due to an invalid access to an System MMR location\n" \ + level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \ + level " or a 16-bit register is accessed with a 32-bit instruction.\n" +#define HWC_x3(level) \ + "External Memory Addressing Error\n" +#define EXC_0x04(level) \ + "Unimplmented exception occurred\n" \ + level " - Maybe you forgot to install a custom exception handler?\n" +#define HWC_x12(level) \ + "Performance Monitor Overflow\n" +#define HWC_x18(level) \ + "RAISE 5 instruction\n" \ + level " Software issued a RAISE 5 instruction to invoke the Hardware\n" +#define HWC_default(level) \ + "Reserved\n" +#define EXC_0x03(level) \ + "Application stack overflow\n" \ + level " - Please increase the stack size of the application using elf2flt -s option,\n" \ + level " and/or reduce the stack use of the application.\n" +#define EXC_0x10(level) \ + "Single step\n" \ + level " - When the processor is in single step mode, every instruction\n" \ + level " generates an exception. Primarily used for debugging.\n" +#define EXC_0x11(level) \ + "Exception caused by a trace buffer full condition\n" \ + level " - The processor takes this exception when the trace\n" \ + level " buffer overflows (only when enabled by the Trace Unit Control register).\n" +#define EXC_0x21(level) \ + "Undefined instruction\n" \ + level " - May be used to emulate instructions that are not defined for\n" \ + level " a particular processor implementation.\n" +#define EXC_0x22(level) \ + "Illegal instruction combination\n" \ + level " - See section for multi-issue rules in the Blackfin\n" \ + level " Processor Instruction Set Reference.\n" +#define EXC_0x23(level) \ + "Data access CPLB protection violation\n" \ + level " - Attempted read or write to Supervisor resource,\n" \ + level " or illegal data memory access. \n" +#define EXC_0x24(level) \ + "Data access misaligned address violation\n" \ + level " - Attempted misaligned data memory or data cache access.\n" +#define EXC_0x25(level) \ + "Unrecoverable event\n" \ + level " - For example, an exception generated while processing a previous exception.\n" +#define EXC_0x26(level) \ + "Data access CPLB miss\n" \ + level " - Used by the MMU to signal a CPLB miss on a data access.\n" +#define EXC_0x27(level) \ + "Data access multiple CPLB hits\n" \ + level " - More than one CPLB entry matches data fetch address.\n" +#define EXC_0x28(level) \ + "Program Sequencer Exception caused by an emulation watchpoint match\n" \ + level " - There is a watchpoint match, and one of the EMUSW\n" \ + level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" +#define EXC_0x2A(level) \ + "Instruction fetch misaligned address violation\n" \ + level " - Attempted misaligned instruction cache fetch.\n" +#define EXC_0x2B(level) \ + "CPLB protection violation\n" \ + level " - Illegal instruction fetch access (memory protection violation).\n" +#define EXC_0x2C(level) \ + "Instruction fetch CPLB miss\n" \ + level " - CPLB miss on an instruction fetch.\n" +#define EXC_0x2D(level) \ + "Instruction fetch multiple CPLB hits\n" \ + level " - More than one CPLB entry matches instruction fetch address.\n" +#define EXC_0x2E(level) \ + "Illegal use of supervisor resource\n" \ + level " - Attempted to use a Supervisor register or instruction from User mode.\n" \ + level " Supervisor resources are registers and instructions that are reserved\n" \ + level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \ + level " only instructions.\n" + +extern void double_fault_c(struct pt_regs *fp); + +#endif /* __ASSEMBLY__ */ +#endif /* _BFIN_TRAPS_H */ diff --git a/kernel/arch/blackfin/include/asm/uaccess.h b/kernel/arch/blackfin/include/asm/uaccess.h new file mode 100644 index 000000000..90612a7f2 --- /dev/null +++ b/kernel/arch/blackfin/include/asm/uaccess.h @@ -0,0 +1,275 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + * + * Based on: include/asm-m68knommu/uaccess.h + */ + +#ifndef __BLACKFIN_UACCESS_H +#define __BLACKFIN_UACCESS_H + +/* + * User space memory access functions + */ +#include <linux/sched.h> +#include <linux/mm.h> +#include <linux/string.h> + +#include <asm/segment.h> +#include <asm/sections.h> + +#define get_ds() (KERNEL_DS) +#define get_fs() (current_thread_info()->addr_limit) + +static inline void set_fs(mm_segment_t fs) +{ + current_thread_info()->addr_limit = fs; +} + +#define segment_eq(a, b) ((a) == (b)) + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size)) + +/* + * The fs value determines whether argument validity checking should be + * performed or not. If get_fs() == USER_DS, checking is performed, with + * get_fs() == KERNEL_DS, checking is bypassed. + */ + +#ifndef CONFIG_ACCESS_CHECK +static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; } +#else +extern int _access_ok(unsigned long addr, unsigned long size); +#endif + +/* + * The exception table consists of pairs of addresses: the first is the + * address of an instruction that is allowed to fault, and the second is + * the address at which the program should continue. No registers are + * modified, so it is entirely up to the continuation code to figure out + * what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ + +struct exception_table_entry { + unsigned long insn, fixup; +}; + +/* + * These are the main single-value transfer routines. They automatically + * use the right size if we just have the right pointer type. + */ + +#define put_user(x, p) \ + ({ \ + int _err = 0; \ + typeof(*(p)) _x = (x); \ + typeof(*(p)) __user *_p = (p); \ + if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\ + _err = -EFAULT; \ + } \ + else { \ + switch (sizeof (*(_p))) { \ + case 1: \ + __put_user_asm(_x, _p, B); \ + break; \ + case 2: \ + __put_user_asm(_x, _p, W); \ + break; \ + case 4: \ + __put_user_asm(_x, _p, ); \ + break; \ + case 8: { \ + long _xl, _xh; \ + _xl = ((__force long *)&_x)[0]; \ + _xh = ((__force long *)&_x)[1]; \ + __put_user_asm(_xl, ((__force long __user *)_p)+0, );\ + __put_user_asm(_xh, ((__force long __user *)_p)+1, );\ + } break; \ + default: \ + _err = __put_user_bad(); \ + break; \ + } \ + } \ + _err; \ + }) + +#define __put_user(x, p) put_user(x, p) +static inline int bad_user_access_length(void) +{ + panic("bad_user_access_length"); + return -1; +} + +#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\ + __FILE__, __LINE__, __func__),\ + bad_user_access_length(), (-EFAULT)) + +/* + * Tell gcc we read from memory instead of writing: this is because + * we do not write to any memory gcc knows about, so there are no + * aliasing issues. + */ + +#define __ptr(x) ((unsigned long __force *)(x)) + +#define __put_user_asm(x, p, bhw) \ + __asm__ (#bhw"[%1] = %0;\n\t" \ + : /* no outputs */ \ + :"d" (x), "a" (__ptr(p)) : "memory") + +#define get_user(x, ptr) \ +({ \ + int _err = 0; \ + unsigned long _val = 0; \ + const typeof(*(ptr)) __user *_p = (ptr); \ + const size_t ptr_size = sizeof(*(_p)); \ + if (likely(access_ok(VERIFY_READ, _p, ptr_size))) { \ + BUILD_BUG_ON(ptr_size >= 8); \ + switch (ptr_size) { \ + case 1: \ + __get_user_asm(_val, _p, B, (Z)); \ + break; \ + case 2: \ + __get_user_asm(_val, _p, W, (Z)); \ + break; \ + case 4: \ + __get_user_asm(_val, _p, , ); \ + break; \ + } \ + } else \ + _err = -EFAULT; \ + x = (__force typeof(*(ptr)))_val; \ + _err; \ +}) + +#define __get_user(x, p) get_user(x, p) + +#define __get_user_bad() (bad_user_access_length(), (-EFAULT)) + +#define __get_user_asm(x, ptr, bhw, option) \ +({ \ + __asm__ __volatile__ ( \ + "%0 =" #bhw "[%1]" #option ";" \ + : "=d" (x) \ + : "a" (__ptr(ptr))); \ +}) + +#define __copy_from_user(to, from, n) copy_from_user(to, from, n) +#define __copy_to_user(to, from, n) copy_to_user(to, from, n) +#define __copy_to_user_inatomic __copy_to_user +#define __copy_from_user_inatomic __copy_from_user + +#define copy_to_user_ret(to, from, n, retval) ({ if (copy_to_user(to, from, n))\ + return retval; }) + +#define copy_from_user_ret(to, from, n, retval) ({ if (copy_from_user(to, from, n))\ + return retval; }) + +static inline unsigned long __must_check +copy_from_user(void *to, const void __user *from, unsigned long n) +{ + if (access_ok(VERIFY_READ, from, n)) + memcpy(to, (const void __force *)from, n); + else + return n; + return 0; +} + +static inline unsigned long __must_check +copy_to_user(void __user *to, const void *from, unsigned long n) +{ + if (access_ok(VERIFY_WRITE, to, n)) + memcpy((void __force *)to, from, n); + else + return n; + SSYNC(); + return 0; +} + +/* + * Copy a null terminated string from userspace. + */ + +static inline long __must_check +strncpy_from_user(char *dst, const char __user *src, long count) +{ + char *tmp; + if (!access_ok(VERIFY_READ, src, 1)) + return -EFAULT; + strncpy(dst, (const char __force *)src, count); + for (tmp = dst; *tmp && count > 0; tmp++, count--) ; + return (tmp - dst); +} + +/* + * Get the size of a string in user space. + * src: The string to measure + * n: The maximum valid length + * + * Get the size of a NUL-terminated string in user space. + * + * Returns the size of the string INCLUDING the terminating NUL. + * On exception, returns 0. + * If the string is too long, returns a value greater than n. + */ +static inline long __must_check strnlen_user(const char __user *src, long n) +{ + if (!access_ok(VERIFY_READ, src, 1)) + return 0; + return strnlen((const char __force *)src, n) + 1; +} + +static inline long __must_check strlen_user(const char __user *src) +{ + if (!access_ok(VERIFY_READ, src, 1)) + return 0; + return strlen((const char __force *)src) + 1; +} + +/* + * Zero Userspace + */ + +static inline unsigned long __must_check +__clear_user(void __user *to, unsigned long n) +{ + if (!access_ok(VERIFY_WRITE, to, n)) + return n; + memset((void __force *)to, 0, n); + return 0; +} + +#define clear_user(to, n) __clear_user(to, n) + +/* How to interpret these return values: + * CORE: can be accessed by core load or dma memcpy + * CORE_ONLY: can only be accessed by core load + * DMA: can only be accessed by dma memcpy + * IDMA: can only be accessed by interprocessor dma memcpy (BF561) + * ITEST: can be accessed by isram memcpy or dma memcpy + */ +enum { + BFIN_MEM_ACCESS_CORE = 0, + BFIN_MEM_ACCESS_CORE_ONLY, + BFIN_MEM_ACCESS_DMA, + BFIN_MEM_ACCESS_IDMA, + BFIN_MEM_ACCESS_ITEST, +}; +/** + * bfin_mem_access_type() - what kind of memory access is required + * @addr: the address to check + * @size: number of bytes needed + * @return: <0 is error, >=0 is BFIN_MEM_ACCESS_xxx enum (see above) + */ +int bfin_mem_access_type(unsigned long addr, unsigned long size); + +#endif /* _BLACKFIN_UACCESS_H */ diff --git a/kernel/arch/blackfin/include/asm/unistd.h b/kernel/arch/blackfin/include/asm/unistd.h new file mode 100644 index 000000000..c8c8ff9ef --- /dev/null +++ b/kernel/arch/blackfin/include/asm/unistd.h @@ -0,0 +1,22 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ +#ifndef __ASM_BFIN_UNISTD_H +#define __ASM_BFIN_UNISTD_H + +#include <uapi/asm/unistd.h> + +#define __ARCH_WANT_STAT64 +#define __ARCH_WANT_SYS_ALARM +#define __ARCH_WANT_SYS_GETHOSTNAME +#define __ARCH_WANT_SYS_PAUSE +#define __ARCH_WANT_SYS_TIME +#define __ARCH_WANT_SYS_FADVISE64 +#define __ARCH_WANT_SYS_GETPGRP +#define __ARCH_WANT_SYS_LLSEEK +#define __ARCH_WANT_SYS_NICE +#define __ARCH_WANT_SYS_VFORK + +#endif /* __ASM_BFIN_UNISTD_H */ |