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authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/avr32/mach-at32ap/intc.c
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/avr32/mach-at32ap/intc.c')
-rw-r--r--kernel/arch/avr32/mach-at32ap/intc.c200
1 files changed, 200 insertions, 0 deletions
diff --git a/kernel/arch/avr32/mach-at32ap/intc.c b/kernel/arch/avr32/mach-at32ap/intc.c
new file mode 100644
index 000000000..aaff83cc5
--- /dev/null
+++ b/kernel/arch/avr32/mach-at32ap/intc.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2006, 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/syscore_ops.h>
+#include <linux/export.h>
+
+#include <asm/io.h>
+
+#include "intc.h"
+
+struct intc {
+ void __iomem *regs;
+ struct irq_chip chip;
+#ifdef CONFIG_PM
+ unsigned long suspend_ipr;
+ unsigned long saved_ipr[64];
+#endif
+};
+
+extern struct platform_device at32_intc0_device;
+
+/*
+ * TODO: We may be able to implement mask/unmask by setting IxM flags
+ * in the status register.
+ */
+static void intc_mask_irq(struct irq_data *d)
+{
+
+}
+
+static void intc_unmask_irq(struct irq_data *d)
+{
+
+}
+
+static struct intc intc0 = {
+ .chip = {
+ .name = "intc",
+ .irq_mask = intc_mask_irq,
+ .irq_unmask = intc_unmask_irq,
+ },
+};
+
+/*
+ * All interrupts go via intc at some point.
+ */
+asmlinkage void do_IRQ(int level, struct pt_regs *regs)
+{
+ struct pt_regs *old_regs;
+ unsigned int irq;
+ unsigned long status_reg;
+
+ local_irq_disable();
+
+ old_regs = set_irq_regs(regs);
+
+ irq_enter();
+
+ irq = intc_readl(&intc0, INTCAUSE0 - 4 * level);
+ generic_handle_irq(irq);
+
+ /*
+ * Clear all interrupt level masks so that we may handle
+ * interrupts during softirq processing. If this is a nested
+ * interrupt, interrupts must stay globally disabled until we
+ * return.
+ */
+ status_reg = sysreg_read(SR);
+ status_reg &= ~(SYSREG_BIT(I0M) | SYSREG_BIT(I1M)
+ | SYSREG_BIT(I2M) | SYSREG_BIT(I3M));
+ sysreg_write(SR, status_reg);
+
+ irq_exit();
+
+ set_irq_regs(old_regs);
+}
+
+void __init init_IRQ(void)
+{
+ extern void _evba(void);
+ extern void irq_level0(void);
+ struct resource *regs;
+ struct clk *pclk;
+ unsigned int i;
+ u32 offset, readback;
+
+ regs = platform_get_resource(&at32_intc0_device, IORESOURCE_MEM, 0);
+ if (!regs) {
+ printk(KERN_EMERG "intc: no mmio resource defined\n");
+ goto fail;
+ }
+ pclk = clk_get(&at32_intc0_device.dev, "pclk");
+ if (IS_ERR(pclk)) {
+ printk(KERN_EMERG "intc: no clock defined\n");
+ goto fail;
+ }
+
+ clk_enable(pclk);
+
+ intc0.regs = ioremap(regs->start, resource_size(regs));
+ if (!intc0.regs) {
+ printk(KERN_EMERG "intc: failed to map registers (0x%08lx)\n",
+ (unsigned long)regs->start);
+ goto fail;
+ }
+
+ /*
+ * Initialize all interrupts to level 0 (lowest priority). The
+ * priority level may be changed by calling
+ * irq_set_priority().
+ *
+ */
+ offset = (unsigned long)&irq_level0 - (unsigned long)&_evba;
+ for (i = 0; i < NR_INTERNAL_IRQS; i++) {
+ intc_writel(&intc0, INTPR0 + 4 * i, offset);
+ readback = intc_readl(&intc0, INTPR0 + 4 * i);
+ if (readback == offset)
+ irq_set_chip_and_handler(i, &intc0.chip,
+ handle_simple_irq);
+ }
+
+ /* Unmask all interrupt levels */
+ sysreg_write(SR, (sysreg_read(SR)
+ & ~(SR_I3M | SR_I2M | SR_I1M | SR_I0M)));
+
+ return;
+
+fail:
+ panic("Interrupt controller initialization failed!\n");
+}
+
+#ifdef CONFIG_PM
+void intc_set_suspend_handler(unsigned long offset)
+{
+ intc0.suspend_ipr = offset;
+}
+
+static int intc_suspend(void)
+{
+ int i;
+
+ if (unlikely(!irqs_disabled())) {
+ pr_err("intc_suspend: called with interrupts enabled\n");
+ return -EINVAL;
+ }
+
+ if (unlikely(!intc0.suspend_ipr)) {
+ pr_err("intc_suspend: suspend_ipr not initialized\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < 64; i++) {
+ intc0.saved_ipr[i] = intc_readl(&intc0, INTPR0 + 4 * i);
+ intc_writel(&intc0, INTPR0 + 4 * i, intc0.suspend_ipr);
+ }
+
+ return 0;
+}
+
+static void intc_resume(void)
+{
+ int i;
+
+ for (i = 0; i < 64; i++)
+ intc_writel(&intc0, INTPR0 + 4 * i, intc0.saved_ipr[i]);
+}
+#else
+#define intc_suspend NULL
+#define intc_resume NULL
+#endif
+
+static struct syscore_ops intc_syscore_ops = {
+ .suspend = intc_suspend,
+ .resume = intc_resume,
+};
+
+static int __init intc_init_syscore(void)
+{
+ register_syscore_ops(&intc_syscore_ops);
+
+ return 0;
+}
+device_initcall(intc_init_syscore);
+
+unsigned long intc_get_pending(unsigned int group)
+{
+ return intc_readl(&intc0, INTREQ0 + 4 * group);
+}
+EXPORT_SYMBOL_GPL(intc_get_pending);