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authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/arm/mach-socfpga
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/arm/mach-socfpga')
-rw-r--r--kernel/arch/arm/mach-socfpga/Kconfig10
-rw-r--r--kernel/arch/arm/mach-socfpga/Makefile6
-rw-r--r--kernel/arch/arm/mach-socfpga/core.h50
-rw-r--r--kernel/arch/arm/mach-socfpga/headsmp.S37
-rw-r--r--kernel/arch/arm/mach-socfpga/platsmp.c105
-rw-r--r--kernel/arch/arm/mach-socfpga/socfpga.c119
6 files changed, 327 insertions, 0 deletions
diff --git a/kernel/arch/arm/mach-socfpga/Kconfig b/kernel/arch/arm/mach-socfpga/Kconfig
new file mode 100644
index 000000000..b5f8d75d5
--- /dev/null
+++ b/kernel/arch/arm/mach-socfpga/Kconfig
@@ -0,0 +1,10 @@
+config ARCH_SOCFPGA
+ bool "Altera SOCFPGA family" if ARCH_MULTI_V7
+ select ARM_AMBA
+ select ARM_GIC
+ select CACHE_L2X0
+ select DW_APB_TIMER_OF
+ select GPIO_PL061 if GPIOLIB
+ select HAVE_ARM_SCU
+ select HAVE_ARM_TWD if SMP
+ select MFD_SYSCON
diff --git a/kernel/arch/arm/mach-socfpga/Makefile b/kernel/arch/arm/mach-socfpga/Makefile
new file mode 100644
index 000000000..6dd7a93a9
--- /dev/null
+++ b/kernel/arch/arm/mach-socfpga/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y := socfpga.o
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/kernel/arch/arm/mach-socfpga/core.h b/kernel/arch/arm/mach-socfpga/core.h
new file mode 100644
index 000000000..a0f3b1cd4
--- /dev/null
+++ b/kernel/arch/arm/mach-socfpga/core.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2012 Pavel Machek <pavel@denx.de>
+ * Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __MACH_CORE_H
+#define __MACH_CORE_H
+
+#define SOCFPGA_RSTMGR_CTRL 0x04
+#define SOCFPGA_RSTMGR_MODMPURST 0x10
+#define SOCFPGA_RSTMGR_MODPERRST 0x14
+#define SOCFPGA_RSTMGR_BRGMODRST 0x1c
+
+/* System Manager bits */
+#define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */
+#define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */
+
+#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
+
+extern void socfpga_secondary_startup(void);
+extern void __iomem *socfpga_scu_base_addr;
+
+extern void socfpga_init_clocks(void);
+extern void socfpga_sysmgr_init(void);
+
+extern void __iomem *sys_manager_base_addr;
+extern void __iomem *rst_manager_base_addr;
+
+extern struct smp_operations socfpga_smp_ops;
+extern char secondary_trampoline, secondary_trampoline_end;
+
+extern unsigned long socfpga_cpu1start_addr;
+
+#define SOCFPGA_SCU_VIRT_BASE 0xfee00000
+
+#endif
diff --git a/kernel/arch/arm/mach-socfpga/headsmp.S b/kernel/arch/arm/mach-socfpga/headsmp.S
new file mode 100644
index 000000000..f65ea0af4
--- /dev/null
+++ b/kernel/arch/arm/mach-socfpga/headsmp.S
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2003 ARM Limited
+ * Copyright (c) u-boot contributors
+ * Copyright (c) 2012 Pavel Machek <pavel@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/memory.h>
+
+ .arch armv7-a
+
+ENTRY(secondary_trampoline)
+ /* CPU1 will always fetch from 0x0 when it is brought out of reset.
+ * Thus, we can just subtract the PAGE_OFFSET to get the physical
+ * address of &cpu1start_addr. This would not work for platforms
+ * where the physical memory does not start at 0x0.
+ */
+ adr r0, 1f
+ ldmia r0, {r1, r2}
+ sub r2, r2, #PAGE_OFFSET
+ ldr r3, [r2]
+ ldr r4, [r3]
+ bx r4
+
+ .align
+1: .long .
+ .long socfpga_cpu1start_addr
+ENTRY(secondary_trampoline_end)
+
+ENTRY(socfpga_secondary_startup)
+ bl v7_invalidate_l1
+ b secondary_startup
+ENDPROC(socfpga_secondary_startup)
diff --git a/kernel/arch/arm/mach-socfpga/platsmp.c b/kernel/arch/arm/mach-socfpga/platsmp.c
new file mode 100644
index 000000000..c64d89b7c
--- /dev/null
+++ b/kernel/arch/arm/mach-socfpga/platsmp.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ * Copyright 2012 Pavel Machek <pavel@denx.de>
+ * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
+ * Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
+
+#include "core.h"
+
+static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
+
+ if (socfpga_cpu1start_addr) {
+ /* This will put CPU #1 into reset. */
+ writel(RSTMGR_MPUMODRST_CPU1,
+ rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
+
+ memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+
+ writel(virt_to_phys(socfpga_secondary_startup),
+ sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
+
+ flush_cache_all();
+ smp_wmb();
+ outer_clean_range(0, trampoline_size);
+
+ /* This will release CPU #1 out of reset. */
+ writel(0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
+ }
+
+ return 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+static void __init socfpga_smp_init_cpus(void)
+{
+ unsigned int i, ncores;
+
+ ncores = scu_get_core_count(socfpga_scu_base_addr);
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+
+ /* sanity check */
+ if (ncores > num_possible_cpus()) {
+ pr_warn("socfpga: no. of cores (%d) greater than configured"
+ "maximum of %d - clipping\n", ncores, num_possible_cpus());
+ ncores = num_possible_cpus();
+ }
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+}
+
+static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
+{
+ scu_enable(socfpga_scu_base_addr);
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+static void socfpga_cpu_die(unsigned int cpu)
+{
+ /* Do WFI. If we wake up early, go back into WFI */
+ while (1)
+ cpu_do_idle();
+}
+
+struct smp_operations socfpga_smp_ops __initdata = {
+ .smp_init_cpus = socfpga_smp_init_cpus,
+ .smp_prepare_cpus = socfpga_smp_prepare_cpus,
+ .smp_boot_secondary = socfpga_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = socfpga_cpu_die,
+#endif
+};
diff --git a/kernel/arch/arm/mach-socfpga/socfpga.c b/kernel/arch/arm/mach-socfpga/socfpga.c
new file mode 100644
index 000000000..f5e597c20
--- /dev/null
+++ b/kernel/arch/arm/mach-socfpga/socfpga.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/reboot.h>
+
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/cacheflush.h>
+
+#include "core.h"
+
+void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
+void __iomem *sys_manager_base_addr;
+void __iomem *rst_manager_base_addr;
+unsigned long socfpga_cpu1start_addr;
+
+static struct map_desc scu_io_desc __initdata = {
+ .virtual = SOCFPGA_SCU_VIRT_BASE,
+ .pfn = 0, /* run-time */
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+};
+
+static struct map_desc uart_io_desc __initdata = {
+ .virtual = 0xfec02000,
+ .pfn = __phys_to_pfn(0xffc02000),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+};
+
+static void __init socfpga_scu_map_io(void)
+{
+ unsigned long base;
+
+ /* Get SCU base */
+ asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+ scu_io_desc.pfn = __phys_to_pfn(base);
+ iotable_init(&scu_io_desc, 1);
+}
+
+static void __init socfpga_map_io(void)
+{
+ socfpga_scu_map_io();
+ iotable_init(&uart_io_desc, 1);
+ early_printk("Early printk initialized\n");
+}
+
+void __init socfpga_sysmgr_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
+
+ if (of_property_read_u32(np, "cpu1-start-addr",
+ (u32 *) &socfpga_cpu1start_addr))
+ pr_err("SMP: Need cpu1-start-addr in device tree.\n");
+
+ /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
+ smp_wmb();
+ sync_cache_w(&socfpga_cpu1start_addr);
+
+ sys_manager_base_addr = of_iomap(np, 0);
+
+ np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
+ rst_manager_base_addr = of_iomap(np, 0);
+}
+
+static void __init socfpga_init_irq(void)
+{
+ irqchip_init();
+ socfpga_sysmgr_init();
+}
+
+static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
+{
+ u32 temp;
+
+ temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
+
+ if (mode == REBOOT_HARD)
+ temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
+ else
+ temp |= RSTMGR_CTRL_SWWARMRSTREQ;
+ writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
+}
+
+static const char *altera_dt_match[] = {
+ "altr,socfpga",
+ NULL
+};
+
+DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
+ .l2c_aux_val = 0,
+ .l2c_aux_mask = ~0,
+ .smp = smp_ops(socfpga_smp_ops),
+ .map_io = socfpga_map_io,
+ .init_irq = socfpga_init_irq,
+ .restart = socfpga_cyclone5_restart,
+ .dt_compat = altera_dt_match,
+MACHINE_END