diff options
author | 2015-08-04 12:17:53 -0700 | |
---|---|---|
committer | 2015-08-04 15:44:42 -0700 | |
commit | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch) | |
tree | 1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/arm/mach-davinci/mux.c | |
parent | 98260f3884f4a202f9ca5eabed40b1354c489b29 (diff) |
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base.
It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:
commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date: Sat Jul 25 12:13:34 2015 +0200
Prepare v4.1.3-rt3
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.
Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/arm/mach-davinci/mux.c')
-rw-r--r-- | kernel/arch/arm/mach-davinci/mux.c | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/kernel/arch/arm/mach-davinci/mux.c b/kernel/arch/arm/mach-davinci/mux.c new file mode 100644 index 000000000..6a2ff0a65 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/mux.c @@ -0,0 +1,116 @@ +/* + * Utility to set the DAVINCI MUX register from a table in mux.h + * + * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> + * + * Based on linux/arch/arm/plat-omap/mux.c: + * Copyright (C) 2003 - 2005 Nokia Corporation + * + * Written by Tony Lindgren + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright (C) 2008 Texas Instruments. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/io.h> +#include <linux/module.h> +#include <linux/spinlock.h> + +#include <mach/mux.h> +#include <mach/common.h> + +static void __iomem *pinmux_base; + +/* + * Sets the DAVINCI MUX register based on the table + */ +int davinci_cfg_reg(const unsigned long index) +{ + static DEFINE_SPINLOCK(mux_spin_lock); + struct davinci_soc_info *soc_info = &davinci_soc_info; + unsigned long flags; + const struct mux_config *cfg; + unsigned int reg_orig = 0, reg = 0; + unsigned int mask, warn = 0; + + if (WARN_ON(!soc_info->pinmux_pins)) + return -ENODEV; + + if (!pinmux_base) { + pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K); + if (WARN_ON(!pinmux_base)) + return -ENOMEM; + } + + if (index >= soc_info->pinmux_pins_num) { + pr_err("Invalid pin mux index: %lu (%lu)\n", + index, soc_info->pinmux_pins_num); + dump_stack(); + return -ENODEV; + } + + cfg = &soc_info->pinmux_pins[index]; + + if (cfg->name == NULL) { + pr_err("No entry for the specified index\n"); + return -ENODEV; + } + + /* Update the mux register in question */ + if (cfg->mask) { + unsigned tmp1, tmp2; + + spin_lock_irqsave(&mux_spin_lock, flags); + reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); + + mask = (cfg->mask << cfg->mask_offset); + tmp1 = reg_orig & mask; + reg = reg_orig & ~mask; + + tmp2 = (cfg->mode << cfg->mask_offset); + reg |= tmp2; + + if (tmp1 != tmp2) + warn = 1; + + __raw_writel(reg, pinmux_base + cfg->mux_reg); + spin_unlock_irqrestore(&mux_spin_lock, flags); + } + + if (warn) { +#ifdef CONFIG_DAVINCI_MUX_WARNINGS + pr_warn("initialized %s\n", cfg->name); +#endif + } + +#ifdef CONFIG_DAVINCI_MUX_DEBUG + if (cfg->debug || warn) { + pr_warn("Setting register %s\n", cfg->name); + pr_warn(" %s (0x%08x) = 0x%08x -> 0x%08x\n", + cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); + } +#endif + + return 0; +} +EXPORT_SYMBOL(davinci_cfg_reg); + +int davinci_cfg_reg_list(const short pins[]) +{ + int i, error = -EINVAL; + + if (pins) + for (i = 0; pins[i] >= 0; i++) { + error = davinci_cfg_reg(pins[i]); + if (error) + break; + } + + return error; +} |