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authorYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 12:17:53 -0700
committerYunhong Jiang <yunhong.jiang@intel.com>2015-08-04 15:44:42 -0700
commit9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (patch)
tree1c9cafbcd35f783a87880a10f85d1a060db1a563 /kernel/arch/arm/boot/dts/xenvm-4.2.dts
parent98260f3884f4a202f9ca5eabed40b1354c489b29 (diff)
Add the rt linux 4.1.3-rt3 as base
Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
Diffstat (limited to 'kernel/arch/arm/boot/dts/xenvm-4.2.dts')
-rw-r--r--kernel/arch/arm/boot/dts/xenvm-4.2.dts81
1 files changed, 81 insertions, 0 deletions
diff --git a/kernel/arch/arm/boot/dts/xenvm-4.2.dts b/kernel/arch/arm/boot/dts/xenvm-4.2.dts
new file mode 100644
index 000000000..336915151
--- /dev/null
+++ b/kernel/arch/arm/boot/dts/xenvm-4.2.dts
@@ -0,0 +1,81 @@
+/*
+ * Xen Virtual Machine for unprivileged guests
+ *
+ * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU)
+ * Cortex-A15 MPCore (V2P-CA15)
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ model = "XENVM-4.2";
+ compatible = "xen,xenvm-4.2", "xen,xenvm";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+ /* this field is going to be adjusted by the hypervisor */
+ bootargs = "console=hvc0 root=/dev/xvda";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci";
+ method = "hvc";
+ cpu_off = <1>;
+ cpu_on = <2>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* this field is going to be adjusted by the hypervisor */
+ reg = <0 0x80000000 0 0x08000000>;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x2c001000 0 0x1000>,
+ <0 0x2c002000 0 0x100>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ hypervisor {
+ compatible = "xen,xen-4.2", "xen,xen";
+ /* this field is going to be adjusted by the hypervisor */
+ reg = <0 0xb0000000 0 0x20000>;
+ /* this field is going to be adjusted by the hypervisor */
+ interrupts = <1 15 0xf08>;
+ };
+
+ motherboard {
+ arm,v2m-memory-map = "rs1";
+ };
+};