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#jinja2:variable_start_string:'[[', variable_end_string:']]', block_start_string:'[%', block_end_string:'%]'
# Copyright (c) 2016-2017 Intel Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

# flow definition for ACL tests - 1K flows - ipv4 only
#
# the number of flows defines the widest range of parameters
# for example if srcip_range=1.0.0.1-1.0.0.255 and dst_ip_range=10.0.0.1-10.0.1.255
# and it should define only 16 flows
#
# there is assumption that packets generated will have a random sequences of following addresses pairs
# in the packets
# 1. src=1.x.x.x(x.x.x =random from 1..255) dst=10.x.x.x (random from 1..512)
# 2. src=1.x.x.x(x.x.x =random from 1..255) dst=10.x.x.x (random from 1..512)
# ...
# 512. src=1.x.x.x(x.x.x =random from 1..255) dst=10.x.x.x (random from 1..512)
#
# not all combination should be filled
# Any other field with random range will be added to flow definition
#
# the example.yaml provides all possibilities for traffic generation
#
# the profile defines a public and private side to make limited traffic correlation
# between private and public side same way as it is made by IXIA solution.
#
---
schema: "nsb:traffic_profile:0.1"

# This file is a template, it will be filled with values from tc.yaml before passing to the traffic generator

name: rfc2544
description: Traffic profile to run RFC2544 latency
traffic_profile:
  traffic_type: RFC2544Profile # defines traffic behavior - constant or look for highest possible throughput
  frame_rate: 100  # pc of linerate
  duration: {{ duration }}

[% for vnf_num in range(num_vnfs|int) %]
uplink_[[ vnf_num ]]:
  ipv4:
    id: [[vnf_num * 2 + 1]]
    outer_l2:
      framesize:
        64B: "{{ get(imix, 'imix.uplink.64B', '0') }}"
        128B: "{{ get(imix, 'imix.uplink.128B', '0') }}"
        256B: "{{ get(imix, 'imix.uplink.256B', '0') }}"
        373b: "{{ get(imix, 'imix.uplink.373B', '0') }}"
        512B: "{{ get(imix, 'imix.uplink.512B', '0') }}"
        570B: "{{get(imix, 'imix.uplink.570B', '0') }}"
        1400B: "{{get(imix, 'imix.uplink.1400B', '0') }}"
        1500B: "{{get(imix, 'imix.uplink.1500B', '0') }}"
        1518B: "{{get(imix, 'imix.uplink.1518B', '0') }}"
    outer_l3v4:
      proto: "udp"
      srcip4: "{{get(flow, 'flow.src_ip_[[ vnf_num ]]', '1.1.1.1-1.1.255.255') }}"
      dstip4: "{{get(flow, 'flow.dst_ip_[[ vnf_num ]]', '90.90.1.1-90.90.255.255') }}"
      count: "{{get(flow, 'flow.count', '1') }}"
      ttl: 32
      dscp: 0
    outer_l4:
      srcport: "{{get(flow, 'flow.src_port_[[ vnf_num ]]', '1234-4321') }}"
      dstport: "{{get(flow, 'flow.dst_port_[[ vnf_num ]]', '2001-4001') }}"
      count: "{{get(flow, 'flow.count', '1') }}"
downlink_[[ vnf_num ]]:
  ipv4:
    id: [[vnf_num * 2 + 2]]
    outer_l2:
      framesize:
        64B: "{{ get(imix, 'imix.downlink.64B', '0') }}"
        128B: "{{ get(imix, 'imix.downlink.128B', '0') }}"
        256B: "{{ get(imix, 'imix.downlink.256B', '0') }}"
        373b: "{{ get(imix, 'imix.downlink.373B', '0') }}"
        512B: "{{ get(imix, 'imix.downlink.512B', '0') }}"
        570B: "{{get(imix, 'imix.downlink.570B', '0') }}"
        1400B: "{{get(imix, 'imix.downlink.1400B', '0') }}"
        1500B: "{{get(imix, 'imix.downlink.1500B', '0') }}"
        1518B: "{{get(imix, 'imix.downlink.1518B', '0') }}"

    outer_l3v4:
      proto: "udp"
      srcip4: "{{get(flow, 'flow.dst_ip_[[ vnf_num ]]', '90.90.1.1-90.90.255.255') }}"
      dstip4: "{{get(flow, 'flow.src_ip_[[ vnf_num ]]', '1.1.1.1-1.1.255.255') }}"
      count: "{{get(flow, 'flow.count', '1') }}"
      ttl: 32
      dscp: 0
    outer_l4:
      srcport: "{{get(flow, 'flow.dst_port_[[ vnf_num ]]', '1234-4321') }}"
      dstport: "{{get(flow, 'flow.src_port_[[ vnf_num ]]', '2001-4001') }}"
      count: "{{get(flow, 'flow.count', '1') }}"
[% endfor %]
n>; } static inline void superio_exit(void) { outb(0x02, REG); outb(0x02, VAL); release_region(REG, 2); } static inline void superio_select(int ldn) { outb(LDNREG, REG); outb(ldn, VAL); } static inline int superio_inb(int reg) { outb(reg, REG); return inb(VAL); } static inline void superio_outb(int val, int reg) { outb(reg, REG); outb(val, VAL); } static inline int superio_inw(int reg) { int val; outb(reg++, REG); val = inb(VAL) << 8; outb(reg, REG); val |= inb(VAL); return val; } static inline void superio_outw(int val, int reg) { outb(reg++, REG); outb(val >> 8, VAL); outb(reg, REG); outb(val, VAL); } static inline void superio_set_mask(int mask, int reg) { u8 curr_val = superio_inb(reg); u8 new_val = curr_val | mask; if (curr_val != new_val) superio_outb(new_val, reg); } static inline void superio_clear_mask(int mask, int reg) { u8 curr_val = superio_inb(reg); u8 new_val = curr_val & ~mask; if (curr_val != new_val) superio_outb(new_val, reg); } static int it87_gpio_request(struct gpio_chip *chip, unsigned gpio_num) { u8 mask, group; int rc = 0; struct it87_gpio *it87_gpio = to_it87_gpio(chip); mask = 1 << (gpio_num % 8); group = (gpio_num / 8); spin_lock(&it87_gpio->lock); rc = superio_enter(); if (rc) goto exit; /* not all the IT87xx chips support Simple I/O and not all of * them allow all the lines to be set/unset to Simple I/O. */ if (group < it87_gpio->simple_size) superio_set_mask(mask, group + it87_gpio->simple_base); /* clear output enable, setting the pin to input, as all the * newly-exported GPIO interfaces are set to input. */ superio_clear_mask(mask, group + it87_gpio->output_base); superio_exit(); exit: spin_unlock(&it87_gpio->lock); return rc; } static int it87_gpio_get(struct gpio_chip *chip, unsigned gpio_num) { u16 reg; u8 mask; struct it87_gpio *it87_gpio = to_it87_gpio(chip); mask = 1 << (gpio_num % 8); reg = (gpio_num / 8) + it87_gpio->io_base; return !!(inb(reg) & mask); } static int it87_gpio_direction_in(struct gpio_chip *chip, unsigned gpio_num) { u8 mask, group; int rc = 0; struct it87_gpio *it87_gpio = to_it87_gpio(chip); mask = 1 << (gpio_num % 8); group = (gpio_num / 8); spin_lock(&it87_gpio->lock); rc = superio_enter(); if (rc) goto exit; /* clear the output enable bit */ superio_clear_mask(mask, group + it87_gpio->output_base); superio_exit(); exit: spin_unlock(&it87_gpio->lock); return rc; } static void it87_gpio_set(struct gpio_chip *chip, unsigned gpio_num, int val) { u8 mask, curr_vals; u16 reg; struct it87_gpio *it87_gpio = to_it87_gpio(chip); mask = 1 << (gpio_num % 8); reg = (gpio_num / 8) + it87_gpio->io_base; curr_vals = inb(reg); if (val) outb(curr_vals | mask, reg); else outb(curr_vals & ~mask, reg); } static int it87_gpio_direction_out(struct gpio_chip *chip, unsigned gpio_num, int val) { u8 mask, group; int rc = 0; struct it87_gpio *it87_gpio = to_it87_gpio(chip); mask = 1 << (gpio_num % 8); group = (gpio_num / 8); spin_lock(&it87_gpio->lock); rc = superio_enter(); if (rc) goto exit; /* set the output enable bit */ superio_set_mask(mask, group + it87_gpio->output_base); it87_gpio_set(chip, gpio_num, val); superio_exit(); exit: spin_unlock(&it87_gpio->lock); return rc; } static struct gpio_chip it87_template_chip = { .label = KBUILD_MODNAME, .owner = THIS_MODULE, .request = it87_gpio_request, .get = it87_gpio_get, .direction_input = it87_gpio_direction_in, .set = it87_gpio_set, .direction_output = it87_gpio_direction_out, .base = -1 }; static int __init it87_gpio_init(void) { int rc = 0, i; u16 chip_type; u8 chip_rev, gpio_ba_reg; char *labels, **labels_table; struct it87_gpio *it87_gpio = &it87_gpio_chip; rc = superio_enter(); if (rc) return rc; chip_type = superio_inw(CHIPID); chip_rev = superio_inb(CHIPREV) & 0x0f; superio_exit(); it87_gpio->chip = it87_template_chip; switch (chip_type) { case IT8728_ID: case IT8732_ID: gpio_ba_reg = 0x62; it87_gpio->io_size = 8; it87_gpio->output_base = 0xc8; it87_gpio->simple_base = 0xc0; it87_gpio->simple_size = 5; it87_gpio->chip.ngpio = 64; break; case IT8761_ID: gpio_ba_reg = 0x60; it87_gpio->io_size = 4; it87_gpio->output_base = 0xf0; it87_gpio->simple_size = 0; it87_gpio->chip.ngpio = 16; break; case NO_DEV_ID: pr_err("no device\n"); return -ENODEV; default: pr_err("Unknown Chip found, Chip %04x Revision %x\n", chip_type, chip_rev); return -ENODEV; } rc = superio_enter(); if (rc) return rc; superio_select(GPIO); /* fetch GPIO base address */ it87_gpio->io_base = superio_inw(gpio_ba_reg); superio_exit(); pr_info("Found Chip IT%04x rev %x. %u GPIO lines starting at %04xh\n", chip_type, chip_rev, it87_gpio->chip.ngpio, it87_gpio->io_base); if (!request_region(it87_gpio->io_base, it87_gpio->io_size, KBUILD_MODNAME)) return -EBUSY; /* Set up aliases for the GPIO connection. * * ITE documentation for recent chips such as the IT8728F * refers to the GPIO lines as GPxy, with a coordinates system * where x is the GPIO group (starting from 1) and y is the * bit within the group. * * By creating these aliases, we make it easier to understand * to which GPIO pin we're referring to. */ labels = kcalloc(it87_gpio->chip.ngpio, sizeof("it87_gpXY"), GFP_KERNEL); labels_table = kcalloc(it87_gpio->chip.ngpio, sizeof(const char *), GFP_KERNEL); if (!labels || !labels_table) { rc = -ENOMEM; goto labels_free; } for (i = 0; i < it87_gpio->chip.ngpio; i++) { char *label = &labels[i * sizeof("it87_gpXY")]; sprintf(label, "it87_gp%u%u", 1+(i/8), i%8); labels_table[i] = label; } it87_gpio->chip.names = (const char *const*)labels_table; rc = gpiochip_add(&it87_gpio->chip); if (rc) goto labels_free; return 0; labels_free: kfree(labels_table); kfree(labels); release_region(it87_gpio->io_base, it87_gpio->io_size); return rc; } static void __exit it87_gpio_exit(void) { struct it87_gpio *it87_gpio = &it87_gpio_chip; gpiochip_remove(&it87_gpio->chip); release_region(it87_gpio->io_base, it87_gpio->io_size); kfree(it87_gpio->chip.names[0]); kfree(it87_gpio->chip.names); } module_init(it87_gpio_init); module_exit(it87_gpio_exit); MODULE_AUTHOR("Diego Elio Pettenò <flameeyes@flameeyes.eu>"); MODULE_DESCRIPTION("GPIO interface for IT87xx Super I/O chips"); MODULE_LICENSE("GPL");