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; Copyright (c) 2016-2017 Intel Corporation
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
;      http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.

[lua]
acl_table = dofile("acl_rules-2.lua")

[eal options]
-n=4 ; force number of memory channels
no-output=no ; disable DPDK debug output

[port 0]
name=if0
mac=hardware
rx desc=2048
tx desc=2048
[port 1]
name=if1
mac=hardware
rx desc=2048
tx desc=2048
[port 2]
name=if2
mac=hardware
rx desc=2048
tx desc=2048
[port 3]
name=if3
mac=hardware
rx desc=2048
tx desc=2048

[defaults]
mempool size=65K
memcache size=512
qinq tag="0xa888"

[global]
start time=5
name=ACL handle x4

[core 0]
task=0
mode=master

[core 1]
name=W-up
task=0
mode=acl
max rules=32768
rules=acl_table
rx port=if0
tx cores=1t1
drop=no

name=l2fwd_if0
task=1
mode=l2fwd
rx ring=yes
dst mac=@@tester_p0
tx port=if0
drop=no

[core 2]
name=W-up
task=0
mode=acl
max rules=32768
rules=acl_table
rx port=if1
tx cores=2t1
drop=no

name=l2fwd_if1
task=1
mode=l2fwd
rx ring=yes
dst mac=@@tester_p1
tx port=if1
drop=no

[core 3]
name=W-up
task=0
mode=acl
max rules=32768
rules=acl_table
rx port=if2
tx cores=3t1
drop=no

name=l2fwd_if2
task=1
mode=l2fwd
rx ring=yes
dst mac=@@tester_p2
tx port=if2
drop=no

[core 4]
name=W-up
task=0
mode=acl
max rules=32768
rules=acl_table
rx port=if3
tx cores=4t1
drop=no

name=l2fwd_if3
task=1
mode=l2fwd
rx ring=yes
dst mac=@@tester_p3
tx port=if3
drop=no
an> #define LCR_EPS 0x1000 /* Even Parity Select */ #define LCR_SP 0x2000 /* Stick Parity */ #define LCR_SB 0x4000 /* Set Break */ #define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */ /* MODEM Control Register */ #define MCR_DTR 0x0100 /* Data Terminal Ready */ #define MCR_RTS 0x0200 /* Request to Send */ #define MCR_OUT1 0x0400 /* Out 1 */ #define MCR_IRQEN 0x0800 /* IRQ Enable */ #define MCR_LOOP 0x1000 /* Loop */ /* Line Status Register */ #define LSR_DR 0x0100 /* Data Ready */ #define LSR_OE 0x0200 /* Overrun Error */ #define LSR_PE 0x0400 /* Parity Error */ #define LSR_FE 0x0800 /* Framing Error */ #define LSR_BI 0x1000 /* Break Interrupt */ #define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */ #define LSR_TEMT 0x4000 /* Transmitter Empty */ #define LSR_FIFOE 0x8000 /* Receiver FIFO error */ /* MODEM Status Register */ #define MSR_DCTS 0x0100 /* Delta Clear to Send */ #define MSR_DDSR 0x0200 /* Delta Data Set Ready */ #define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */ #define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */ #define MSR_CTS 0x1000 /* Clear to Send */ #define MSR_DSR 0x2000 /* Data Set Ready */ #define MSR_RI 0x4000 /* Ring Indicator */ #define MSR_DCD 0x8000 /* Data Carrier Detect */ /* Baud Rate Divisor */ #define UART_CLK (1843200) /* 1.8432 MHz */ #define UART_BAUD(x) (UART_CLK / (16 * (x))) /* RTC register definition */ #define RTC_SECONDS 0 #define RTC_SECONDS_ALARM 1 #define RTC_MINUTES 2 #define RTC_MINUTES_ALARM 3 #define RTC_HOURS 4 #define RTC_HOURS_ALARM 5 #define RTC_DAY_OF_WEEK 6 #define RTC_DAY_OF_MONTH 7 #define RTC_MONTH 8 #define RTC_YEAR 9 #define RTC_FREQ_SELECT 10 # define RTC_UIP 0x80 # define RTC_DIV_CTL 0x70 /* This RTC can work under 32.768KHz clock only. */ # define RTC_OSC_ENABLE 0x20 # define RTC_OSC_DISABLE 0x00 #define RTC_CONTROL 11 # define RTC_SET 0x80 # define RTC_PIE 0x40 # define RTC_AIE 0x20 # define RTC_UIE 0x10 # define RTC_SQWE 0x08 # define RTC_DM_BINARY 0x04 # define RTC_24H 0x02 # define RTC_DST_EN 0x01 #endif /* __ASM_SH_SMC37C93X_H */