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path: root/samples/vnf_samples/nsut/prox/configs/dscp.lua
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-- Copyright (c) 2016-2017 Intel Corporation
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
--      http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
--;

return {
   {dscp = 0,  tc = 0, queue = 0},
   {dscp = 1,  tc = 0, queue = 1},
   {dscp = 2,  tc = 0, queue = 2},
   {dscp = 3,  tc = 0, queue = 3},
   {dscp = 4,  tc = 1, queue = 0},
   {dscp = 5,  tc = 1, queue = 1},
   {dscp = 6,  tc = 1, queue = 2},
   {dscp = 7,  tc = 1, queue = 3},
   {dscp = 8,  tc = 2, queue = 0},
   {dscp = 9,  tc = 2, queue = 1},
   {dscp = 10, tc = 2, queue = 2},
   {dscp = 11, tc = 2, queue = 3},
   {dscp = 12, tc = 3, queue = 0},
   {dscp = 13, tc = 3, queue = 1},
   {dscp = 14, tc = 3, queue = 2},
   {dscp = 15, tc = 3, queue = 3},
   {dscp = 16, tc = 0, queue = 0},
   {dscp = 17, tc = 0, queue = 1},
   {dscp = 18, tc = 0, queue = 2},
   {dscp = 19, tc = 0, queue = 3},
   {dscp = 20, tc = 1, queue = 0},
   {dscp = 21, tc = 1, queue = 1},
   {dscp = 22, tc = 1, queue = 2},
   {dscp = 23, tc = 1, queue = 3},
   {dscp = 24, tc = 2, queue = 0},
   {dscp = 25, tc = 2, queue = 1},
   {dscp = 26, tc = 2, queue = 2},
   {dscp = 27, tc = 2, queue = 3},
   {dscp = 28, tc = 3, queue = 0},
   {dscp = 29, tc = 3, queue = 1},
   {dscp = 30, tc = 3, queue = 2},
   {dscp = 31, tc = 3, queue = 3},
   {dscp = 32, tc = 0, queue = 0},
   {dscp = 33, tc = 0, queue = 1},
   {dscp = 34, tc = 0, queue = 2},
   {dscp = 35, tc = 0, queue = 3},
   {dscp = 36, tc = 1, queue = 0},
   {dscp = 37, tc = 1, queue = 1},
   {dscp = 38, tc = 1, queue = 2},
   {dscp = 39, tc = 1, queue = 3},
   {dscp = 40, tc = 2, queue = 0},
   {dscp = 41, tc = 2, queue = 1},
   {dscp = 42, tc = 2, queue = 2},
   {dscp = 43, tc = 2, queue = 3},
   {dscp = 44, tc = 3, queue = 0},
   {dscp = 45, tc = 3, queue = 1},
   {dscp = 46, tc = 3, queue = 2},
   {dscp = 47, tc = 3, queue = 3},
   {dscp = 48, tc = 0, queue = 0},
   {dscp = 49, tc = 0, queue = 1},
   {dscp = 50, tc = 0, queue = 2},
   {dscp = 51, tc = 0, queue = 3},
   {dscp = 52, tc = 1, queue = 0},
   {dscp = 53, tc = 1, queue = 1},
   {dscp = 54, tc = 1, queue = 2},
   {dscp = 55, tc = 1, queue = 3},
   {dscp = 56, tc = 2, queue = 0},
   {dscp = 57, tc = 2, queue = 1},
   {dscp = 58, tc = 2, queue = 2},
   {dscp = 59, tc = 2, queue = 3},
   {dscp = 60, tc = 3, queue = 0},
   {dscp = 61, tc = 3, queue = 1},
   {dscp = 62, tc = 3, queue = 2},
   {dscp = 63, tc = 3, queue = 3},
}
an class="p">; unsigned long long tod_epoch_difference; } __attribute__ ((packed)); /* Inline assembly helper functions */ static inline int etr_setr(struct etr_eacr *ctrl) { int rc = -EOPNOTSUPP; asm volatile( " .insn s,0xb2160000,%1\n" "0: la %0,0\n" "1:\n" EX_TABLE(0b,1b) : "+d" (rc) : "Q" (*ctrl)); return rc; } /* Stores a format 1 aib with 64 bytes */ static inline int etr_stetr(struct etr_aib *aib) { int rc = -EOPNOTSUPP; asm volatile( " .insn s,0xb2170000,%1\n" "0: la %0,0\n" "1:\n" EX_TABLE(0b,1b) : "+d" (rc) : "Q" (*aib)); return rc; } /* Stores a format 2 aib with 96 bytes for specified port */ static inline int etr_steai(struct etr_aib *aib, unsigned int func) { register unsigned int reg0 asm("0") = func; int rc = -EOPNOTSUPP; asm volatile( " .insn s,0xb2b30000,%1\n" "0: la %0,0\n" "1:\n" EX_TABLE(0b,1b) : "+d" (rc) : "Q" (*aib), "d" (reg0)); return rc; } /* Function codes for the steai instruction. */ #define ETR_STEAI_STEPPING_PORT 0x10 #define ETR_STEAI_ALTERNATE_PORT 0x11 #define ETR_STEAI_PORT_0 0x12 #define ETR_STEAI_PORT_1 0x13 static inline int etr_ptff(void *ptff_block, unsigned int func) { register unsigned int reg0 asm("0") = func; register unsigned long reg1 asm("1") = (unsigned long) ptff_block; int rc = -EOPNOTSUPP; asm volatile( " .word 0x0104\n" " ipm %0\n" " srl %0,28\n" : "=d" (rc), "=m" (ptff_block) : "d" (reg0), "d" (reg1), "m" (ptff_block) : "cc"); return rc; } /* Function codes for the ptff instruction. */ #define ETR_PTFF_QAF 0x00 /* query available functions */ #define ETR_PTFF_QTO 0x01 /* query tod offset */ #define ETR_PTFF_QSI 0x02 /* query steering information */ #define ETR_PTFF_ATO 0x40 /* adjust tod offset */ #define ETR_PTFF_STO 0x41 /* set tod offset */ #define ETR_PTFF_SFS 0x42 /* set fine steering rate */ #define ETR_PTFF_SGS 0x43 /* set gross steering rate */ /* Functions needed by the machine check handler */ void etr_switch_to_local(void); void etr_sync_check(void); /* STP interruption parameter */ struct stp_irq_parm { unsigned int _pad0 : 14; unsigned int tsc : 1; /* Timing status change */ unsigned int lac : 1; /* Link availability change */ unsigned int tcpc : 1; /* Time control parameter change */ unsigned int _pad2 : 15; } __attribute__ ((packed)); #define STP_OP_SYNC 1 #define STP_OP_CTRL 3 struct stp_sstpi { unsigned int rsvd0; unsigned int rsvd1 : 8; unsigned int stratum : 8; unsigned int vbits : 16; unsigned int leaps : 16; unsigned int tmd : 4; unsigned int ctn : 4; unsigned int rsvd2 : 3; unsigned int c : 1; unsigned int tst : 4; unsigned int tzo : 16; unsigned int dsto : 16; unsigned int ctrl : 16; unsigned int rsvd3 : 16; unsigned int tto; unsigned int rsvd4; unsigned int ctnid[3]; unsigned int rsvd5; unsigned int todoff[4]; unsigned int rsvd6[48]; } __attribute__ ((packed)); /* Functions needed by the machine check handler */ void stp_sync_check(void); void stp_island_check(void); #endif /* __S390_ETR_H */