1 files changed, 105 insertions, 0 deletions
diff --git a/samples/vnf_samples/nsut/prox/configs/gen_lb-4.cfg b/samples/vnf_samples/nsut/prox/configs/gen_lb-4.cfg
new file mode 100644
index 000000000..4ac4f94d7
--- /dev/null
+++ b/samples/vnf_samples/nsut/prox/configs/gen_lb-4.cfg
@@ -0,0 +1,105 @@
+# Copyright (c) 2016-2017 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#;
+
+[eal options]
+-n=4 ; force number of memory channels
+no-output=no ; disable DPDK debug output
+
+[variables]
+$sut_mac0=@@dst_mac0
+
+[port 0]
+name=p0
+mac=hardware
+rx desc=4096
+tx desc=4096
+promiscuous=yes
+
+[port 1]
+name=p1
+mac=hardware
+rx desc=4096
+tx desc=1024
+promiscuous=yes
+
+[port 2]
+name=p2
+mac=hardware
+rx desc=4096
+tx desc=1024
+promiscuous=yes
+
+[port 3]
+name=p3
+mac=hardware
+rx desc=4096
+tx desc=1024
+promiscuous=yes
+
+[defaults]
+mempool size=16K
+
+[global]
+start time=5
+name=Gen Load Balancing
+
+[core 0]
+mode=master
+
+[core 1]
+name=p0
+task=0
+mode=gen
+tx port=p0
+bps=1250000000
+; Ethernet + IP + pseudo-UDP
+pkt inline=${sut_mac0} 70 00 00 00 00 01 08 00 45 00 00 1c 00 01 00 00 40 11 f7 7d 00 00 00 01 00 00 00 02 13 88 13 88 00 08 55 7b
+; src_ip: 10.x.x.x
+random=101000000000XXXX0000XXXX000XXXXX
+rand_offset=26
+; dst_ip: 10.x.x.x
+random=101000000000XXXX0000XXXX000XXXXX
+rand_offset=30
+; sport: [0..31]
+; dport: [0..31]
+random=00000000000XXXXX00000000000XXXXX
+rand_offset=34
+
+[core 2]
+name=p0
+task=0
+mode=nop
+rx port=p0
+
+[core 3]
+name=p1
+task=0
+mode=nop
+rx port=p1
+
+[core 4]
+name=p2
+task=0
+mode=nop
+rx port=p2
+
+[core 5]
+name=p3
+task=0
+mode=nop
+rx port=p3
+
+