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diff --git a/samples/vnf_samples/nsut/prox/configs/gen_l2fwd-4.cfg b/samples/vnf_samples/nsut/prox/configs/gen_l2fwd-4.cfg
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+# Copyright (c) 2016-2017 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#;
+
+[eal options]
+-n=4
+no-output=no ; disable DPDK debug output
+
+[port 0]
+name=p0
+mac=hardware
+promiscuous=yes
+
+[port 1]
+name=p1
+mac=hardware
+promiscuous=yes
+
+[port 2]
+name=p2
+mac=hardware
+promiscuous=yes
+
+[port 3]
+name=p3
+mac=hardware
+promiscuous=yes
+
+[defaults]
+mempool size=4K
+
+[variables]
+$sut_mac0=@@dst_mac0
+$sut_mac1=@@dst_mac1
+$sut_mac2=@@dst_mac2
+$sut_mac3=@@dst_mac3
+
+[global]
+start time=5
+name=Basic Gen x4
+
+[core 0]
+mode=master
+
+[core 1]
+name=gen 0
+task=0
+mode=gen
+tx port=p0
+bps=1250000000
+; Ethernet + IP + UDP
+pkt inline=${sut_mac0} 3c fd fe 9f a3 a0 08 a0 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b
+
+[core 2]
+name=gen 1
+task=0
+mode=gen
+tx port=p1
+bps=1250000000
+; Ethernet + IP + UDP
+pkt inline=${sut_mac1} 3c fd fe 9f a5 50 08 a0 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b
+
+[core 3]
+name=gen 2
+task=0
+mode=gen
+tx port=p2
+bps=1250000000
+; Ethernet + IP + UDP
+pkt inline=${sut_mac2} 3c fd fe 9f a5 50 08 a0 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b
+
+[core 4]
+name=gen 3
+task=0
+mode=gen
+tx port=p3
+bps=1250000000
+; Ethernet + IP + UDP
+pkt inline=${sut_mac3} 3c fd fe 9f a5 50 08 a0 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b
+
+[core 5]
+name=rec 0
+task=0
+mode=lat
+rx port=p0
+
+[core 6]
+name=rec 1
+task=0
+mode=lat
+rx port=p1
+
+[core 7]
+name=rec 2
+task=0
+mode=lat
+rx port=p2
+
+[core 8]
+name=rec 3
+task=0
+mode=lat
+rx port=p3