Support NSB NFVi buffering and Load Balance on 2 and 4 ports

JIRA: YARDSTICK-1582

Most use cases support 4 ports.
Buffering support only 1 core.
Request is about supporting buffering & Load balance
for 2 and 4 ports

Change-Id: I734f9d6702825b31253a21092c86fc72e367586b
Signed-off-by: Daniel Martin Buckley <daniel.m.buckley@intel.com>

1 files changed, 81 insertions, 0 deletions

diff --git a/samples/vnf_samples/nsut/prox/configs/handle_lb-2.cfg b/samples/vnf_samples/nsut/prox/configs/handle_lb-2.cfg
new file mode 100644
index 000000000..18ae9f4f9
--- /dev/null
+++ b/samples/vnf_samples/nsut/prox/configs/handle_lb-2.cfg
@@ -0,0 +1,81 @@
+# Copyright (c) 2016-2017 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#;
+
+[eal options]
+-n=4
+no-output=no ; disable DPDK debug output
+
+[lua]
+dofile("tuples.lua")
+
+[port 0]
+name=if0
+mac=hardware
+rx desc=4096
+tx desc=2048
+promiscuous=yes
+
+[port 1]
+name=if1
+mac=hardware
+rx desc=2048
+tx desc=2048
+promiscuous=yes
+
+[defaults]
+memcache size=512
+mempool size=16K
+
+[global]
+start time=5
+name=Handle 5 Tuple Load Balance
+
+[core 0]
+mode=master
+
+[core 1]
+name=Handle_LB
+task=0
+mode=lb5tuple
+rx port=if0
+tx cores=3,4,3,4
+drop=no
+
+[core 2]
+name=Handle_LB
+task=0
+mode=lb5tuple
+rx port=if1
+tx cores=3,4,3,4
+drop=no
+
+[core 3]
+name=TX_p0
+task=0
+mode=l2fwd
+dst mac=@@p0
+rx ring=yes
+tx port=if0
+drop=no
+
+[core 4]
+name=TX_p1
+task=0
+mode=l2fwd
+dst mac=@@p1
+rx ring=yes
+tx port=if1
+drop=no