diff options
author | DanielMartinBuckley <daniel.m.buckley@intel.com> | 2019-01-16 16:45:56 +0000 |
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committer | Daniel Martin Buckley <daniel.m.buckley@intel.com> | 2019-02-04 13:05:12 +0000 |
commit | 7798690cb936d49e6e05b599afe79f047c172e43 (patch) | |
tree | 0bc3e883f1ddd4650a10270102fb3755c7c3ee11 /samples/vnf_samples/nsut/prox/configs/gen_lb-2.cfg | |
parent | 1af0aec8013848bfadb81994a37d5d6b0aa121b3 (diff) |
Support NSB NFVi buffering and Load Balance on 2 and 4 ports
JIRA: YARDSTICK-1582
Most use cases support 4 ports.
Buffering support only 1 core.
Request is about supporting buffering & Load balance
for 2 and 4 ports
Change-Id: I734f9d6702825b31253a21092c86fc72e367586b
Signed-off-by: Daniel Martin Buckley <daniel.m.buckley@intel.com>
Diffstat (limited to 'samples/vnf_samples/nsut/prox/configs/gen_lb-2.cfg')
-rw-r--r-- | samples/vnf_samples/nsut/prox/configs/gen_lb-2.cfg | 114 |
1 files changed, 114 insertions, 0 deletions
diff --git a/samples/vnf_samples/nsut/prox/configs/gen_lb-2.cfg b/samples/vnf_samples/nsut/prox/configs/gen_lb-2.cfg new file mode 100644 index 000000000..c86b5f063 --- /dev/null +++ b/samples/vnf_samples/nsut/prox/configs/gen_lb-2.cfg @@ -0,0 +1,114 @@ +# Copyright (c) 2016-2017 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#; + +[eal options] +-n=4 ; force number of memory channels +no-output=no ; disable DPDK debug output + +[variables] +$sut_mac0=@@dst_mac0 +$sut_mac1=@@dst_mac1 + +[port 0] +name=p0 +mac=hardware +rx desc=4096 +tx desc=4096 +promiscuous=yes + +[port 1] +name=p1 +mac=hardware +rx desc=4096 +tx desc=1024 +promiscuous=yes + + +[defaults] +mempool size=16K + +[global] +start time=5 +name=Gen Load Balancing + +[core 0] +mode=master + +[core 1-4] +name=p0 +task=0 +mode=gen +tx port=p0 +bps=1250000000 +; Ethernet + IP + pseudo-UDP +pkt inline=${sut_mac0} 3c fd fe 9f a3 08 08 00 45 00 00 24 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 10 55 7b 00 01 02 03 04 05 06 07 +; src_ip: 10.x.x.x +random=101000000000XXXX0000XXXX000XXXXX +rand_offset=26 +; dst_ip: 10.x.x.x +random=101000000000XXXX0000XXXX000XXXXX +rand_offset=30 +; sport: [0..31] +; dport: [0..31] +random=00000000000XXXXX00000000000XXXXX +rand_offset=34 +lat pos=42 +signature pos=46 +signature=0xcafedeca + +[core 5-8] +name=p1 +task=0 +mode=gen +tx port=p1 +bps=1250000000 +; Ethernet + IP + pseudo-UDP +pkt inline=${sut_mac1} 3c fd fe 9f a3 08 08 00 45 00 00 24 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 10 55 7b 00 01 02 03 04 05 06 07 +; src_ip: 10.x.x.x +random=101000000000XXXX0000XXXX000XXXXX +rand_offset=26 +; dst_ip: 10.x.x.x +random=101000000000XXXX0000XXXX000XXXXX +rand_offset=30 +; sport: [0..31] +; dport: [0..31] +random=00000000000XXXXX00000000000XXXXX +rand_offset=34 +lat pos=42 +signature pos=46 +signature=0xcafedeca + +[core 28] +name=rec_0 +task=0 +mode=lat +rx port=p0 +lat pos=42 +signature pos=46 +signature=0xcafedeca + +[core 29] +name=rec_1 +task=0 +mode=lat +rx port=p1 +lat pos=42 +signature pos=46 +signature=0xcafedeca + + + + |