diff options
| author |   Ross Brattain <ross.b.brattain@intel.com> | 2017-11-17 09:48:39 +0000 |
|---|---|---|
| committer |   Gerrit Code Review <gerrit@opnfv.org> | 2017-11-17 09:48:39 +0000 |
| commit | 680cd988b2dfc5a0074cb829e5bae69f0bc7a6af (patch) | |
| tree | 72158375a723d38b2946030acc1033c458aaedab /samples/vnf_samples/nsut/prox/configs/gen_all-4.cfg | |
| parent | 144e467652c2b6cd11803ef78014d2748b6ec4a8 (diff) | |
| parent | 4b0bf9ea920b461b6464d0c6888b3b0bcc9a0004 (diff) | |
Merge "NSB Prox BM test case fixes for scale up"
Diffstat (limited to 'samples/vnf_samples/nsut/prox/configs/gen_all-4.cfg')
| -rw-r--r-- | samples/vnf_samples/nsut/prox/configs/gen_all-4.cfg | 96 |
1 files changed, 0 insertions, 96 deletions
diff --git a/samples/vnf_samples/nsut/prox/configs/gen_all-4.cfg b/samples/vnf_samples/nsut/prox/configs/gen_all-4.cfg deleted file mode 100644 index 7a23bf005..000000000 --- a/samples/vnf_samples/nsut/prox/configs/gen_all-4.cfg +++ /dev/null @@ -1,96 +0,0 @@ -; Copyright (c) 2017 Intel Corporation -; -; Licensed under the Apache License, Version 2.0 (the "License"); -; you may not use this file except in compliance with the License. -; You may obtain a copy of the License at -; -; http://www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, -; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. - -[eal options] --n=4 ; force number of memory channels -no-output=no ; disable DPDK debug output - -[port 0] -name=p0 -mac=70:00:00:00:00:01 -[port 1] -name=p1 -mac=70:00:00:00:00:02 -[port 2] -name=p2 -mac=70:00:00:00:00:03 -[port 3] -name=p3 -mac=70:00:00:00:00:04 - - -[defaults] -mempool size=4K - -[global] -start time=5 -name=BNG gen -[core 0] -mode=master - -[core 1] -name=cpe0 -task=0 -mode=gen -tx port=p0 -bps=1250000000 -pkt inline=50 00 00 00 00 01 70 00 00 00 00 01 08 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b - -[core 2] -name=cpe0 -task=0 -mode=gen -tx port=p1 -bps=1250000000 -pkt inline=50 00 00 00 00 02 70 00 00 00 00 02 08 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b - -[core 3] -name=cpe0 -task=0 -mode=gen -tx port=p2 -bps=1250000000 -pkt inline=50 00 00 00 00 03 70 00 00 00 00 03 08 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b - -[core 4] -name=cpe0 -task=0 -mode=gen -tx port=p3 -bps=1250000000 -pkt inline=50 00 00 00 00 04 70 00 00 00 00 04 08 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b - -[core 5] -task=0 -mode=lat -rx port=p0 -lat pos=42 - -[core 6] -task=0 -mode=lat -rx port=p1 -lat pos=42 - -[core 7] -task=0 -mode=lat -rx port=p2 -lat pos=42 - -[core 8] -task=0 -mode=lat -rx port=p3 -lat pos=42 |