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authorRoss Brattain <ross.b.brattain@intel.com>2017-04-24 23:25:48 +0200
committerRoss Brattain <ross.b.brattain@intel.com>2017-08-14 16:22:51 -0700
commita4d2958ddb727c2aaf46956cbdbf7718bfd0be89 (patch)
treedcd1293eb6306fd1a955018c26d59e7e0293c864 /samples/vnf_samples/nsut/prox/configs/gen_all-2.cfg
parentfb57af27e97bbd27e5eeeeddc766518e3c700f3c (diff)
PROX VNF and TG
PROX was added to samplevnf project https://git.opnfv.org/samplevnf/tree/VNFs/DPPD-PROX JIRA: YARDSTICK-638 Change-Id: If9875b1130c6bed87deb8720b0d8b28ede9289d9 Signed-off-by: Ross Brattain <ross.b.brattain@intel.com>
Diffstat (limited to 'samples/vnf_samples/nsut/prox/configs/gen_all-2.cfg')
-rw-r--r--samples/vnf_samples/nsut/prox/configs/gen_all-2.cfg62
1 files changed, 62 insertions, 0 deletions
diff --git a/samples/vnf_samples/nsut/prox/configs/gen_all-2.cfg b/samples/vnf_samples/nsut/prox/configs/gen_all-2.cfg
new file mode 100644
index 000000000..ac7f0475f
--- /dev/null
+++ b/samples/vnf_samples/nsut/prox/configs/gen_all-2.cfg
@@ -0,0 +1,62 @@
+; Copyright (c) 2017 Intel Corporation
+;
+; Licensed under the Apache License, Version 2.0 (the "License");
+; you may not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+; http://www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+
+[eal options]
+-n=4 ; force number of memory channels
+no-output=no ; disable DPDK debug output
+
+[port 0]
+name=p0
+mac=70:00:00:00:00:01
+[port 1]
+name=p1
+mac=70:00:00:00:00:02
+
+
+[defaults]
+mempool size=4K
+
+[global]
+start time=5
+name=BNG gen
+[core 0]
+mode=master
+
+[core 1]
+name=cpe0
+task=0
+mode=gen
+tx port=p0
+bps=1250000000
+pkt inline=50 00 00 00 00 01 70 00 00 00 00 01 08 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b
+
+[core 2]
+name=cpe0
+task=0
+mode=gen
+tx port=p1
+bps=1250000000
+pkt inline=50 00 00 00 00 02 70 00 00 00 00 02 08 00 45 00 00 1c 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 08 55 7b
+
+[core 3]
+task=0
+mode=lat
+rx port=p0
+lat pos=42
+
+[core 4]
+task=0
+mode=lat
+rx port=p1
+lat pos=42