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authorRoss Brattain <ross.b.brattain@intel.com>2017-08-11 02:52:24 +0000
committerGerrit Code Review <gerrit@opnfv.org>2017-08-11 02:52:24 +0000
commitdc3748b2f28a7e934a7f494b29399c1a6bbebfcf (patch)
tree2dfccf1d72869c55c443b7f271c6df08b933254e /samples/vnf_samples/nsut/cgnapt/cgnat.cfg
parent90b70c723c4c3b731ca3e88f79b7c7e7f1a7c20d (diff)
parentc5c5d3d675f255452c596167ed28e2ce88383af6 (diff)
Merge "Sample CGNAPT VNF"
Diffstat (limited to 'samples/vnf_samples/nsut/cgnapt/cgnat.cfg')
-rw-r--r--samples/vnf_samples/nsut/cgnapt/cgnat.cfg90
1 files changed, 90 insertions, 0 deletions
diff --git a/samples/vnf_samples/nsut/cgnapt/cgnat.cfg b/samples/vnf_samples/nsut/cgnapt/cgnat.cfg
new file mode 100644
index 000000000..8b16f57f6
--- /dev/null
+++ b/samples/vnf_samples/nsut/cgnapt/cgnat.cfg
@@ -0,0 +1,90 @@
+# Copyright (c) 2016-2017 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+[PIPELINE0]
+type = MASTER
+core = 0
+[PIPELINE1]
+type = ARPICMP
+core = 1
+
+pktq_in = SWQ4
+pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0
+; ARP route table entries (ip, mask, if_port, nh) hex values with no 0x
+arp_route_tbl = (c0102814,fffff000,1,c0102814) (c0106414,fffff000,0,c0106414)
+;arp_route_tbl = (c0122814,fffff000,3,c0122814) (c0126414,fffff000,1,c0126414)
+; Link MAC addresses in order aa:bb:cc:dd:ee:ff separated by space
+nd_route_tbl = (0064:ff9b:0:0:0:0:9810:6414,120,0,0064:ff9b:0:0:0:0:9810:6414)
+;
+; Hex values with no leading 0x, MACs in ascending port order starting @P0
+;ports_mac_list = 00:05:CA:30:21:F0 00:05:CA:30:21:F1 ;00:05:CA:30:21:F2 00:05:CA:30:21:F3
+;
+; egress (private interface) info
+pktq_in_prv = RXQ0.0
+;
+;for pub port <-> prv port mapping (prv, pub)
+prv_to_pub_map = (0,1)
+;lib_arp_debug = 0
+[PIPELINE2]
+type = TIMER
+core = 2
+n_flows = 1048576
+[PIPELINE3]
+type = TXRX
+core = 3
+pipeline_txrx_type = RXRX
+dest_if_offset = 176
+pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
+pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SWQ4
+;
+[PIPELINE4]
+type = LOADB
+core = 4
+pktq_in = SWQ0 SWQ1 SWQ2 SWQ3
+pktq_out = SWQ4 SWQ5 SWQ6 SWQ7 SWQ8 SWQ9 SWQ10 SWQ11
+outport_offset = 136; 8
+n_vnf_threads = 2
+;loadb_debug = 0
+[PIPELINE5]
+type = CGNAPT
+core = 5
+pktq_in = SWQ4 SWQ5 SWQ6 SWQ7
+pktq_out = SWQ12 SWQ13 SWQ14 SWQ15
+;
+; to make pipeline timer as 1-sec granularity
+;
+phyport_offset = 204
+n_flows = 1048576
+key_offset = 192;64
+key_size = 8
+hash_offset = 200;72
+;cgnapt_debug = 2
+;
+timer_period = 100
+max_clients_per_ip = 65535
+max_port_per_client = 10
+public_ip_port_range = 98103214:(1, 65535)
+vnf_set = (3,4,5)
+pkt_type = ipv4
+cgnapt_meta_offset = 128
+prv_que_handler = (0)
+
+
+[PIPELINE7]
+type = TXRX
+core = 7
+pipeline_txrx_type = TXTX
+dest_if_offset = 176
+pktq_in = SWQ12 SWQ13 SWQ14 SWQ15 SWQ16 SWQ17 SWQ18 SWQ19
+pktq_out = TXQ0.1 TXQ1.1 TXQ2.1 TXQ3.1 TXQ0.2 TXQ1.2 TXQ2.2 TXQ3.2