diff options
| author |   Deepak S <deepak.s@linux.intel.com> | 2017-06-20 14:14:06 -0700 |
|---|---|---|
| committer |   Ross Brattain <ross.b.brattain@intel.com> | 2017-08-08 13:31:10 -0700 |
| commit | 0230c8fa3201dcacabadb4fec5abc2d479afe723 (patch) | |
| tree | cfe5f57dd2d7130a1fda7643ac4523af86238ed2 /samples/vnf_samples/nsut/acl/acl.cfg | |
| parent | 5ce3b6f8c8b3217091e51a6041455738603d90b8 (diff) | |
Sample ACL VNF
Change-Id: I33de47ac6ca353d6c69f0d166809b4c95d3fd90f
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Edward MacGillivray <edward.s.macgillivray@intel.com>
Signed-off-by: Ross Brattain <ross.b.brattain@intel.com>
Diffstat (limited to 'samples/vnf_samples/nsut/acl/acl.cfg')
| -rw-r--r-- | samples/vnf_samples/nsut/acl/acl.cfg | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/samples/vnf_samples/nsut/acl/acl.cfg b/samples/vnf_samples/nsut/acl/acl.cfg new file mode 100644 index 000000000..fd3c51ee8 --- /dev/null +++ b/samples/vnf_samples/nsut/acl/acl.cfg @@ -0,0 +1,55 @@ +# Copyright (c) 2016-2017 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +[PIPELINE0] +type = MASTER +core = 0 +[PIPELINE1] +type = ARPICMP +core = 1 +pktq_in = SWQ4 +pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0 +arp_route_tbl = (c0102814,fffff000,1,c0102814) (c0106414,fffff000,0,c0106414) +nd_route_tbl = (0064:ff9b:0:0:0:0:9810:6414,120,0,0064:ff9b:0:0:0:0:9810:6414) +pktq_in_prv = RXQ0.0 +prv_to_pub_map = (0,1) +[PIPELINE2] +type = TXRX +core = 2 +pipeline_txrx_type = RXRX +dest_if_offset = 176 +pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0 +pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SWQ4 +[PIPELINE3] +type = LOADB +core = 3 +pktq_in = SWQ0 SWQ1 SWQ2 SWQ3 +pktq_out = SWQ4 SWQ5 SWQ6 SWQ7 SWQ8 SWQ9 SWQ10 SWQ11 +outport_offset = 136; 8 +n_vnf_threads = 2 +[PIPELINE4] +type = ACL +core = 4 +pktq_in = SWQ2 SWQ3 +pktq_out = SWQ8 SWQ9 +traffic_type = 4 +pkt_type = ipv4 +n_flows = 2000000 +[PIPELINE5] +type = TXRX +core = 5 +pipeline_txrx_type = TXTX +dest_if_offset = 176 +pktq_in = SWQ8 SWQ9 SWQ10 SWQ11 SWQ12 SWQ13 +pktq_out = TXQ0.0 TXQ1.0 TXQ0.1 TXQ1.1 TXQ0.2 TXQ1.2 |