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authorRoss Brattain <ross.b.brattain@intel.com>2017-03-15 11:50:29 -0700
committerRoss Brattain <ross.b.brattain@intel.com>2017-08-14 23:27:23 +0000
commit029bbae1bd73dd50e146d069c6080cd0f0064126 (patch)
tree478d0a153b85d62b79a5c8d3f4b2de80762a2957 /ansible/roles/vcpu_pin_set_setup/vars
parenta4d2958ddb727c2aaf46956cbdbf7718bfd0be89 (diff)
Ansible typo fix, whitespace
Change-Id: I3639ab84ab5b9e802e1bbd23674b0fbda46fdc66 Signed-off-by: Ross Brattain <ross.b.brattain@intel.com>
Diffstat (limited to 'ansible/roles/vcpu_pin_set_setup/vars')
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