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| author |   Abhijit Sinha <abhijit.sinha@intel.com> | 2018-10-12 16:53:22 +0000 |
|---|---|---|
| committer |   Gerrit Code Review <gerrit@opnfv.org> | 2018-10-12 16:53:22 +0000 |
| commit | 44420fe96dbd91b2e3b296cd237f1967dd6b8a22 (patch) | |
| tree | beebe2330f52a96596d07c9fb9b2c22766d91d93 /ansible/cpu_pin_setup.yaml | |
| parent | 111b92a6a9d9ca9c24442497e444770369fac8be (diff) | |
| parent | 425b33f5618282b0f36a1f36c91be22355264c7f (diff) | |
Merge "Add 4 port topology for agnostic vnf and Ixia tg"
Diffstat (limited to 'ansible/cpu_pin_setup.yaml')
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