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authorAl Morton <acmorton@att.com>2015-10-02 02:18:09 +0100
committerMaryam Tahhan <maryam.tahhan@intel.com>2015-10-15 16:40:35 +0000
commitfeab46f1583db64f69f38fa01cd68371c1c60953 (patch)
treeafcf9dbc4ece4eb75c0509f233dd27c1e4f5dec5 /docs/to-be-reorganized
parent8e49abe59fa559e319ce5a956c74881a6e0184a7 (diff)
test_spec: LTD: Memory BW Test - probable issue caused by md to rst conversion
The following text in the Description needs to be formatted as a list in .RST: Furthermore: - the ratio of reads to writes should be recorded. JIRA: VSPERF-109 Change-Id: I3b6c819d1ac07cc466c747d3552cbcc4de5f34bf Signed-off-by: Al Morton <acmorton@att.com> Reviewed-by: Maryam Tahhan <maryam.tahhan@intel.com> Reviewed-by: Billy O'Mahony<billy.o.mahony@intel.com> Reviewed-by: Gene Snider <eugene.snider@huawei.com>
Diffstat (limited to 'docs/to-be-reorganized')
-rw-r--r--docs/to-be-reorganized/vswitchperf_ltd.rst25
1 files changed, 14 insertions, 11 deletions
diff --git a/docs/to-be-reorganized/vswitchperf_ltd.rst b/docs/to-be-reorganized/vswitchperf_ltd.rst
index ee89c98b..25c8cfc2 100644
--- a/docs/to-be-reorganized/vswitchperf_ltd.rst
+++ b/docs/to-be-reorganized/vswitchperf_ltd.rst
@@ -1814,17 +1814,20 @@ Test ID: LTD.MemoryBandwidth.RFC2544.0PacketLoss.Scalability
random data to random addresses in unused physical memory. The random
nature of the data and addresses is intended to consume cache, exercise
main memory access (as opposed to cache) and exercise all memory buses
- equally. Furthermore: - the ratio of reads to writes should be recorded.
- A ratio of 1:1 SHOULD be used. - the reads and writes MUST be of
- cache-line size and be cache-line aligned. - in NUMA architectures
- memory access SHOULD be local to the core's node. Whether only local
- memory or a mix of local and remote memory is used MUST be recorded. -
- the memory bandwidth (reads plus writes) used per-core MUST be recorded;
- the test MUST be run with a per-core memory bandwidth equal to half the
- maximum system memory bandwidth divided by the number of cores. The test
- MAY be run with other values for the per-core memory bandwidth. - the
- test MAY also be run with the memory intensive application running on
- all cores.
+ equally. Furthermore:
+
+ - the ratio of reads to writes should be recorded. A ratio of 1:1
+ SHOULD be used.
+ - the reads and writes MUST be of cache-line size and be cache-line aligned.
+ - in NUMA architectures memory access SHOULD be local to the core's node.
+ Whether only local memory or a mix of local and remote memory is used
+ MUST be recorded.
+ - the memory bandwidth (reads plus writes) used per-core MUST be recorded;
+ the test MUST be run with a per-core memory bandwidth equal to half the
+ maximum system memory bandwidth divided by the number of cores. The test
+ MAY be run with other values for the per-core memory bandwidth.
+ - the test MAY also be run with the memory intensive application running
+ on all cores.
Under these conditions the DUT's 0% packet loss throughput is determined
as per LTD.Throughput.RFC2544.PacketLossRatio.