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| author |   Radek Zetik <radekx.zetik@intel.com> | 2016-01-25 12:22:46 +0000 |
|---|---|---|
| committer |   Maryam Tahhan <maryam.tahhan@intel.com> | 2016-01-25 16:15:17 +0000 |
| commit | 11ea896d3dee85a79316c57838adef8807784359 (patch) | |
| tree | 34b532692f6a508fb724909170f055983b7e76b7 /core/component_factory.py | |
| parent | da081ab2603eb34baf7d7fe7b61f681ef15d865e (diff) | |
VSPERF docs: Patches for Design Document
Routing Table Figure has an odd description
for the table#1 description.
Connectivity to the DUT is assumed, could provide
example directions. Suggest a new section.
JIRA: VSPERF-178
JIRA: VSPERF-179
Change-Id: I38e48034a9029d4a8969affdddef5b281dc8eba3
Signed-off-by: Radek Zetik <radekx.zetik@intel.com>
Reviewed-by: Maryam Tahhan <maryam.tahhan@intel.com>
Reviewed-by: Brian Castelli <brian.castelli@spirent.com>
Reviewed-by: Al Morton <acmorton@att.com>
Reviewed-by: Tv Rao <tv.rao@freescale.com>
Diffstat (limited to 'core/component_factory.py')
0 files changed, 0 insertions, 0 deletions