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| author |   Dino Simeon Madarang <dino.simeonx.madarang@intel.com> | 2016-02-02 08:32:01 +0000 |
|---|---|---|
| committer |   Maryam Tahhan <maryam.tahhan@intel.com> | 2016-03-16 15:05:00 +0000 |
| commit | 8ee2450bd267c7dc173f62909a8a4ebe13feab84 (patch) | |
| tree | 26c52f865e0470d5cc6228046196c1338399acc5 /core/loader/loader.py | |
| parent | bc1c22c6391745759c8e85f5d4070abf259269d8 (diff) | |
tunneling: Vanilla OVS decapsulation tests
Add Vanilla OVS VXLAN/GRE/GENEVE decapsulation tests
Recent changes:
* Line wrap
* Fix GENEVE IP settings
* Add GRE and GENEVE steps to integration.rst
* Add DUT_NIC1_MAC and DUT_NIC2_MAC
* Remove unnecessary call to vswitch.set_tunnel_arp
* Move optional VXLAN/GRE/GENEVE decap settings to a different section
* Add tunnel type to report files md and rst
* Fix typo error: l4 to L4 in conf/integration/03_traffic.conf
Change-Id: I8a43521668d5870ec893aed1df49467f0a84a07d
JIRA: VSPERF-180
Signed-off-by: Dino Simeon Madarang <dino.simeonx.madarang@intel.com>
Signed-off-by: Martin Klozik <martinx.klozik@intel.com>
Reviewed-by: Maryam Tahhan <maryam.tahhan@intel.com>
Reviewed-by: Al Morton <acmorton@att.com>
Reviewed-by: Brian Castelli <brian.castelli@spirent.com>
Diffstat (limited to 'core/loader/loader.py')
0 files changed, 0 insertions, 0 deletions