Update git submodules - opnfvdocs - Documentation for OPNFV releases - Now on GitLab at https://gitlab.com/anuket/opnfvdocs

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author	Abhijit Sinha <abhijit.sinha@intel.com>	2018-05-17 10:47:49 +0000
committer	Gerrit Code Review <gerrit@opnfv.org>	2018-05-17 10:47:49 +0000
commit	4d0c878473b9ce977e219b08d88c050d6c20c666 (patch)
tree	74874889787bc9188dd6ee2d8ec3ed9401a2722e /docs/submodules
parent	52cf3d3936d15096d34613f3094e5745ac287fd6 (diff)

Update git submodules

* Update docs/submodules/yardstick from branch 'master' - Merge "Fix PEP8 errors in prox_binseach" - Fix PEP8 errors in prox_binseach There were some pep8 errors in the prox_binsearch.py file. These are fixed here. JIRA: YARDSTICK-1173 Change-Id: I817bba89c6ba298bb0f27b2538aa7585cb286754 Signed-off-by: Abhijit Sinha <abhijit.sinha@intel.com>

Diffstat (limited to 'docs/submodules')

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docs/submodules/yardstick

1 files changed, 0 insertions, 0 deletions

// Helpers for working with i8259 interrupt controller. // // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net> // Copyright (C) 2002 MandrakeSoft S.A. // // This file may be distributed under the terms of the GNU LGPLv3 license. #include "biosvar.h" // SET_IVT #include "config.h" // CONFIG_* #include "output.h" // dprintf #include "pic.h" // pic_* u16 pic_irqmask_read(void) { return inb(PORT_PIC1_DATA) | (inb(PORT_PIC2_DATA) << 8); } void pic_irqmask_write(u16 mask) { outb(mask, PORT_PIC1_DATA); outb(mask >> 8, PORT_PIC2_DATA); } void pic_irqmask_mask(u16 off, u16 on) { u8 pic1off = off, pic1on = on, pic2off = off>>8, pic2on = on>>8; outb((inb(PORT_PIC1_DATA) & ~pic1off) | pic1on, PORT_PIC1_DATA); outb((inb(PORT_PIC2_DATA) & ~pic2off) | pic2on, PORT_PIC2_DATA); } void pic_reset(u8 irq0, u8 irq8) { // Send ICW1 (select OCW1 + will send ICW4) outb(0x11, PORT_PIC1_CMD); outb(0x11, PORT_PIC2_CMD); // Send ICW2 (base irqs: 0x08-0x0f for irq0-7, 0x70-0x77 for irq8-15) outb(irq0, PORT_PIC1_DATA); outb(irq8, PORT_PIC2_DATA); // Send ICW3 (cascaded pic ids) outb(0x04, PORT_PIC1_DATA); outb(0x02, PORT_PIC2_DATA); // Send ICW4 (enable 8086 mode) outb(0x01, PORT_PIC1_DATA); outb(0x01, PORT_PIC2_DATA); // Mask all irqs (except cascaded PIC2 irq) pic_irqmask_write(PIC_IRQMASK_DEFAULT); } void pic_setup(void) { dprintf(3, "init pic\n"); pic_reset(BIOS_HWIRQ0_VECTOR, BIOS_HWIRQ8_VECTOR); } void enable_hwirq(int hwirq, struct segoff_s func) { pic_irqmask_mask(1 << hwirq, 0); int vector; if (hwirq < 8) vector = BIOS_HWIRQ0_VECTOR + hwirq; else vector = BIOS_HWIRQ8_VECTOR + hwirq - 8; SET_IVT(vector, func); } static u8 pic_isr1_read(void) { // 0x0b == select OCW1 + read ISR outb(0x0b, PORT_PIC1_CMD); return inb(PORT_PIC1_CMD); } static u8 pic_isr2_read(void) { // 0x0b == select OCW1 + read ISR outb(0x0b, PORT_PIC2_CMD); return inb(PORT_PIC2_CMD); } // Handler for otherwise unused hardware irqs. void VISIBLE16 handle_hwpic1(struct bregs *regs) { dprintf(DEBUG_ISR_hwpic1, "handle_hwpic1 irq=%x\n", pic_isr1_read()); pic_eoi1(); } void VISIBLE16 handle_hwpic2(struct bregs *regs) { dprintf(DEBUG_ISR_hwpic2, "handle_hwpic2 irq=%x\n", pic_isr2_read()); pic_eoi2(); }


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