1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
|
/*
* (C) Copyright 2004
* Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
*
* (C) Copyright 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* ------------------------------------------------------------------------- */
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC8245 1
#define CONFIG_HIDDEN_DRAGON 1
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#if 0
#define USE_DINK32 1
#else
#undef USE_DINK32
#endif
#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
#define CONFIG_BAUDRATE 9600
#define CONFIG_DRAM_SPEED 100 /* MHz */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define PCI_ENET0_IOADDR 0x80000000
#define PCI_ENET0_MEMADDR 0x80000000
#define PCI_ENET1_IOADDR 0x81000000
#define PCI_ENET1_MEMADDR 0x81000000
#define CONFIG_RTL8139
/* Make sure the ethaddr can be overwritten
TODO: Remove this on final product
*/
#define CONFIG_ENV_OVERWRITE
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_MAX_RAM_SIZE 0x02000000
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
#if defined (USE_DINK32)
#define CONFIG_SYS_MONITOR_LEN 0x00030000
#define CONFIG_SYS_MONITOR_BASE 0x00090000
#define CONFIG_SYS_RAMBOOT 1
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#else
#undef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN 0x00030000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#endif
#define CONFIG_SYS_FLASH_BASE 0xFFE00000
#define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
#define CONFIG_SYS_EUMB_ADDR 0xFC000000
#define CONFIG_SYS_ISA_MEM 0xFD000000
#define CONFIG_SYS_ISA_IO 0xFE000000
#define CONFIG_SYS_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */
#define CONFIG_SYS_FLASH_RANGE_SIZE 0x00200000
#define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */
/*
* select i2c support configuration
*
* Supported configurations are {none, software, hardware} drivers.
* If the software driver is chosen, there are some additional
* configuration items that the driver uses to drive the port pins.
*/
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#ifdef CONFIG_SYS_I2C_SOFT
#error "Soft I2C is not configured properly. Please review!"
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
else iop->pdat &= ~0x00010000
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#endif /* CONFIG_SYS_I2C_SOFT */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */
#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
/* TODO: Change this to VIA686A */
/*
* NS87308 Configuration
*/
#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
#define CONFIG_SYS_NS87308_BADDR_10 1
#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \
CONFIG_SYS_NS87308_UART2 | \
CONFIG_SYS_NS87308_POWRMAN | \
CONFIG_SYS_NS87308_RTC_APC )
#undef CONFIG_SYS_NS87308_PS2MOD
#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
#define CONFIG_SYS_NS87308_CS0_CONF 0x30
#define CONFIG_SYS_NS87308_CS1_BASE 0x0075
#define CONFIG_SYS_NS87308_CS1_CONF 0x30
#define CONFIG_SYS_NS87308_CS2_BASE 0x0074
#define CONFIG_SYS_NS87308_CS2_CONF 0x30
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#if (CONFIG_CONS_INDEX > 2)
#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000
#else
#define CONFIG_SYS_NS16550_CLK 1843200
#endif
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
/* the following are for SDRAM only*/
#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
#if 0
#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
#endif
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
#define CONFIG_SYS_EXTROM 1
#define CONFIG_SYS_REGDIMM 0
/* memory bank settings*/
/*
* only bits 20-29 are actually used from these vales to set the
* start/end address the upper two bits will be 0, and the lower 20
* bits will be set to 0x00000 for a start address, or 0xfffff for an
* end address
*/
#define CONFIG_SYS_BANK0_START 0x00000000
#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE 1
#define CONFIG_SYS_BANK1_START 0x3ff00000
#define CONFIG_SYS_BANK1_END 0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE 0
#define CONFIG_SYS_BANK2_START 0x3ff00000
#define CONFIG_SYS_BANK2_END 0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE 0
#define CONFIG_SYS_BANK3_START 0x3ff00000
#define CONFIG_SYS_BANK3_END 0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE 0
#define CONFIG_SYS_BANK4_START 0x00000000
#define CONFIG_SYS_BANK4_END 0x00000000
#define CONFIG_SYS_BANK4_ENABLE 0
#define CONFIG_SYS_BANK5_START 0x00000000
#define CONFIG_SYS_BANK5_END 0x00000000
#define CONFIG_SYS_BANK5_ENABLE 0
#define CONFIG_SYS_BANK6_START 0x00000000
#define CONFIG_SYS_BANK6_END 0x00000000
#define CONFIG_SYS_BANK6_ENABLE 0
#define CONFIG_SYS_BANK7_START 0x00000000
#define CONFIG_SYS_BANK7_END 0x00000000
#define CONFIG_SYS_BANK7_ENABLE 0
/*
* Memory bank enable bitmask, specifying which of the banks defined above
are actually present. MSB is for bank #7, LSB is for bank #0.
*/
#define CONFIG_SYS_BANK_ENABLE 0x01
#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
/* see 8240 book for bit definitions */
#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
/* currently accessed page in memory */
/* see 8240 book for details */
/* SDRAM 0 - 256MB */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
/* stack in DCACHE @ 1GB (no backing mem) */
#if defined(USE_DINK32)
#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
#else
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#endif
/* PCI memory */
#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
/* Flash, config addrs, etc */
#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 36 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/* values according to the manual */
#define CONFIG_DRAM_50MHZ 1
#define CONFIG_SDRAM_50MHZ
#undef NR_8259_INTS
#define NR_8259_INTS 1
#define CONFIG_DISK_SPINUP_TIME 1000000
#endif /* __CONFIG_H */
|
