1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
|
/*
* QEMU Xilinx OPB Interrupt Controller.
*
* Copyright (c) 2009 Edgar E. Iglesias.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "hw/sysbus.h"
#include "hw/hw.h"
#define D(x)
#define R_ISR 0
#define R_IPR 1
#define R_IER 2
#define R_IAR 3
#define R_SIE 4
#define R_CIE 5
#define R_IVR 6
#define R_MER 7
#define R_MAX 8
#define TYPE_XILINX_INTC "xlnx.xps-intc"
#define XILINX_INTC(obj) OBJECT_CHECK(struct xlx_pic, (obj), TYPE_XILINX_INTC)
struct xlx_pic
{
SysBusDevice parent_obj;
MemoryRegion mmio;
qemu_irq parent_irq;
/* Configuration reg chosen at synthesis-time. QEMU populates
the bits at board-setup. */
uint32_t c_kind_of_intr;
/* Runtime control registers. */
uint32_t regs[R_MAX];
/* state of the interrupt input pins */
uint32_t irq_pin_state;
};
static void update_irq(struct xlx_pic *p)
{
uint32_t i;
/* level triggered interrupt */
if (p->regs[R_MER] & 2) {
p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr;
}
/* Update the pending register. */
p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER];
/* Update the vector register. */
for (i = 0; i < 32; i++) {
if (p->regs[R_IPR] & (1U << i)) {
break;
}
}
if (i == 32)
i = ~0;
p->regs[R_IVR] = i;
qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);
}
static uint64_t
pic_read(void *opaque, hwaddr addr, unsigned int size)
{
struct xlx_pic *p = opaque;
uint32_t r = 0;
addr >>= 2;
switch (addr)
{
default:
if (addr < ARRAY_SIZE(p->regs))
r = p->regs[addr];
break;
}
D(printf("%s %x=%x\n", __func__, addr * 4, r));
return r;
}
static void
pic_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_pic *p = opaque;
uint32_t value = val64;
addr >>= 2;
D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
switch (addr)
{
case R_IAR:
p->regs[R_ISR] &= ~value; /* ACK. */
break;
case R_SIE:
p->regs[R_IER] |= value; /* Atomic set ie. */
break;
case R_CIE:
p->regs[R_IER] &= ~value; /* Atomic clear ie. */
break;
case R_MER:
p->regs[R_MER] = value & 0x3;
break;
case R_ISR:
if ((p->regs[R_MER] & 2)) {
break;
}
/* fallthrough */
default:
if (addr < ARRAY_SIZE(p->regs))
p->regs[addr] = value;
break;
}
update_irq(p);
}
static const MemoryRegionOps pic_ops = {
.read = pic_read,
.write = pic_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
}
};
static void irq_handler(void *opaque, int irq, int level)
{
struct xlx_pic *p = opaque;
/* edge triggered interrupt */
if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
p->regs[R_ISR] |= (level << irq);
}
p->irq_pin_state &= ~(1 << irq);
p->irq_pin_state |= level << irq;
update_irq(p);
}
static void xilinx_intc_init(Object *obj)
{
struct xlx_pic *p = XILINX_INTC(obj);
qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc",
R_MAX * 4);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio);
}
static Property xilinx_intc_properties[] = {
DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void xilinx_intc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->props = xilinx_intc_properties;
}
static const TypeInfo xilinx_intc_info = {
.name = TYPE_XILINX_INTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct xlx_pic),
.instance_init = xilinx_intc_init,
.class_init = xilinx_intc_class_init,
};
static void xilinx_intc_register_types(void)
{
type_register_static(&xilinx_intc_info);
}
type_init(xilinx_intc_register_types)
|
