summaryrefslogtreecommitdiffstats
path: root/kernel/include/linux/mfd/samsung/irq.h
blob: 667aa40486dd41ca2e0ade8f2cee7c6e35c470bd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
/* irq.h
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd
 *              http://www.samsung.com
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 */

#ifndef __LINUX_MFD_SEC_IRQ_H
#define __LINUX_MFD_SEC_IRQ_H

enum s2mpa01_irq {
	S2MPA01_IRQ_PWRONF,
	S2MPA01_IRQ_PWRONR,
	S2MPA01_IRQ_JIGONBF,
	S2MPA01_IRQ_JIGONBR,
	S2MPA01_IRQ_ACOKBF,
	S2MPA01_IRQ_ACOKBR,
	S2MPA01_IRQ_PWRON1S,
	S2MPA01_IRQ_MRB,

	S2MPA01_IRQ_RTC60S,
	S2MPA01_IRQ_RTCA1,
	S2MPA01_IRQ_RTCA0,
	S2MPA01_IRQ_SMPL,
	S2MPA01_IRQ_RTC1S,
	S2MPA01_IRQ_WTSR,

	S2MPA01_IRQ_INT120C,
	S2MPA01_IRQ_INT140C,
	S2MPA01_IRQ_LDO3_TSD,
	S2MPA01_IRQ_B16_TSD,
	S2MPA01_IRQ_B24_TSD,
	S2MPA01_IRQ_B35_TSD,

	S2MPA01_IRQ_NR,
};

#define S2MPA01_IRQ_PWRONF_MASK		(1 << 0)
#define S2MPA01_IRQ_PWRONR_MASK		(1 << 1)
#define S2MPA01_IRQ_JIGONBF_MASK	(1 << 2)
#define S2MPA01_IRQ_JIGONBR_MASK	(1 << 3)
#define S2MPA01_IRQ_ACOKBF_MASK		(1 << 4)
#define S2MPA01_IRQ_ACOKBR_MASK		(1 << 5)
#define S2MPA01_IRQ_PWRON1S_MASK	(1 << 6)
#define S2MPA01_IRQ_MRB_MASK		(1 << 7)

#define S2MPA01_IRQ_RTC60S_MASK		(1 << 0)
#define S2MPA01_IRQ_RTCA1_MASK		(1 << 1)
#define S2MPA01_IRQ_RTCA0_MASK		(1 << 2)
#define S2MPA01_IRQ_SMPL_MASK		(1 << 3)
#define S2MPA01_IRQ_RTC1S_MASK		(1 << 4)
#define S2MPA01_IRQ_WTSR_MASK		(1 << 5)

#define S2MPA01_IRQ_INT120C_MASK	(1 << 0)
#define S2MPA01_IRQ_INT140C_MASK	(1 << 1)
#define S2MPA01_IRQ_LDO3_TSD_MASK	(1 << 2)
#define S2MPA01_IRQ_B16_TSD_MASK	(1 << 3)
#define S2MPA01_IRQ_B24_TSD_MASK	(1 << 4)
#define S2MPA01_IRQ_B35_TSD_MASK	(1 << 5)

enum s2mps11_irq {
	S2MPS11_IRQ_PWRONF,
	S2MPS11_IRQ_PWRONR,
	S2MPS11_IRQ_JIGONBF,
	S2MPS11_IRQ_JIGONBR,
	S2MPS11_IRQ_ACOKBF,
	S2MPS11_IRQ_ACOKBR,
	S2MPS11_IRQ_PWRON1S,
	S2MPS11_IRQ_MRB,

	S2MPS11_IRQ_RTC60S,
	S2MPS11_IRQ_RTCA1,
	S2MPS11_IRQ_RTCA0,
	S2MPS11_IRQ_SMPL,
	S2MPS11_IRQ_RTC1S,
	S2MPS11_IRQ_WTSR,

	S2MPS11_IRQ_INT120C,
	S2MPS11_IRQ_INT140C,

	S2MPS11_IRQ_NR,
};

#define S2MPS11_IRQ_PWRONF_MASK		(1 << 0)
#define S2MPS11_IRQ_PWRONR_MASK		(1 << 1)
#define S2MPS11_IRQ_JIGONBF_MASK	(1 << 2)
#define S2MPS11_IRQ_JIGONBR_MASK	(1 << 3)
#define S2MPS11_IRQ_ACOKBF_MASK		(1 << 4)
#define S2MPS11_IRQ_ACOKBR_MASK		(1 << 5)
#define S2MPS11_IRQ_PWRON1S_MASK	(1 << 6)
#define S2MPS11_IRQ_MRB_MASK		(1 << 7)

#define S2MPS11_IRQ_RTC60S_MASK		(1 << 0)
#define S2MPS11_IRQ_RTCA1_MASK		(1 << 1)
#define S2MPS11_IRQ_RTCA0_MASK		(1 << 2)
#define S2MPS11_IRQ_SMPL_MASK		(1 << 3)
#define S2MPS11_IRQ_RTC1S_MASK		(1 << 4)
#define S2MPS11_IRQ_WTSR_MASK		(1 << 5)

#define S2MPS11_IRQ_INT120C_MASK	(1 << 0)
#define S2MPS11_IRQ_INT140C_MASK	(1 << 1)

enum s2mps14_irq {
	S2MPS14_IRQ_PWRONF,
	S2MPS14_IRQ_PWRONR,
	S2MPS14_IRQ_JIGONBF,
	S2MPS14_IRQ_JIGONBR,
	S2MPS14_IRQ_ACOKBF,
	S2MPS14_IRQ_ACOKBR,
	S2MPS14_IRQ_PWRON1S,
	S2MPS14_IRQ_MRB,

	S2MPS14_IRQ_RTC60S,
	S2MPS14_IRQ_RTCA1,
	S2MPS14_IRQ_RTCA0,
	S2MPS14_IRQ_SMPL,
	S2MPS14_IRQ_RTC1S,
	S2MPS14_IRQ_WTSR,

	S2MPS14_IRQ_INT120C,
	S2MPS14_IRQ_INT140C,
	S2MPS14_IRQ_TSD,

	S2MPS14_IRQ_NR,
};

enum s2mpu02_irq {
	S2MPU02_IRQ_PWRONF,
	S2MPU02_IRQ_PWRONR,
	S2MPU02_IRQ_JIGONBF,
	S2MPU02_IRQ_JIGONBR,
	S2MPU02_IRQ_ACOKBF,
	S2MPU02_IRQ_ACOKBR,
	S2MPU02_IRQ_PWRON1S,
	S2MPU02_IRQ_MRB,

	S2MPU02_IRQ_RTC60S,
	S2MPU02_IRQ_RTCA1,
	S2MPU02_IRQ_RTCA0,
	S2MPU02_IRQ_SMPL,
	S2MPU02_IRQ_RTC1S,
	S2MPU02_IRQ_WTSR,

	S2MPU02_IRQ_INT120C,
	S2MPU02_IRQ_INT140C,
	S2MPU02_IRQ_TSD,

	S2MPU02_IRQ_NR,
};

/* Masks for interrupts are the same as in s2mps11 */
#define S2MPS14_IRQ_TSD_MASK		(1 << 2)

enum s5m8767_irq {
	S5M8767_IRQ_PWRR,
	S5M8767_IRQ_PWRF,
	S5M8767_IRQ_PWR1S,
	S5M8767_IRQ_JIGR,
	S5M8767_IRQ_JIGF,
	S5M8767_IRQ_LOWBAT2,
	S5M8767_IRQ_LOWBAT1,

	S5M8767_IRQ_MRB,
	S5M8767_IRQ_DVSOK2,
	S5M8767_IRQ_DVSOK3,
	S5M8767_IRQ_DVSOK4,

	S5M8767_IRQ_RTC60S,
	S5M8767_IRQ_RTCA1,
	S5M8767_IRQ_RTCA2,
	S5M8767_IRQ_SMPL,
	S5M8767_IRQ_RTC1S,
	S5M8767_IRQ_WTSR,

	S5M8767_IRQ_NR,
};

#define S5M8767_IRQ_PWRR_MASK		(1 << 0)
#define S5M8767_IRQ_PWRF_MASK		(1 << 1)
#define S5M8767_IRQ_PWR1S_MASK		(1 << 3)
#define S5M8767_IRQ_JIGR_MASK		(1 << 4)
#define S5M8767_IRQ_JIGF_MASK		(1 << 5)
#define S5M8767_IRQ_LOWBAT2_MASK	(1 << 6)
#define S5M8767_IRQ_LOWBAT1_MASK	(1 << 7)

#define S5M8767_IRQ_MRB_MASK		(1 << 2)
#define S5M8767_IRQ_DVSOK2_MASK		(1 << 3)
#define S5M8767_IRQ_DVSOK3_MASK		(1 << 4)
#define S5M8767_IRQ_DVSOK4_MASK		(1 << 5)

#define S5M8767_IRQ_RTC60S_MASK		(1 << 0)
#define S5M8767_IRQ_RTCA1_MASK		(1 << 1)
#define S5M8767_IRQ_RTCA2_MASK		(1 << 2)
#define S5M8767_IRQ_SMPL_MASK		(1 << 3)
#define S5M8767_IRQ_RTC1S_MASK		(1 << 4)
#define S5M8767_IRQ_WTSR_MASK		(1 << 5)

enum s5m8763_irq {
	S5M8763_IRQ_DCINF,
	S5M8763_IRQ_DCINR,
	S5M8763_IRQ_JIGF,
	S5M8763_IRQ_JIGR,
	S5M8763_IRQ_PWRONF,
	S5M8763_IRQ_PWRONR,

	S5M8763_IRQ_WTSREVNT,
	S5M8763_IRQ_SMPLEVNT,
	S5M8763_IRQ_ALARM1,
	S5M8763_IRQ_ALARM0,

	S5M8763_IRQ_ONKEY1S,
	S5M8763_IRQ_TOPOFFR,
	S5M8763_IRQ_DCINOVPR,
	S5M8763_IRQ_CHGRSTF,
	S5M8763_IRQ_DONER,
	S5M8763_IRQ_CHGFAULT,

	S5M8763_IRQ_LOBAT1,
	S5M8763_IRQ_LOBAT2,

	S5M8763_IRQ_NR,
};

#define S5M8763_IRQ_DCINF_MASK		(1 << 2)
#define S5M8763_IRQ_DCINR_MASK		(1 << 3)
#define S5M8763_IRQ_JIGF_MASK		(1 << 4)
#define S5M8763_IRQ_JIGR_MASK		(1 << 5)
#define S5M8763_IRQ_PWRONF_MASK		(1 << 6)
#define S5M8763_IRQ_PWRONR_MASK		(1 << 7)

#define S5M8763_IRQ_WTSREVNT_MASK	(1 << 0)
#define S5M8763_IRQ_SMPLEVNT_MASK	(1 << 1)
#define S5M8763_IRQ_ALARM1_MASK		(1 << 2)
#define S5M8763_IRQ_ALARM0_MASK		(1 << 3)

#define S5M8763_IRQ_ONKEY1S_MASK	(1 << 0)
#define S5M8763_IRQ_TOPOFFR_MASK	(1 << 2)
#define S5M8763_IRQ_DCINOVPR_MASK	(1 << 3)
#define S5M8763_IRQ_CHGRSTF_MASK	(1 << 4)
#define S5M8763_IRQ_DONER_MASK		(1 << 5)
#define S5M8763_IRQ_CHGFAULT_MASK	(1 << 7)

#define S5M8763_IRQ_LOBAT1_MASK		(1 << 0)
#define S5M8763_IRQ_LOBAT2_MASK		(1 << 1)

#define S5M8763_ENRAMP                  (1 << 4)

#endif /*  __LINUX_MFD_SEC_IRQ_H */