summaryrefslogtreecommitdiffstats
path: root/kernel/drivers/net/wireless/rtlwifi/rtl8192ee/pwrseq.h
blob: 781eeaa6af4953f9a9baa19ee4e5ae02c97358f7 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
/******************************************************************************
 *
 * Copyright(c) 2009-2014  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#ifndef __RTL92E_PWRSEQ_H__
#define __RTL92E_PWRSEQ_H__

#include "../pwrseqcmd.h"
/**
 *	Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd
 *	There are 6 HW Power States:
 *	0: POFF--Power Off
 *	1: PDN--Power Down
 *	2: CARDEMU--Card Emulation
 *	3: ACT--Active Mode
 *	4: LPS--Low Power State
 *	5: SUS--Suspend
 *
 *	The transision from different states are defined below
 *	TRANS_CARDEMU_TO_ACT
 *	TRANS_ACT_TO_CARDEMU
 *	TRANS_CARDEMU_TO_SUS
 *	TRANS_SUS_TO_CARDEMU
 *	TRANS_CARDEMU_TO_PDN
 *	TRANS_ACT_TO_LPS
 *	TRANS_LPS_TO_ACT
 *
 *	TRANS_END
 *	PWR SEQ Version: rtl8192E_PwrSeq_V09.h
 */

#define	RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS	18
#define	RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS	18
#define	RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS	18
#define	RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS	18
#define	RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS	18
#define	RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS	18
#define	RTL8192E_TRANS_ACT_TO_LPS_STEPS		23
#define	RTL8192E_TRANS_LPS_TO_ACT_STEPS		23
#define	RTL8192E_TRANS_END_STEPS		1

#define RTL8192E_TRANS_CARDEMU_TO_ACT					\
	/* format */							\
	/* comments here */						\
	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
	/* disable HWPDN 0x04[15]=0*/					\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},			\
	/* disable SW LPS 0x04[10]=0*/					\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0},			\
	/* disable WL suspend*/						\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},		\
	/* wait till 0x04[17] = 1    power ready*/			\
	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)},		\
	/* release WLON reset  0x04[16]=1*/				\
	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
	/* polling until return 0*/					\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
	/**/								\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},

#define RTL8192E_TRANS_ACT_TO_CARDEMU					\
	/* format */							\
	/* comments here */						\
	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
	/*0x1F[7:0] = 0 turn off RF*/					\
	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0},			\
	/*0x4C[23]=0x4E[7]=0, switch DPDT_SEL_P output from register 0x65[2] */\
	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},			\
	/*0x04[9] = 1 turn off MAC by HW state machine*/		\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)},		\
	/*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0},

#define RTL8192E_TRANS_CARDEMU_TO_SUS					\
	/* format */							\
	/* comments here */						\
	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
	/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/		\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\
	/*0x04[12:11] = 2b'01 enable WL suspend*/			\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
	 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,	\
	 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},				\
	/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/		\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
	/*Set SDIO suspend local register*/				\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
	 /*wait power state to suspend*/				\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},

#define RTL8192E_TRANS_SUS_TO_CARDEMU					\
	/* format */							\
	/* comments here */						\
	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
	/*Set SDIO suspend local register*/				\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0},			\
	/*wait power state to suspend*/					\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)},		\
	/*0x04[12:11] = 2b'01enable WL suspend*/			\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},

#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS				\
	/* format */							\
	/* comments here */						\
	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
	/*0x07=0x20 , SOP option to disable BG/MB*/			\
	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x20},			\
	/*Unlock small LDO Register*/					\
	{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)},		\
	/*Disable small LDO*/						\
	{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0},			\
	/*0x04[12:11] = 2b'01 enable WL suspend*/			\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
	 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,		\
	 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},				\
	/*0x04[10] = 1, enable SW LPS*/					\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)},		\
	/*Set SDIO suspend local register*/				\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
	/*wait power state to suspend*/					\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), 0},

#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU				\
	/* format */							\
	/* comments here */						\
	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
	/*Set SDIO suspend local register*/				\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0},			\
	/*wait power state to suspend*/					\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)},		\
	/*Enable small LDO*/						\
	{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)},		\
	/*Lock small LDO Register*/					\
	{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0},			\
	/*0x04[12:11] = 2b'01enable WL suspend*/			\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},

#define RTL8192E_TRANS_CARDEMU_TO_PDN					\
	/* format */							\
	/* comments here */						\
	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
	/* 0x04[16] = 0*/						\
	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0},			\
	/* 0x04[15] = 1*/						\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)},

#define RTL8192E_TRANS_PDN_TO_CARDEMU					\
	/* format */							\
	/* comments here */						\
	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
	/* 0x04[15] = 0*/						\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},

#define RTL8192E_TRANS_ACT_TO_LPS					\
	/* format */							\
	/* comments here */						\
	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
	/*PCIe DMA stop*/						\
	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},			\
	/*Tx Pause*/							\
	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},			\
	/*Should be zero if no packet is transmitting*/			\
	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},			\
	/*Should be zero if no packet is transmitting*/			\
	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},			\
	/*Should be zero if no packet is transmitting*/			\
	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},			\
	/*Should be zero if no packet is transmitting*/			\
	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0},			\
	/*CCK and OFDM are disabled,and clock are gated*/		\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0},			\
	/*Delay 1us*/							\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},		\
	/*Whole BB is reset*/						\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0},			\
	/*Reset MAC TRX*/						\
	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x03},			\
	/*check if removed later*/					\
	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0},			\
	/*When driver enter Sus/ Disable, enable LOP for BT*/		\
	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x00},			\
	/*Respond TxOK to scheduler*/					\
	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)},

#define RTL8192E_TRANS_LPS_TO_ACT					\
	/* format */							\
	/* comments here */						\
	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
	/*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\
	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, 0xFF, 0x84},		\
	/*USB RPWM*/							\
	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84},			\
	/*PCIe RPWM*/							\
	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84},			\
	/*Delay*/							\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS},		\
	/*0x08[4] = 0 switch TSF to 40M*/				\
	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0},			\
	/*Polling 0x109[7]=0  TSF in 40M*/				\
	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(7), 0},		\
	/*0x101[1] = 1*/						\
	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)},		\
	/*0x100[7:0] = 0xFF  enable WMAC TRX*/				\
	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},			\
	/* 0x02[1:0] = 2b'11 enable BB macro*/				\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\
	/*0x522 = 0*/							\
	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0},			\
	/*Clear ISR*/							\
	{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},

#define RTL8192E_TRANS_END						\
	/* format */							\
	/* comments here */						\
	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	 0, PWR_CMD_END, 0, 0},

extern struct wlan_pwr_cfg rtl8192E_power_on_flow
					[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS +
					 RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_radio_off_flow
					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
					 RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_card_disable_flow
					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
					 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
					 RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_card_enable_flow
					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
					 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
					 RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_suspend_flow
					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
					 RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
					 RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_resume_flow
					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
					 RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
					 RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_hwpdn_flow
					[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
					 RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
					 RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_enter_lps_flow
					[RTL8192E_TRANS_ACT_TO_LPS_STEPS +
					 RTL8192E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8192E_leave_lps_flow
					[RTL8192E_TRANS_LPS_TO_ACT_STEPS +
					 RTL8192E_TRANS_END_STEPS];

/* RTL8192EE Power Configuration CMDs for PCIe interface */
#define RTL8192E_NIC_PWR_ON_FLOW	rtl8192E_power_on_flow
#define RTL8192E_NIC_RF_OFF_FLOW	rtl8192E_radio_off_flow
#define RTL8192E_NIC_DISABLE_FLOW	rtl8192E_card_disable_flow
#define RTL8192E_NIC_ENABLE_FLOW	rtl8192E_card_enable_flow
#define RTL8192E_NIC_SUSPEND_FLOW	rtl8192E_suspend_flow
#define RTL8192E_NIC_RESUME_FLOW	rtl8192E_resume_flow
#define RTL8192E_NIC_PDN_FLOW		rtl8192E_hwpdn_flow
#define RTL8192E_NIC_LPS_ENTER_FLOW	rtl8192E_enter_lps_flow
#define RTL8192E_NIC_LPS_LEAVE_FLOW	rtl8192E_leave_lps_flow

#endif