summaryrefslogtreecommitdiffstats
path: root/kernel/drivers/net/ethernet/ezchip/nps_enet.h
blob: 6703674d679c964c00cac0ea12e084267df1ee47 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
/*
 * Copyright(c) 2015 EZchip Technologies.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in
 * the file called "COPYING".
 */

#ifndef _NPS_ENET_H
#define _NPS_ENET_H

/* default values */
#define NPS_ENET_NAPI_POLL_WEIGHT		0x2
#define NPS_ENET_MAX_FRAME_LENGTH		0x3FFF
#define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR	0x7
#define NPS_ENET_GE_MAC_CFG_0_RX_IFG		0x5
#define NPS_ENET_GE_MAC_CFG_0_TX_IFG		0xC
#define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN		0x7
#define NPS_ENET_GE_MAC_CFG_2_STAT_EN		0x3
#define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH		0x14
#define NPS_ENET_GE_MAC_CFG_3_MAX_LEN		0x3FFC
#define NPS_ENET_ENABLE				1
#define NPS_ENET_DISABLE			0

/* register definitions  */
#define NPS_ENET_REG_TX_CTL		0x800
#define NPS_ENET_REG_TX_BUF		0x808
#define NPS_ENET_REG_RX_CTL		0x810
#define NPS_ENET_REG_RX_BUF		0x818
#define NPS_ENET_REG_BUF_INT_ENABLE	0x8C0
#define NPS_ENET_REG_GE_MAC_CFG_0	0x1000
#define NPS_ENET_REG_GE_MAC_CFG_1	0x1004
#define NPS_ENET_REG_GE_MAC_CFG_2	0x1008
#define NPS_ENET_REG_GE_MAC_CFG_3	0x100C
#define NPS_ENET_REG_GE_RST		0x1400
#define NPS_ENET_REG_PHASE_FIFO_CTL	0x1404

/* Tx control register */
struct nps_enet_tx_ctl {
	union {
		/* ct: SW sets to indicate frame ready in Tx buffer for
		 *     transmission. HW resets to when transmission done
		 * et: Transmit error
		 * nt: Length in bytes of Tx frame loaded to Tx buffer
		 */
		struct {
			u32
			__reserved_1:16,
			ct:1,
			et:1,
			__reserved_2:3,
			nt:11;
		};

		u32 value;
	};
};

/* Rx control register */
struct nps_enet_rx_ctl {
	union {
		/* cr:  HW sets to indicate frame ready in Rx buffer.
		 *      SW resets to indicate host read received frame
		 *      and new frames can be written to Rx buffer
		 * er:  Rx error indication
		 * crc: Rx CRC error indication
		 * nr:  Length in bytes of Rx frame loaded by MAC to Rx buffer
		 */
		struct {
			u32
			__reserved_1:16,
			cr:1,
			er:1,
			crc:1,
			__reserved_2:2,
			nr:11;
		};

		u32 value;
	};
};

/* Interrupt enable for data buffer events register */
struct nps_enet_buf_int_enable {
	union {
		/* tx_done: Interrupt generation in the case when new frame
		 *          is ready in Rx buffer
		 * rx_rdy:  Interrupt generation in the case when current frame
		 *          was read from TX buffer
		 */
		struct {
			u32
			__reserved:30,
			tx_done:1,
			rx_rdy:1;
		};

		u32 value;
	};
};

/* Gbps Eth MAC Configuration 0 register */
struct nps_enet_ge_mac_cfg_0 {
	union {
		/* tx_pr_len:          Transmit preamble length in bytes
		 * tx_ifg_nib:         Tx idle pattern
		 * nib_mode:           Nibble (4-bit) Mode
		 * rx_pr_check_en:     Receive preamble Check Enable
		 * tx_ifg:             Transmit inter-Frame Gap
		 * rx_ifg:             Receive inter-Frame Gap
		 * tx_fc_retr:         Transmit Flow Control Retransmit Mode
		 * rx_length_check_en: Receive Length Check Enable
		 * rx_crc_ignore:      Results of the CRC check are ignored
		 * rx_crc_strip:       MAC strips the CRC from received frames
		 * rx_fc_en:           Receive Flow Control Enable
		 * tx_crc_en:          Transmit CRC Enabled
		 * tx_pad_en:          Transmit Padding Enable
		 * tx_cf_en:           Transmit Flow Control Enable
		 * tx_en:              Transmit Enable
		 * rx_en:              Receive Enable
		 */
		struct {
			u32
			tx_pr_len:4,
			tx_ifg_nib:4,
			nib_mode:1,
			rx_pr_check_en:1,
			tx_ifg:6,
			rx_ifg:4,
			tx_fc_retr:3,
			rx_length_check_en:1,
			rx_crc_ignore:1,
			rx_crc_strip:1,
			rx_fc_en:1,
			tx_crc_en:1,
			tx_pad_en:1,
			tx_fc_en:1,
			tx_en:1,
			rx_en:1;
		};

		u32 value;
	};
};

/* Gbps Eth MAC Configuration 1 register */
struct nps_enet_ge_mac_cfg_1 {
	union {
		/* octet_3: MAC address octet 3
		 * octet_2: MAC address octet 2
		 * octet_1: MAC address octet 1
		 * octet_0: MAC address octet 0
		 */
		struct {
			u32
			octet_3:8,
			octet_2:8,
			octet_1:8,
			octet_0:8;
		};

		u32 value;
	};
};

/* Gbps Eth MAC Configuration 2 register */
struct nps_enet_ge_mac_cfg_2 {
	union {
		/* transmit_flush_en: MAC flush enable
		 * stat_en:           RMON statistics interface enable
		 * disc_da:           Discard frames with DA different
		 *                    from MAC address
		 * disc_bc:           Discard broadcast frames
		 * disc_mc:           Discard multicast frames
		 * octet_5:           MAC address octet 5
		 * octet_4:           MAC address octet 4
		 */
		struct {
			u32
			transmit_flush_en:1,
			__reserved_1:5,
			stat_en:2,
			__reserved_2:1,
			disc_da:1,
			disc_bc:1,
			disc_mc:1,
			__reserved_3:4,
			octet_5:8,
			octet_4:8;
		};

		u32 value;
	};
};

/* Gbps Eth MAC Configuration 3 register */
struct nps_enet_ge_mac_cfg_3 {
	union {
		/* ext_oob_cbfc_sel:  Selects one of the 4 profiles for
		 *                    extended OOB in-flow-control indication
		 * max_len:           Maximum receive frame length in bytes
		 * tx_cbfc_en:        Enable transmission of class-based
		 *                    flow control packets
		 * rx_ifg_th:         Threshold for IFG status reporting via OOB
		 * cf_timeout:        Configurable time to decrement FC counters
		 * cf_drop:           Drop control frames
		 * redirect_cbfc_sel: Selects one of CBFC redirect profiles
		 * rx_cbfc_redir_en:  Enable Rx class-based flow
		 *                    control redirect
		 * rx_cbfc_en:        Enable Rx class-based flow control
		 * tm_hd_mode:        TM header mode
		 */
		struct {
			u32
			ext_oob_cbfc_sel:2,
			max_len:14,
			tx_cbfc_en:1,
			rx_ifg_th:5,
			cf_timeout:4,
			cf_drop:1,
			redirect_cbfc_sel:2,
			rx_cbfc_redir_en:1,
			rx_cbfc_en:1,
			tm_hd_mode:1;
		};

		u32 value;
	};
};

/* GE MAC, PCS reset control register */
struct nps_enet_ge_rst {
	union {
		/* gmac_0: GE MAC reset
		 * spcs_0: SGMII PCS reset
		 */
		struct {
			u32
			__reserved_1:23,
			gmac_0:1,
			__reserved_2:7,
			spcs_0:1;
		};

		u32 value;
	};
};

/* Tx phase sync FIFO control register */
struct nps_enet_phase_fifo_ctl {
	union {
		/* init: initialize serdes TX phase sync FIFO pointers
		 * rst:  reset serdes TX phase sync FIFO
		 */
		struct {
			u32
			__reserved:30,
			init:1,
			rst:1;
		};

		u32 value;
	};
};

/**
 * struct nps_enet_priv - Storage of ENET's private information.
 * @regs_base:      Base address of ENET memory-mapped control registers.
 * @irq:            For RX/TX IRQ number.
 * @tx_packet_sent: SW indication if frame is being sent.
 * @tx_skb:         socket buffer of sent frame.
 * @napi:           Structure for NAPI.
 */
struct nps_enet_priv {
	void __iomem *regs_base;
	s32 irq;
	bool tx_packet_sent;
	struct sk_buff *tx_skb;
	struct napi_struct napi;
	struct nps_enet_ge_mac_cfg_2 ge_mac_cfg_2;
	struct nps_enet_ge_mac_cfg_3 ge_mac_cfg_3;
};

/**
 * nps_reg_set - Sets ENET register with provided value.
 * @priv:       Pointer to EZchip ENET private data structure.
 * @reg:        Register offset from base address.
 * @value:      Value to set in register.
 */
static inline void nps_enet_reg_set(struct nps_enet_priv *priv,
				    s32 reg, s32 value)
{
	iowrite32be(value, priv->regs_base + reg);
}

/**
 * nps_reg_get - Gets value of specified ENET register.
 * @priv:       Pointer to EZchip ENET private data structure.
 * @reg:        Register offset from base address.
 *
 * returns:     Value of requested register.
 */
static inline u32 nps_enet_reg_get(struct nps_enet_priv *priv, s32 reg)
{
	return ioread32be(priv->regs_base + reg);
}

#endif /* _NPS_ENET_H */