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path: root/kernel/drivers/hid/hid-picolcd_fb.c
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/***************************************************************************
 *   Copyright (C) 2010-2012 by Bruno Prémont <bonbons@linux-vserver.org>  *
 *                                                                         *
 *   Based on Logitech G13 driver (v0.4)                                   *
 *     Copyright (C) 2009 by Rick L. Vinyard, Jr. <rvinyard@cs.nmsu.edu>   *
 *                                                                         *
 *   This program is free software: you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation, version 2 of the License.               *
 *                                                                         *
 *   This driver is distributed in the hope that it will be useful, but    *
 *   WITHOUT ANY WARRANTY; without even the implied warranty of            *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU      *
 *   General Public License for more details.                              *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this software. If not see <http://www.gnu.org/licenses/>.  *
 ***************************************************************************/

#include <linux/hid.h>
#include <linux/vmalloc.h>

#include <linux/fb.h>
#include <linux/module.h>

#include "hid-picolcd.h"

/* Framebuffer
 *
 * The PicoLCD use a Topway LCD module of 256x64 pixel
 * This display area is tiled over 4 controllers with 8 tiles
 * each. Each tile has 8x64 pixel, each data byte representing
 * a 1-bit wide vertical line of the tile.
 *
 * The display can be updated at a tile granularity.
 *
 *       Chip 1           Chip 2           Chip 3           Chip 4
 * +----------------+----------------+----------------+----------------+
 * |     Tile 1     |     Tile 1     |     Tile 1     |     Tile 1     |
 * +----------------+----------------+----------------+----------------+
 * |     Tile 2     |     Tile 2     |     Tile 2     |     Tile 2     |
 * +----------------+----------------+----------------+----------------+
 *                                  ...
 * +----------------+----------------+----------------+----------------+
 * |     Tile 8     |     Tile 8     |     Tile 8     |     Tile 8     |
 * +----------------+----------------+----------------+----------------+
 */
#define PICOLCDFB_NAME "picolcdfb"
#define PICOLCDFB_WIDTH (256)
#define PICOLCDFB_HEIGHT (64)
#define PICOLCDFB_SIZE (PICOLCDFB_WIDTH * PICOLCDFB_HEIGHT / 8)

#define PICOLCDFB_UPDATE_RATE_LIMIT   10
#define PICOLCDFB_UPDATE_RATE_DEFAULT  2

/* Framebuffer visual structures */
static const struct fb_fix_screeninfo picolcdfb_fix = {
	.id          = PICOLCDFB_NAME,
	.type        = FB_TYPE_PACKED_PIXELS,
	.visual      = FB_VISUAL_MONO01,
	.xpanstep    = 0,
	.ypanstep    = 0,
	.ywrapstep   = 0,
	.line_length = PICOLCDFB_WIDTH / 8,
	.accel       = FB_ACCEL_NONE,
};

static const struct fb_var_screeninfo picolcdfb_var = {
	.xres           = PICOLCDFB_WIDTH,
	.yres           = PICOLCDFB_HEIGHT,
	.xres_virtual   = PICOLCDFB_WIDTH,
	.yres_virtual   = PICOLCDFB_HEIGHT,
	.width          = 103,
	.height         = 26,
	.bits_per_pixel = 1,
	.grayscale      = 1,
	.red            = {
		.offset = 0,
		.length = 1,
		.msb_right = 0,
	},
	.green          = {
		.offset = 0,
		.length = 1,
		.msb_right = 0,
	},
	.blue           = {
		.offset = 0,
		.length = 1,
		.msb_right = 0,
	},
	.transp         = {
		.offset = 0,
		.length = 0,
		.msb_right = 0,
	},
};

/* Send a given tile to PicoLCD */
static int picolcd_fb_send_tile(struct picolcd_data *data, u8 *vbitmap,
		int chip, int tile)
{
	struct hid_report *report1, *report2;
	unsigned long flags;
	u8 *tdata;
	int i;

	report1 = picolcd_out_report(REPORT_LCD_CMD_DATA, data->hdev);
	if (!report1 || report1->maxfield != 1)
		return -ENODEV;
	report2 = picolcd_out_report(REPORT_LCD_DATA, data->hdev);
	if (!report2 || report2->maxfield != 1)
		return -ENODEV;

	spin_lock_irqsave(&data->lock, flags);
	if ((data->status & PICOLCD_FAILED)) {
		spin_unlock_irqrestore(&data->lock, flags);
		return -ENODEV;
	}
	hid_set_field(report1->field[0],  0, chip << 2);
	hid_set_field(report1->field[0],  1, 0x02);
	hid_set_field(report1->field[0],  2, 0x00);
	hid_set_field(report1->field[0],  3, 0x00);
	hid_set_field(report1->field[0],  4, 0xb8 | tile);
	hid_set_field(report1->field[0],  5, 0x00);
	hid_set_field(report1->field[0],  6, 0x00);
	hid_set_field(report1->field[0],  7, 0x40);
	hid_set_field(report1->field[0],  8, 0x00);
	hid_set_field(report1->field[0],  9, 0x00);
	hid_set_field(report1->field[0], 10,   32);

	hid_set_field(report2->field[0],  0, (chip << 2) | 0x01);
	hid_set_field(report2->field[0],  1, 0x00);
	hid_set_field(report2->field[0],  2, 0x00);
	hid_set_field(report2->field[0],  3,   32);

	tdata = vbitmap + (tile * 4 + chip) * 64;
	for (i = 0; i < 64; i++)
		if (i < 32)
			hid_set_field(report1->field[0], 11 + i, tdata[i]);
		else
			hid_set_field(report2->field[0], 4 + i - 32, tdata[i]);

	hid_hw_request(data->hdev, report1, HID_REQ_SET_REPORT);
	hid_hw_request(data->hdev, report2, HID_REQ_SET_REPORT);
	spin_unlock_irqrestore(&data->lock, flags);
	return 0;
}

/* Translate a single tile*/
static int picolcd_fb_update_tile(u8 *vbitmap, const u8 *bitmap, int bpp,
		int chip, int tile)
{
	int i, b, changed = 0;
	u8 tdata[64];
	u8 *vdata = vbitmap + (tile * 4 + chip) * 64;

	if (bpp == 1) {
		for (b = 7; b >= 0; b--) {
			const u8 *bdata = bitmap + tile * 256 + chip * 8 + b * 32;
			for (i = 0; i < 64; i++) {
				tdata[i] <<= 1;
				tdata[i] |= (bdata[i/8] >> (i % 8)) & 0x01;
			}
		}
	} else if (bpp == 8) {
		for (b = 7; b >= 0; b--) {
			const u8 *bdata = bitmap + (tile * 256 + chip * 8 + b * 32) * 8;
			for (i = 0; i < 64; i++) {
				tdata[i] <<= 1;
				tdata[i] |= (bdata[i] & 0x80) ? 0x01 : 0x00;
			}
		}
	} else {
		/* Oops, we should never get here! */
		WARN_ON(1);
		return 0;
	}

	for (i = 0; i < 64; i++)
		if (tdata[i] != vdata[i]) {
			changed = 1;
			vdata[i] = tdata[i];
		}
	return changed;
}

void picolcd_fb_refresh(struct picolcd_data *data)
{
	if (data->fb_info)
		schedule_delayed_work(&data->fb_info->deferred_work, 0);
}

/* Reconfigure LCD display */
int picolcd_fb_reset(struct picolcd_data *data, int clear)
{
	struct hid_report *report = picolcd_out_report(REPORT_LCD_CMD, data->hdev);
	struct picolcd_fb_data *fbdata = data->fb_info->par;
	int i, j;
	unsigned long flags;
	static const u8 mapcmd[8] = { 0x00, 0x02, 0x00, 0x64, 0x3f, 0x00, 0x64, 0xc0 };

	if (!report || report->maxfield != 1)
		return -ENODEV;

	spin_lock_irqsave(&data->lock, flags);
	for (i = 0; i < 4; i++) {
		for (j = 0; j < report->field[0]->maxusage; j++)
			if (j == 0)
				hid_set_field(report->field[0], j, i << 2);
			else if (j < sizeof(mapcmd))
				hid_set_field(report->field[0], j, mapcmd[j]);
			else
				hid_set_field(report->field[0], j, 0);
		hid_hw_request(data->hdev, report, HID_REQ_SET_REPORT);
	}
	spin_unlock_irqrestore(&data->lock, flags);

	if (clear) {
		memset(fbdata->vbitmap, 0, PICOLCDFB_SIZE);
		memset(fbdata->bitmap, 0, PICOLCDFB_SIZE*fbdata->bpp);
	}
	fbdata->force = 1;

	/* schedule first output of framebuffer */
	if (fbdata->ready)
		schedule_delayed_work(&data->fb_info->deferred_work, 0);
	else
		fbdata->ready = 1;

	return 0;
}

/* Update fb_vbitmap from the screen_base and send changed tiles to device */
static void picolcd_fb_update(struct fb_info *info)
{
	int chip, tile, n;
	unsigned long flags;
	struct picolcd_fb_data *fbdata = info->par;
	struct picolcd_data *data;

	mutex_lock(&info->lock);

	spin_lock_irqsave(&fbdata->lock, flags);
	if (!fbdata->ready && fbdata->picolcd)
		picolcd_fb_reset(fbdata->picolcd, 0);
	spin_unlock_irqrestore(&fbdata->lock, flags);

	/*
	 * Translate the framebuffer into the format needed by the PicoLCD.
	 * See display layout above.
	 * Do this one tile after the other and push those tiles that changed.
	 *
	 * Wait for our IO to complete as otherwise we might flood the queue!
	 */
	n = 0;
	for (chip = 0; chip < 4; chip++)
		for (tile = 0; tile < 8; tile++) {
			if (!fbdata->force && !picolcd_fb_update_tile(
					fbdata->vbitmap, fbdata->bitmap,
					fbdata->bpp, chip, tile))
				continue;
			n += 2;
			if (n >= HID_OUTPUT_FIFO_SIZE / 2) {
				spin_lock_irqsave(&fbdata->lock, flags);
				data = fbdata->picolcd;
				spin_unlock_irqrestore(&fbdata->lock, flags);
				mutex_unlock(&info->lock);
				if (!data)
					return;
				hid_hw_wait(data->hdev);
				mutex_lock(&info->lock);
				n = 0;
			}
			spin_lock_irqsave(&fbdata->lock, flags);
			data = fbdata->picolcd;
			spin_unlock_irqrestore(&fbdata->lock, flags);
			if (!data || picolcd_fb_send_tile(data,
					fbdata->vbitmap, chip, tile))
				goto out;
		}
	fbdata->force = false;
	if (n) {
		spin_lock_irqsave(&fbdata->lock, flags);
		data = fbdata->picolcd;
		spin_unlock_irqrestore(&fbdata->lock, flags);
		mutex_unlock(&info->lock);
		if (data)
			hid_hw_wait(data->hdev);
		return;
	}
out:
	mutex_unlock(&info->lock);
}

/* Stub to call the system default and update the image on the picoLCD */
static void picolcd_fb_fillrect(struct fb_info *info,
		const struct fb_fillrect *rect)
{
	if (!info->par)
		return;
	sys_fillrect(info, rect);

	schedule_delayed_work(&info->deferred_work, 0);
}

/* Stub to call the system default and update the image on the picoLCD */
static void picolcd_fb_copyarea(struct fb_info *info,
		const struct fb_copyarea *area)
{
	if (!info->par)
		return;
	sys_copyarea(info, area);

	schedule_delayed_work(&info->deferred_work, 0);
}

/* Stub to call the system default and update the image on the picoLCD */
static void picolcd_fb_imageblit(struct fb_info *info, const struct fb_image *image)
{
	if (!info->par)
		return;
	sys_imageblit(info, image);

	schedule_delayed_work(&info->deferred_work, 0);
}

/*
 * this is the slow path from userspace. they can seek and write to
 * the fb. it's inefficient to do anything less than a full screen draw
 */
static ssize_t picolcd_fb_write(struct fb_info *info, const char __user *buf,
		size_t count, loff_t *ppos)
{
	ssize_t ret;
	if (!info->par)
		return -ENODEV;
	ret = fb_sys_write(info, buf, count, ppos);
	if (ret >= 0)
		schedule_delayed_work(&info->deferred_work, 0);
	return ret;
}

static int picolcd_fb_blank(int blank, struct fb_info *info)
{
	/* We let fb notification do this for us via lcd/backlight device */
	return 0;
}

static void picolcd_fb_destroy(struct fb_info *info)
{
	struct picolcd_fb_data *fbdata = info->par;

	/* make sure no work is deferred */
	fb_deferred_io_cleanup(info);

	/* No thridparty should ever unregister our framebuffer! */
	WARN_ON(fbdata->picolcd != NULL);

	vfree((u8 *)info->fix.smem_start);
	framebuffer_release(info);
}

static int picolcd_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
	__u32 bpp      = var->bits_per_pixel;
	__u32 activate = var->activate;

	/* only allow 1/8 bit depth (8-bit is grayscale) */
	*var = picolcdfb_var;
	var->activate = activate;
	if (bpp >= 8) {
		var->bits_per_pixel = 8;
		var->red.length     = 8;
		var->green.length   = 8;
		var->blue.length    = 8;
	} else {
		var->bits_per_pixel = 1;
		var->red.length     = 1;
		var->green.length   = 1;
		var->blue.length    = 1;
	}
	return 0;
}

static int picolcd_set_par(struct fb_info *info)
{
	struct picolcd_fb_data *fbdata = info->par;
	u8 *tmp_fb, *o_fb;
	if (info->var.bits_per_pixel == fbdata->bpp)
		return 0;
	/* switch between 1/8 bit depths */
	if (info->var.bits_per_pixel != 1 && info->var.bits_per_pixel != 8)
		return -EINVAL;

	o_fb   = fbdata->bitmap;
	tmp_fb = kmalloc(PICOLCDFB_SIZE*info->var.bits_per_pixel, GFP_KERNEL);
	if (!tmp_fb)
		return -ENOMEM;

	/* translate FB content to new bits-per-pixel */
	if (info->var.bits_per_pixel == 1) {
		int i, b;
		for (i = 0; i < PICOLCDFB_SIZE; i++) {
			u8 p = 0;
			for (b = 0; b < 8; b++) {
				p <<= 1;
				p |= o_fb[i*8+b] ? 0x01 : 0x00;
			}
			tmp_fb[i] = p;
		}
		memcpy(o_fb, tmp_fb, PICOLCDFB_SIZE);
		info->fix.visual = FB_VISUAL_MONO01;
		info->fix.line_length = PICOLCDFB_WIDTH / 8;
	} else {
		int i;
		memcpy(tmp_fb, o_fb, PICOLCDFB_SIZE);
		for (i = 0; i < PICOLCDFB_SIZE * 8; i++)
			o_fb[i] = tmp_fb[i/8] & (0x01 << (7 - i % 8)) ? 0xff : 0x00;
		info->fix.visual = FB_VISUAL_DIRECTCOLOR;
		info->fix.line_length = PICOLCDFB_WIDTH;
	}

	kfree(tmp_fb);
	fbdata->bpp = info->var.bits_per_pixel;
	return 0;
}

/* Note this can't be const because of struct fb_info definition */
static struct fb_ops picolcdfb_ops = {
	.owner        = THIS_MODULE,
	.fb_destroy   = picolcd_fb_destroy,
	.fb_read      = fb_sys_read,
	.fb_write     = picolcd_fb_write,
	.fb_blank     = picolcd_fb_blank,
	.fb_fillrect  = picolcd_fb_fillrect,
	.fb_copyarea  = picolcd_fb_copyarea,
	.fb_imageblit = picolcd_fb_imageblit,
	.fb_check_var = picolcd_fb_check_var,
	.fb_set_par   = picolcd_set_par,
};


/* Callback from deferred IO workqueue */
static void picolcd_fb_deferred_io(struct fb_info *info, struct list_head *pagelist)
{
	picolcd_fb_update(info);
}

static const struct fb_deferred_io picolcd_fb_defio = {
	.delay = HZ / PICOLCDFB_UPDATE_RATE_DEFAULT,
	.deferred_io = picolcd_fb_deferred_io,
};


/*
 * The "fb_update_rate" sysfs attribute
 */
static ssize_t picolcd_fb_update_rate_show(struct device *dev,
		struct device_attribute *attr, char *buf)
{
	struct picolcd_data *data = dev_get_drvdata(dev);
	struct picolcd_fb_data *fbdata = data->fb_info->par;
	unsigned i, fb_update_rate = fbdata->update_rate;
	size_t ret = 0;

	for (i = 1; i <= PICOLCDFB_UPDATE_RATE_LIMIT; i++)
		if (ret >= PAGE_SIZE)
			break;
		else if (i == fb_update_rate)
			ret += snprintf(buf+ret, PAGE_SIZE-ret, "[%u] ", i);
		else
			ret += snprintf(buf+ret, PAGE_SIZE-ret, "%u ", i);
	if (ret > 0)
		buf[min(ret, (size_t)PAGE_SIZE)-1] = '\n';
	return ret;
}

static ssize_t picolcd_fb_update_rate_store(struct device *dev,
		struct device_attribute *attr, const char *buf, size_t count)
{
	struct picolcd_data *data = dev_get_drvdata(dev);
	struct picolcd_fb_data *fbdata = data->fb_info->par;
	int i;
	unsigned u;

	if (count < 1 || count > 10)
		return -EINVAL;

	i = sscanf(buf, "%u", &u);
	if (i != 1)
		return -EINVAL;

	if (u > PICOLCDFB_UPDATE_RATE_LIMIT)
		return -ERANGE;
	else if (u == 0)
		u = PICOLCDFB_UPDATE_RATE_DEFAULT;

	fbdata->update_rate = u;
	data->fb_info->fbdefio->delay = HZ / fbdata->update_rate;
	return count;
}

static DEVICE_ATTR(fb_update_rate, 0664, picolcd_fb_update_rate_show,
		picolcd_fb_update_rate_store);

/* initialize Framebuffer device */
int picolcd_init_framebuffer(struct picolcd_data *data)
{
	struct device *dev = &data->hdev->dev;
	struct fb_info *info = NULL;
	struct picolcd_fb_data *fbdata = NULL;
	int i, error = -ENOMEM;
	u32 *palette;

	/* The extra memory is:
	 * - 256*u32 for pseudo_palette
	 * - struct fb_deferred_io
	 */
	info = framebuffer_alloc(256 * sizeof(u32) +
			sizeof(struct fb_deferred_io) +
			sizeof(struct picolcd_fb_data) +
			PICOLCDFB_SIZE, dev);
	if (info == NULL) {
		dev_err(dev, "failed to allocate a framebuffer\n");
		goto err_nomem;
	}

	info->fbdefio = info->par;
	*info->fbdefio = picolcd_fb_defio;
	info->par += sizeof(struct fb_deferred_io);
	palette = info->par;
	info->par += 256 * sizeof(u32);
	for (i = 0; i < 256; i++)
		palette[i] = i > 0 && i < 16 ? 0xff : 0;
	info->pseudo_palette = palette;
	info->fbops = &picolcdfb_ops;
	info->var = picolcdfb_var;
	info->fix = picolcdfb_fix;
	info->fix.smem_len   = PICOLCDFB_SIZE*8;
	info->flags = FBINFO_FLAG_DEFAULT;

	fbdata = info->par;
	spin_lock_init(&fbdata->lock);
	fbdata->picolcd = data;
	fbdata->update_rate = PICOLCDFB_UPDATE_RATE_DEFAULT;
	fbdata->bpp     = picolcdfb_var.bits_per_pixel;
	fbdata->force   = 1;
	fbdata->vbitmap = info->par + sizeof(struct picolcd_fb_data);
	fbdata->bitmap  = vmalloc(PICOLCDFB_SIZE*8);
	if (fbdata->bitmap == NULL) {
		dev_err(dev, "can't get a free page for framebuffer\n");
		goto err_nomem;
	}
	info->screen_base = (char __force __iomem *)fbdata->bitmap;
	info->fix.smem_start = (unsigned long)fbdata->bitmap;
	memset(fbdata->vbitmap, 0xff, PICOLCDFB_SIZE);
	data->fb_info = info;

	error = picolcd_fb_reset(data, 1);
	if (error) {
		dev_err(dev, "failed to configure display\n");
		goto err_cleanup;
	}

	error = device_create_file(dev, &dev_attr_fb_update_rate);
	if (error) {
		dev_err(dev, "failed to create sysfs attributes\n");
		goto err_cleanup;
	}

	fb_deferred_io_init(info);
	error = register_framebuffer(info);
	if (error) {
		dev_err(dev, "failed to register framebuffer\n");
		goto err_sysfs;
	}
	return 0;

err_sysfs:
	device_remove_file(dev, &dev_attr_fb_update_rate);
	fb_deferred_io_cleanup(info);
err_cleanup:
	data->fb_info    = NULL;

err_nomem:
	if (fbdata)
		vfree(fbdata->bitmap);
	framebuffer_release(info);
	return error;
}

void picolcd_exit_framebuffer(struct picolcd_data *data)
{
	struct fb_info *info = data->fb_info;
	struct picolcd_fb_data *fbdata;
	unsigned long flags;

	if (!info)
		return;

	device_remove_file(&data->hdev->dev, &dev_attr_fb_update_rate);
	fbdata = info->par;

	/* disconnect framebuffer from HID dev */
	spin_lock_irqsave(&fbdata->lock, flags);
	fbdata->picolcd = NULL;
	spin_unlock_irqrestore(&fbdata->lock, flags);

	/* make sure there is no running update - thus that fbdata->picolcd
	 * once obtained under lock is guaranteed not to get free() under
	 * the feet of the deferred work */
	flush_delayed_work(&info->deferred_work);

	data->fb_info = NULL;
	unregister_framebuffer(info);
}
ss="p">, 0); mtsdram(dcr_host, SDRAM_BEARH, 0); } /** * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE) * @mci: A pointer to the EDAC memory controller instance * associated with the correctable error being handled and reported. * @status: A pointer to the ECC status structure associated with * the correctable error being handled and reported. * * This routine handles an ibm,sdram-4xx-ddr2 controller ECC * correctable error. Per the aforementioned discussion, there's not * enough status available to use the full EDAC correctable error * interface, so we just pass driver-unique message to the "no info" * interface. */ static void ppc4xx_edac_handle_ce(struct mem_ctl_info *mci, const struct ppc4xx_ecc_status *status) { int row; char message[PPC4XX_EDAC_MESSAGE_SIZE]; ppc4xx_edac_generate_message(mci, status, message, sizeof(message)); for (row = 0; row < mci->nr_csrows; row++) if (ppc4xx_edac_check_bank_error(status, row)) edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, row, 0, -1, message, ""); } /** * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE) * @mci: A pointer to the EDAC memory controller instance * associated with the uncorrectable error being handled and * reported. * @status: A pointer to the ECC status structure associated with * the uncorrectable error being handled and reported. * * This routine handles an ibm,sdram-4xx-ddr2 controller ECC * uncorrectable error. */ static void ppc4xx_edac_handle_ue(struct mem_ctl_info *mci, const struct ppc4xx_ecc_status *status) { const u64 bear = ((u64)status->bearh << 32 | status->bearl); const unsigned long page = bear >> PAGE_SHIFT; const unsigned long offset = bear & ~PAGE_MASK; int row; char message[PPC4XX_EDAC_MESSAGE_SIZE]; ppc4xx_edac_generate_message(mci, status, message, sizeof(message)); for (row = 0; row < mci->nr_csrows; row++) if (ppc4xx_edac_check_bank_error(status, row)) edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, page, offset, 0, row, 0, -1, message, ""); } /** * ppc4xx_edac_check - check controller for ECC errors * @mci: A pointer to the EDAC memory controller instance * associated with the ibm,sdram-4xx-ddr2 controller being * checked. * * This routine is used to check and post ECC errors and is called by * both the EDAC polling thread and this driver's CE and UE interrupt * handler. */ static void ppc4xx_edac_check(struct mem_ctl_info *mci) { #ifdef DEBUG static unsigned int count; #endif struct ppc4xx_ecc_status status; ppc4xx_ecc_get_status(mci, &status); #ifdef DEBUG if (count++ % 30 == 0) ppc4xx_ecc_dump_status(mci, &status); #endif if (status.ecces & SDRAM_ECCES_UE) ppc4xx_edac_handle_ue(mci, &status); if (status.ecces & SDRAM_ECCES_CE) ppc4xx_edac_handle_ce(mci, &status); ppc4xx_ecc_clear_status(mci, &status); } /** * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine * @irq: The virtual interrupt number being serviced. * @dev_id: A pointer to the EDAC memory controller instance * associated with the interrupt being handled. * * This routine implements the interrupt handler for both correctable * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2 * controller. It simply calls through to the same routine used during * polling to check, report and clear the ECC status. * * Unconditionally returns IRQ_HANDLED. */ static irqreturn_t ppc4xx_edac_isr(int irq, void *dev_id) { struct mem_ctl_info *mci = dev_id; ppc4xx_edac_check(mci); return IRQ_HANDLED; } /** * ppc4xx_edac_get_dtype - return the controller memory width * @mcopt1: The 32-bit Memory Controller Option 1 register value * currently set for the controller, from which the width * is derived. * * This routine returns the EDAC device type width appropriate for the * current controller configuration. * * TODO: This needs to be conditioned dynamically through feature * flags or some such when other controller variants are supported as * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the * 16- and 64-bit field definition/value/enumeration (b1) overloaded * among them. * * Returns a device type width enumeration. */ static enum dev_type ppc4xx_edac_get_dtype(u32 mcopt1) { switch (mcopt1 & SDRAM_MCOPT1_WDTH_MASK) { case SDRAM_MCOPT1_WDTH_16: return DEV_X2; case SDRAM_MCOPT1_WDTH_32: return DEV_X4; default: return DEV_UNKNOWN; } } /** * ppc4xx_edac_get_mtype - return controller memory type * @mcopt1: The 32-bit Memory Controller Option 1 register value * currently set for the controller, from which the memory type * is derived. * * This routine returns the EDAC memory type appropriate for the * current controller configuration. * * Returns a memory type enumeration. */ static enum mem_type ppc4xx_edac_get_mtype(u32 mcopt1) { bool rden = ((mcopt1 & SDRAM_MCOPT1_RDEN_MASK) == SDRAM_MCOPT1_RDEN); switch (mcopt1 & SDRAM_MCOPT1_DDR_TYPE_MASK) { case SDRAM_MCOPT1_DDR2_TYPE: return rden ? MEM_RDDR2 : MEM_DDR2; case SDRAM_MCOPT1_DDR1_TYPE: return rden ? MEM_RDDR : MEM_DDR; default: return MEM_UNKNOWN; } } /** * ppc4xx_edac_init_csrows - initialize driver instance rows * @mci: A pointer to the EDAC memory controller instance * associated with the ibm,sdram-4xx-ddr2 controller for which * the csrows (i.e. banks/ranks) are being initialized. * @mcopt1: The 32-bit Memory Controller Option 1 register value * currently set for the controller, from which bank width * and memory typ information is derived. * * This routine initializes the virtual "chip select rows" associated * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2 * controller bank/rank is mapped to a row. * * Returns 0 if OK; otherwise, -EINVAL if the memory bank size * configuration cannot be determined. */ static int ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1) { const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; int status = 0; enum mem_type mtype; enum dev_type dtype; enum edac_type edac_mode; int row, j; u32 mbxcf, size, nr_pages; /* Establish the memory type and width */ mtype = ppc4xx_edac_get_mtype(mcopt1); dtype = ppc4xx_edac_get_dtype(mcopt1); /* Establish EDAC mode */ if (mci->edac_cap & EDAC_FLAG_SECDED) edac_mode = EDAC_SECDED; else if (mci->edac_cap & EDAC_FLAG_EC) edac_mode = EDAC_EC; else edac_mode = EDAC_NONE; /* * Initialize each chip select row structure which correspond * 1:1 with a controller bank/rank. */ for (row = 0; row < mci->nr_csrows; row++) { struct csrow_info *csi = mci->csrows[row]; /* * Get the configuration settings for this * row/bank/rank and skip disabled banks. */ mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row)); if ((mbxcf & SDRAM_MBCF_BE_MASK) != SDRAM_MBCF_BE_ENABLE) continue; /* Map the bank configuration size setting to pages. */ size = mbxcf & SDRAM_MBCF_SZ_MASK; switch (size) { case SDRAM_MBCF_SZ_4MB: case SDRAM_MBCF_SZ_8MB: case SDRAM_MBCF_SZ_16MB: case SDRAM_MBCF_SZ_32MB: case SDRAM_MBCF_SZ_64MB: case SDRAM_MBCF_SZ_128MB: case SDRAM_MBCF_SZ_256MB: case SDRAM_MBCF_SZ_512MB: case SDRAM_MBCF_SZ_1GB: case SDRAM_MBCF_SZ_2GB: case SDRAM_MBCF_SZ_4GB: case SDRAM_MBCF_SZ_8GB: nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size); break; default: ppc4xx_edac_mc_printk(KERN_ERR, mci, "Unrecognized memory bank %d " "size 0x%08x\n", row, SDRAM_MBCF_SZ_DECODE(size)); status = -EINVAL; goto done; } /* * It's unclear exactly what grain should be set to * here. The SDRAM_ECCES register allows resolution of * an error down to a nibble which would potentially * argue for a grain of '1' byte, even though we only * know the associated address for uncorrectable * errors. This value is not used at present for * anything other than error reporting so getting it * wrong should be of little consequence. Other * possible values would be the PLB width (16), the * page size (PAGE_SIZE) or the memory width (2 or 4). */ for (j = 0; j < csi->nr_channels; j++) { struct dimm_info *dimm = csi->channels[j]->dimm; dimm->nr_pages = nr_pages / csi->nr_channels; dimm->grain = 1; dimm->mtype = mtype; dimm->dtype = dtype; dimm->edac_mode = edac_mode; } } done: return status; } /** * ppc4xx_edac_mc_init - initialize driver instance * @mci: A pointer to the EDAC memory controller instance being * initialized. * @op: A pointer to the OpenFirmware device tree node associated * with the controller this EDAC instance is bound to. * @dcr_host: A pointer to the DCR data containing the DCR mapping * for this controller instance. * @mcopt1: The 32-bit Memory Controller Option 1 register value * currently set for the controller, from which ECC capabilities * and scrub mode are derived. * * This routine performs initialization of the EDAC memory controller * instance and related driver-private data associated with the * ibm,sdram-4xx-ddr2 memory controller the instance is bound to. * * Returns 0 if OK; otherwise, < 0 on error. */ static int ppc4xx_edac_mc_init(struct mem_ctl_info *mci, struct platform_device *op, const dcr_host_t *dcr_host, u32 mcopt1) { int status = 0; const u32 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK); struct ppc4xx_edac_pdata *pdata = NULL; const struct device_node *np = op->dev.of_node; if (of_match_device(ppc4xx_edac_match, &op->dev) == NULL) return -EINVAL; /* Initial driver pointers and private data */ mci->pdev = &op->dev; dev_set_drvdata(mci->pdev, mci); pdata = mci->pvt_info; pdata->dcr_host = *dcr_host; pdata->irqs.sec = NO_IRQ; pdata->irqs.ded = NO_IRQ; /* Initialize controller capabilities and configuration */ mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR | MEM_FLAG_DDR2 | MEM_FLAG_RDDR2); mci->edac_ctl_cap = (EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED); mci->scrub_cap = SCRUB_NONE; mci->scrub_mode = SCRUB_NONE; /* * Update the actual capabilites based on the MCOPT1[MCHK] * settings. Scrubbing is only useful if reporting is enabled. */ switch (memcheck) { case SDRAM_MCOPT1_MCHK_CHK: mci->edac_cap = EDAC_FLAG_EC; break; case SDRAM_MCOPT1_MCHK_CHK_REP: mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED); mci->scrub_mode = SCRUB_SW_SRC; break; default: mci->edac_cap = EDAC_FLAG_NONE; break; } /* Initialize strings */ mci->mod_name = PPC4XX_EDAC_MODULE_NAME; mci->mod_ver = PPC4XX_EDAC_MODULE_REVISION; mci->ctl_name = ppc4xx_edac_match->compatible, mci->dev_name = np->full_name; /* Initialize callbacks */ mci->edac_check = ppc4xx_edac_check; mci->ctl_page_to_phys = NULL; /* Initialize chip select rows */ status = ppc4xx_edac_init_csrows(mci, mcopt1); if (status) ppc4xx_edac_mc_printk(KERN_ERR, mci, "Failed to initialize rows!\n"); return status; } /** * ppc4xx_edac_register_irq - setup and register controller interrupts * @op: A pointer to the OpenFirmware device tree node associated * with the controller this EDAC instance is bound to. * @mci: A pointer to the EDAC memory controller instance * associated with the ibm,sdram-4xx-ddr2 controller for which * interrupts are being registered. * * This routine parses the correctable (CE) and uncorrectable error (UE) * interrupts from the device tree node and maps and assigns them to * the associated EDAC memory controller instance. * * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be * mapped and assigned. */ static int ppc4xx_edac_register_irq(struct platform_device *op, struct mem_ctl_info *mci) { int status = 0; int ded_irq, sec_irq; struct ppc4xx_edac_pdata *pdata = mci->pvt_info; struct device_node *np = op->dev.of_node; ded_irq = irq_of_parse_and_map(np, INTMAP_ECCDED_INDEX); sec_irq = irq_of_parse_and_map(np, INTMAP_ECCSEC_INDEX); if (ded_irq == NO_IRQ || sec_irq == NO_IRQ) { ppc4xx_edac_mc_printk(KERN_ERR, mci, "Unable to map interrupts.\n"); status = -ENODEV; goto fail; } status = request_irq(ded_irq, ppc4xx_edac_isr, 0, "[EDAC] MC ECCDED", mci); if (status < 0) { ppc4xx_edac_mc_printk(KERN_ERR, mci, "Unable to request irq %d for ECC DED", ded_irq); status = -ENODEV; goto fail1; } status = request_irq(sec_irq, ppc4xx_edac_isr, 0, "[EDAC] MC ECCSEC", mci); if (status < 0) { ppc4xx_edac_mc_printk(KERN_ERR, mci, "Unable to request irq %d for ECC SEC", sec_irq); status = -ENODEV; goto fail2; } ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCDED irq is %d\n", ded_irq); ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCSEC irq is %d\n", sec_irq); pdata->irqs.ded = ded_irq; pdata->irqs.sec = sec_irq; return 0; fail2: free_irq(sec_irq, mci); fail1: free_irq(ded_irq, mci); fail: return status; } /** * ppc4xx_edac_map_dcrs - locate and map controller registers * @np: A pointer to the device tree node containing the DCR * resources to map. * @dcr_host: A pointer to the DCR data to populate with the * DCR mapping. * * This routine attempts to locate in the device tree and map the DCR * register resources associated with the controller's indirect DCR * address and data windows. * * Returns 0 if the DCRs were successfully mapped; otherwise, < 0 on * error. */ static int ppc4xx_edac_map_dcrs(const struct device_node *np, dcr_host_t *dcr_host) { unsigned int dcr_base, dcr_len; if (np == NULL || dcr_host == NULL) return -EINVAL; /* Get the DCR resource extent and sanity check the values. */ dcr_base = dcr_resource_start(np, 0); dcr_len = dcr_resource_len(np, 0); if (dcr_base == 0 || dcr_len == 0) { ppc4xx_edac_printk(KERN_ERR, "Failed to obtain DCR property.\n"); return -ENODEV; } if (dcr_len != SDRAM_DCR_RESOURCE_LEN) { ppc4xx_edac_printk(KERN_ERR, "Unexpected DCR length %d, expected %d.\n", dcr_len, SDRAM_DCR_RESOURCE_LEN); return -ENODEV; } /* Attempt to map the DCR extent. */ *dcr_host = dcr_map(np, dcr_base, dcr_len); if (!DCR_MAP_OK(*dcr_host)) { ppc4xx_edac_printk(KERN_INFO, "Failed to map DCRs.\n"); return -ENODEV; } return 0; } /** * ppc4xx_edac_probe - check controller and bind driver * @op: A pointer to the OpenFirmware device tree node associated * with the controller being probed for driver binding. * * This routine probes a specific ibm,sdram-4xx-ddr2 controller * instance for binding with the driver. * * Returns 0 if the controller instance was successfully bound to the * driver; otherwise, < 0 on error. */ static int ppc4xx_edac_probe(struct platform_device *op) { int status = 0; u32 mcopt1, memcheck; dcr_host_t dcr_host; const struct device_node *np = op->dev.of_node; struct mem_ctl_info *mci = NULL; struct edac_mc_layer layers[2]; static int ppc4xx_edac_instance; /* * At this point, we only support the controller realized on * the AMCC PPC 405EX[r]. Reject anything else. */ if (!of_device_is_compatible(np, "ibm,sdram-405ex") && !of_device_is_compatible(np, "ibm,sdram-405exr")) { ppc4xx_edac_printk(KERN_NOTICE, "Only the PPC405EX[r] is supported.\n"); return -ENODEV; } /* * Next, get the DCR property and attempt to map it so that we * can probe the controller. */ status = ppc4xx_edac_map_dcrs(np, &dcr_host); if (status) return status; /* * First determine whether ECC is enabled at all. If not, * there is no useful checking or monitoring that can be done * for this controller. */ mcopt1 = mfsdram(&dcr_host, SDRAM_MCOPT1); memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK); if (memcheck == SDRAM_MCOPT1_MCHK_NON) { ppc4xx_edac_printk(KERN_INFO, "%s: No ECC memory detected or " "ECC is disabled.\n", np->full_name); status = -ENODEV; goto done; } /* * At this point, we know ECC is enabled, allocate an EDAC * controller instance and perform the appropriate * initialization. */ layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers[0].size = ppc4xx_edac_nr_csrows; layers[0].is_virt_csrow = true; layers[1].type = EDAC_MC_LAYER_CHANNEL; layers[1].size = ppc4xx_edac_nr_chans; layers[1].is_virt_csrow = false; mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers, sizeof(struct ppc4xx_edac_pdata)); if (mci == NULL) { ppc4xx_edac_printk(KERN_ERR, "%s: " "Failed to allocate EDAC MC instance!\n", np->full_name); status = -ENOMEM; goto done; } status = ppc4xx_edac_mc_init(mci, op, &dcr_host, mcopt1); if (status) { ppc4xx_edac_mc_printk(KERN_ERR, mci, "Failed to initialize instance!\n"); goto fail; } /* * We have a valid, initialized EDAC instance bound to the * controller. Attempt to register it with the EDAC subsystem * and, if necessary, register interrupts. */ if (edac_mc_add_mc(mci)) { ppc4xx_edac_mc_printk(KERN_ERR, mci, "Failed to add instance!\n"); status = -ENODEV; goto fail; } if (edac_op_state == EDAC_OPSTATE_INT) { status = ppc4xx_edac_register_irq(op, mci); if (status) goto fail1; } ppc4xx_edac_instance++; return 0; fail1: edac_mc_del_mc(mci->pdev); fail: edac_mc_free(mci); done: return status; } /** * ppc4xx_edac_remove - unbind driver from controller * @op: A pointer to the OpenFirmware device tree node associated * with the controller this EDAC instance is to be unbound/removed * from. * * This routine unbinds the EDAC memory controller instance associated * with the specified ibm,sdram-4xx-ddr2 controller described by the * OpenFirmware device tree node passed as a parameter. * * Unconditionally returns 0. */ static int ppc4xx_edac_remove(struct platform_device *op) { struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); struct ppc4xx_edac_pdata *pdata = mci->pvt_info; if (edac_op_state == EDAC_OPSTATE_INT) { free_irq(pdata->irqs.sec, mci); free_irq(pdata->irqs.ded, mci); } dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN); edac_mc_del_mc(mci->pdev); edac_mc_free(mci); return 0; } /** * ppc4xx_edac_opstate_init - initialize EDAC reporting method * * This routine ensures that the EDAC memory controller reporting * method is mapped to a sane value as the EDAC core defines the value * to EDAC_OPSTATE_INVAL by default. We don't call the global * opstate_init as that defaults to polling and we want interrupt as * the default. */ static inline void __init ppc4xx_edac_opstate_init(void) { switch (edac_op_state) { case EDAC_OPSTATE_POLL: case EDAC_OPSTATE_INT: break; default: edac_op_state = EDAC_OPSTATE_INT; break; } ppc4xx_edac_printk(KERN_INFO, "Reporting type: %s\n", ((edac_op_state == EDAC_OPSTATE_POLL) ? EDAC_OPSTATE_POLL_STR : ((edac_op_state == EDAC_OPSTATE_INT) ? EDAC_OPSTATE_INT_STR : EDAC_OPSTATE_UNKNOWN_STR))); } /** * ppc4xx_edac_init - driver/module insertion entry point * * This routine is the driver/module insertion entry point. It * initializes the EDAC memory controller reporting state and * registers the driver as an OpenFirmware device tree platform * driver. */ static int __init ppc4xx_edac_init(void) { ppc4xx_edac_printk(KERN_INFO, PPC4XX_EDAC_MODULE_REVISION "\n"); ppc4xx_edac_opstate_init(); return platform_driver_register(&ppc4xx_edac_driver); } /** * ppc4xx_edac_exit - driver/module removal entry point * * This routine is the driver/module removal entry point. It * unregisters the driver as an OpenFirmware device tree platform * driver. */ static void __exit ppc4xx_edac_exit(void) { platform_driver_unregister(&ppc4xx_edac_driver); } module_init(ppc4xx_edac_init); module_exit(ppc4xx_edac_exit); MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>"); MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller"); module_param(edac_op_state, int, 0444); MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting State: " "0=" EDAC_OPSTATE_POLL_STR ", 2=" EDAC_OPSTATE_INT_STR);