summaryrefslogtreecommitdiffstats
path: root/kernel/drivers/gpu/drm/radeon/smu7_fusion.h
blob: 78ada9ffd5082d262ecf4bb769acd67650289d98 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef SMU7_FUSION_H
#define SMU7_FUSION_H

#include "smu7.h"

#pragma pack(push, 1)

#define SMU7_DTE_ITERATIONS 5
#define SMU7_DTE_SOURCES 5
#define SMU7_DTE_SINKS 3
#define SMU7_NUM_CPU_TES 2
#define SMU7_NUM_GPU_TES 1
#define SMU7_NUM_NON_TES 2

// All 'soft registers' should be uint32_t.
struct SMU7_SoftRegisters
{
    uint32_t        RefClockFrequency;
    uint32_t        PmTimerP;
    uint32_t        FeatureEnables;
    uint32_t        HandshakeDisables;

    uint8_t         DisplayPhy1Config;
    uint8_t         DisplayPhy2Config;
    uint8_t         DisplayPhy3Config;
    uint8_t         DisplayPhy4Config;

    uint8_t         DisplayPhy5Config;
    uint8_t         DisplayPhy6Config;
    uint8_t         DisplayPhy7Config;
    uint8_t         DisplayPhy8Config;

    uint32_t        AverageGraphicsA;
    uint32_t        AverageMemoryA;
    uint32_t        AverageGioA;

    uint8_t         SClkDpmEnabledLevels;
    uint8_t         MClkDpmEnabledLevels;
    uint8_t         LClkDpmEnabledLevels;
    uint8_t         PCIeDpmEnabledLevels;

    uint8_t         UVDDpmEnabledLevels;
    uint8_t         SAMUDpmEnabledLevels;
    uint8_t         ACPDpmEnabledLevels;
    uint8_t         VCEDpmEnabledLevels;

    uint32_t        DRAM_LOG_ADDR_H;
    uint32_t        DRAM_LOG_ADDR_L;
    uint32_t        DRAM_LOG_PHY_ADDR_H;
    uint32_t        DRAM_LOG_PHY_ADDR_L;
    uint32_t        DRAM_LOG_BUFF_SIZE;
    uint32_t        UlvEnterC;
    uint32_t        UlvTime;
    uint32_t        Reserved[3];

};

typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;

struct SMU7_Fusion_GraphicsLevel
{
    uint32_t    MinVddNb;

    uint32_t    SclkFrequency;

    uint8_t     Vid;
    uint8_t     VidOffset;
    uint16_t    AT;

    uint8_t     PowerThrottle;
    uint8_t     GnbSlow;
    uint8_t     ForceNbPs1;
    uint8_t     SclkDid;

    uint8_t     DisplayWatermark;
    uint8_t     EnabledForActivity;
    uint8_t     EnabledForThrottle;
    uint8_t     UpH;

    uint8_t     DownH;
    uint8_t     VoltageDownH;
    uint8_t     DeepSleepDivId;

    uint8_t     ClkBypassCntl;

    uint32_t    reserved;
};

typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel;

struct SMU7_Fusion_GIOLevel
{
    uint8_t     EnabledForActivity;
    uint8_t     LclkDid;
    uint8_t     Vid;
    uint8_t     VoltageDownH;

    uint32_t    MinVddNb;

    uint16_t    ResidencyCounter;
    uint8_t     UpH;
    uint8_t     DownH;

    uint32_t    LclkFrequency;

    uint8_t     ActivityLevel;
    uint8_t     EnabledForThrottle;

    uint8_t     ClkBypassCntl;

    uint8_t     padding;
};

typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel;

// UVD VCLK/DCLK state (level) definition.
struct SMU7_Fusion_UvdLevel
{
    uint32_t VclkFrequency;
    uint32_t DclkFrequency;
    uint16_t MinVddNb;
    uint8_t  VclkDivider;
    uint8_t  DclkDivider;

    uint8_t     VClkBypassCntl;
    uint8_t     DClkBypassCntl;

    uint8_t     padding[2];

};

typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel;

// Clocks for other external blocks (VCE, ACP, SAMU).
struct SMU7_Fusion_ExtClkLevel
{
    uint32_t Frequency;
    uint16_t MinVoltage;
    uint8_t  Divider;
    uint8_t  ClkBypassCntl;

    uint32_t Reserved;
};
typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel;

struct SMU7_Fusion_ACPILevel
{
    uint32_t    Flags;
    uint32_t    MinVddNb;
    uint32_t    SclkFrequency;
    uint8_t     SclkDid;
    uint8_t     GnbSlow;
    uint8_t     ForceNbPs1;
    uint8_t     DisplayWatermark;
    uint8_t     DeepSleepDivId;
    uint8_t     padding[3];
};

typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel;

struct SMU7_Fusion_NbDpm
{
    uint8_t DpmXNbPsHi;
    uint8_t DpmXNbPsLo;
    uint8_t Dpm0PgNbPsHi;
    uint8_t Dpm0PgNbPsLo;
    uint8_t EnablePsi1;
    uint8_t SkipDPM0;
    uint8_t SkipPG;
    uint8_t Hysteresis;
    uint8_t EnableDpmPstatePoll;
    uint8_t padding[3];
};

typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm;

struct SMU7_Fusion_StateInfo
{
    uint32_t SclkFrequency;
    uint32_t LclkFrequency;
    uint32_t VclkFrequency;
    uint32_t DclkFrequency;
    uint32_t SamclkFrequency;
    uint32_t AclkFrequency;
    uint32_t EclkFrequency;
    uint8_t  DisplayWatermark;
    uint8_t  McArbIndex;
    int8_t   SclkIndex;
    int8_t   MclkIndex;
};

typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo;

struct SMU7_Fusion_DpmTable
{
    uint32_t                            SystemFlags;

    SMU7_PIDController                  GraphicsPIDController;
    SMU7_PIDController                  GioPIDController;

    uint8_t                            GraphicsDpmLevelCount;
    uint8_t                            GIOLevelCount;
    uint8_t                            UvdLevelCount;
    uint8_t                            VceLevelCount;

    uint8_t                            AcpLevelCount;
    uint8_t                            SamuLevelCount;
    uint16_t                           FpsHighT;

    SMU7_Fusion_GraphicsLevel         GraphicsLevel           [SMU__NUM_SCLK_DPM_STATE];
    SMU7_Fusion_ACPILevel             ACPILevel;
    SMU7_Fusion_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
    SMU7_Fusion_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
    SMU7_Fusion_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
    SMU7_Fusion_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];

    uint8_t                           UvdBootLevel;
    uint8_t                           VceBootLevel;
    uint8_t                           AcpBootLevel;
    uint8_t                           SamuBootLevel;
    uint8_t                           UVDInterval;
    uint8_t                           VCEInterval;
    uint8_t                           ACPInterval;
    uint8_t                           SAMUInterval;

    uint8_t                           GraphicsBootLevel;
    uint8_t                           GraphicsInterval;
    uint8_t                           GraphicsThermThrottleEnable;
    uint8_t                           GraphicsVoltageChangeEnable;

    uint8_t                           GraphicsClkSlowEnable;
    uint8_t                           GraphicsClkSlowDivider;
    uint16_t                          FpsLowT;

    uint32_t                          DisplayCac;
    uint32_t                          LowSclkInterruptT;

    uint32_t                          DRAM_LOG_ADDR_H;
    uint32_t                          DRAM_LOG_ADDR_L;
    uint32_t                          DRAM_LOG_PHY_ADDR_H;
    uint32_t                          DRAM_LOG_PHY_ADDR_L;
    uint32_t                          DRAM_LOG_BUFF_SIZE;

};

struct SMU7_Fusion_GIODpmTable
{

    SMU7_Fusion_GIOLevel              GIOLevel                [SMU7_MAX_LEVELS_GIO];

    SMU7_PIDController                GioPIDController;

    uint32_t                          GIOLevelCount;

    uint8_t                           Enable;
    uint8_t                           GIOVoltageChangeEnable;
    uint8_t                           GIOBootLevel;
    uint8_t                           padding;
    uint8_t                           padding1[2];
    uint8_t                           TargetState;
    uint8_t                           CurrenttState;
    uint8_t                           ThrottleOnHtc;
    uint8_t                           ThermThrottleStatus;
    uint8_t                           ThermThrottleTempSelect;
    uint8_t                           ThermThrottleEnable;
    uint16_t                          TemperatureLimitHigh;
    uint16_t                          TemperatureLimitLow;

};

typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable;
typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable;

#pragma pack(pop)

#endif