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/*
 * Performance event support - hardware-specific disambiguation
 *
 * For now this is a compile-time decision, but eventually it should be
 * runtime.  This would allow multiplatform perf event support for e300 (fsl
 * embedded perf counters) plus server/classic, and would accommodate
 * devices other than the core which provide their own performance counters.
 *
 * Copyright 2010 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#ifdef CONFIG_PPC_PERF_CTRS
#include <asm/perf_event_server.h>
#endif

#ifdef CONFIG_FSL_EMB_PERF_EVENT
#include <asm/perf_event_fsl_emb.h>
#endif

#ifdef CONFIG_PERF_EVENTS
#include <asm/ptrace.h>
#include <asm/reg.h>

/*
 * Overload regs->result to specify whether we should use the MSR (result
 * is zero) or the SIAR (result is non zero).
 */
#define perf_arch_fetch_caller_regs(regs, __ip)			\
	do {							\
		(regs)->result = 0;				\
		(regs)->nip = __ip;				\
		(regs)->gpr[1] = current_stack_pointer();	\
		asm volatile("mfmsr %0" : "=r" ((regs)->msr));	\
	} while (0)
#endif
lass="cp"> #define SC_QAM32 0x0C /* 32QAM modulation */ #define SC_QAM16 0x08 /* 16QAM modulation */ #define SC_QAM4NR 0x04 /* 4QAM-NR modulation */ #define SC_QAM4 0x00 /* 4QAM modulation */ #define LGS_FEC_MASK 0x03 /* FEC Rate Mask */ #define LGS_FEC_0_4 0x00 /* FEC Rate 0.4 */ #define LGS_FEC_0_6 0x01 /* FEC Rate 0.6 */ #define LGS_FEC_0_8 0x02 /* FEC Rate 0.8 */ #define TIM_MASK 0x20 /* Time Interleave Length Mask */ #define TIM_LONG 0x20 /* Time Interleave Length = 720 */ #define TIM_MIDDLE 0x00 /* Time Interleave Length = 240 */ #define CF_MASK 0x80 /* Control Frame Mask */ #define CF_EN 0x80 /* Control Frame On */ #define GI_MASK 0x03 /* Guard Interval Mask */ #define GI_420 0x00 /* 1/9 Guard Interval */ #define GI_595 0x01 /* */ #define GI_945 0x02 /* 1/4 Guard Interval */ #define TS_PARALLEL 0x00 /* Parallel TS Output a.k.a. SPI */ #define TS_SERIAL 0x01 /* Serial TS Output a.k.a. SSI */ #define TS_CLK_NORMAL 0x00 /* MPEG Clock Normal */ #define TS_CLK_INVERTED 0x02 /* MPEG Clock Inverted */ #define TS_CLK_GATED 0x00 /* MPEG clock gated */ #define TS_CLK_FREERUN 0x04 /* MPEG clock free running*/ #endif