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-rw-r--r--core/results/results_constants.py12
1 files changed, 6 insertions, 6 deletions
diff --git a/core/results/results_constants.py b/core/results/results_constants.py
index 263e07a3..58086e32 100644
--- a/core/results/results_constants.py
+++ b/core/results/results_constants.py
@@ -27,11 +27,11 @@ class ResultsConstants(object):
#Traffic Constants
#RFC2544 Throughput & Continuous
- THROUGHPUT_TX_FPS = 'throughput_tx_fps'
+ TX_RATE_FPS = 'tx_rate_fps'
THROUGHPUT_RX_FPS = 'throughput_rx_fps'
- THROUGHPUT_TX_MBPS = 'throughput_tx_mbps'
+ TX_RATE_MBPS = 'tx_rate_mbps'
THROUGHPUT_RX_MBPS = 'throughput_rx_mbps'
- THROUGHPUT_TX_PERCENT = 'throughput_tx_percent'
+ TX_RATE_PERCENT = 'tx_rate_percent'
THROUGHPUT_RX_PERCENT = 'throughput_rx_percent'
MIN_LATENCY_NS = 'min_latency_ns'
MAX_LATENCY_NS = 'max_latency_ns'
@@ -67,11 +67,11 @@ class ResultsConstants(object):
ResultsConstants.ID,
ResultsConstants.PACKET_SIZE,
ResultsConstants.DEPLOYMENT,
- ResultsConstants.THROUGHPUT_TX_FPS,
+ ResultsConstants.TX_RATE_FPS,
ResultsConstants.THROUGHPUT_RX_FPS,
- ResultsConstants.THROUGHPUT_TX_MBPS,
+ ResultsConstants.TX_RATE_MBPS,
ResultsConstants.THROUGHPUT_RX_MBPS,
- ResultsConstants.THROUGHPUT_TX_PERCENT,
+ ResultsConstants.TX_RATE_PERCENT,
ResultsConstants.THROUGHPUT_RX_PERCENT,
ResultsConstants.MIN_LATENCY_NS,
ResultsConstants.MAX_LATENCY_NS,
a> 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 
/***********************license start***************
 * Author: Cavium Networks
 *
 * Contact: support@caviumnetworks.com
 * This file is part of the OCTEON SDK
 *
 * Copyright (c) 2003-2012 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 *
 * This file is distributed in the hope that it will be useful, but
 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 * NONINFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this file; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 * or visit http://www.gnu.org/licenses/.
 *
 * This file may also be available under a different license from Cavium.
 * Contact Cavium Networks for more information
 ***********************license end**************************************/

#ifndef __CVMX_PCSX_DEFS_H__
#define __CVMX_PCSX_DEFS_H__

static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
}

union cvmx_pcsx_anx_adv_reg {
	uint64_t u64;
	struct cvmx_pcsx_anx_adv_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t np:1;
		uint64_t reserved_14_14:1;
		uint64_t rem_flt:2;
		uint64_t reserved_9_11:3;
		uint64_t pause:2;
		uint64_t hfd:1;
		uint64_t fd:1;
		uint64_t reserved_0_4:5;
#else
		uint64_t reserved_0_4:5;
		uint64_t fd:1;
		uint64_t hfd:1;
		uint64_t pause:2;
		uint64_t reserved_9_11:3;
		uint64_t rem_flt:2;
		uint64_t reserved_14_14:1;
		uint64_t np:1;
		uint64_t reserved_16_63:48;
#endif
	} s;
	struct cvmx_pcsx_anx_adv_reg_s cn52xx;
	struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
	struct cvmx_pcsx_anx_adv_reg_s cn56xx;
	struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
	struct cvmx_pcsx_anx_adv_reg_s cn61xx;
	struct cvmx_pcsx_anx_adv_reg_s cn63xx;
	struct cvmx_pcsx_anx_adv_reg_s cn63xxp1;
	struct cvmx_pcsx_anx_adv_reg_s cn66xx;
	struct cvmx_pcsx_anx_adv_reg_s cn68xx;
	struct cvmx_pcsx_anx_adv_reg_s cn68xxp1;
	struct cvmx_pcsx_anx_adv_reg_s cnf71xx;
};

union cvmx_pcsx_anx_ext_st_reg {
	uint64_t u64;
	struct cvmx_pcsx_anx_ext_st_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t thou_xfd:1;
		uint64_t thou_xhd:1;
		uint64_t thou_tfd:1;
		uint64_t thou_thd:1;
		uint64_t reserved_0_11:12;
#else
		uint64_t reserved_0_11:12;
		uint64_t thou_thd:1;
		uint64_t thou_tfd:1;
		uint64_t thou_xhd:1;
		uint64_t thou_xfd:1;
		uint64_t reserved_16_63:48;
#endif
	} s;
	struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
	struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
	struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
	struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
	struct cvmx_pcsx_anx_ext_st_reg_s cn61xx;
	struct cvmx_pcsx_anx_ext_st_reg_s cn63xx;
	struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1;
	struct cvmx_pcsx_anx_ext_st_reg_s cn66xx;
	struct cvmx_pcsx_anx_ext_st_reg_s cn68xx;
	struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1;
	struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx;
};

union cvmx_pcsx_anx_lp_abil_reg {
	uint64_t u64;
	struct cvmx_pcsx_anx_lp_abil_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t np:1;
		uint64_t ack:1;
		uint64_t rem_flt:2;
		uint64_t reserved_9_11:3;
		uint64_t pause:2;
		uint64_t hfd:1;
		uint64_t fd:1;
		uint64_t reserved_0_4:5;
#else
		uint64_t reserved_0_4:5;
		uint64_t fd:1;
		uint64_t hfd:1;
		uint64_t pause:2;
		uint64_t reserved_9_11:3;
		uint64_t rem_flt:2;
		uint64_t ack:1;
		uint64_t np:1;
		uint64_t reserved_16_63:48;
#endif
	} s;
	struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
	struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
	struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
	struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
	struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx;
	struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx;
	struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1;
	struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx;
	struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx;
	struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1;
	struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx;
};

union cvmx_pcsx_anx_results_reg {
	uint64_t u64;
	struct cvmx_pcsx_anx_results_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_7_63:57;
		uint64_t pause:2;
		uint64_t spd:2;
		uint64_t an_cpt:1;
		uint64_t dup:1;
		uint64_t link_ok:1;
#else
		uint64_t link_ok:1;
		uint64_t dup:1;
		uint64_t an_cpt:1;
		uint64_t spd:2;
		uint64_t pause:2;
		uint64_t reserved_7_63:57;
#endif
	} s;
	struct cvmx_pcsx_anx_results_reg_s cn52xx;
	struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
	struct cvmx_pcsx_anx_results_reg_s cn56xx;
	struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
	struct cvmx_pcsx_anx_results_reg_s cn61xx;
	struct cvmx_pcsx_anx_results_reg_s cn63xx;
	struct cvmx_pcsx_anx_results_reg_s cn63xxp1;
	struct cvmx_pcsx_anx_results_reg_s cn66xx;
	struct cvmx_pcsx_anx_results_reg_s cn68xx;
	struct cvmx_pcsx_anx_results_reg_s cn68xxp1;
	struct cvmx_pcsx_anx_results_reg_s cnf71xx;
};

union cvmx_pcsx_intx_en_reg {
	uint64_t u64;
	struct cvmx_pcsx_intx_en_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_13_63:51;
		uint64_t dbg_sync_en:1;
		uint64_t dup:1;
		uint64_t sync_bad_en:1;
		uint64_t an_bad_en:1;
		uint64_t rxlock_en:1;
		uint64_t rxbad_en:1;
		uint64_t rxerr_en:1;
		uint64_t txbad_en:1;
		uint64_t txfifo_en:1;
		uint64_t txfifu_en:1;
		uint64_t an_err_en:1;
		uint64_t xmit_en:1;
		uint64_t lnkspd_en:1;
#else
		uint64_t lnkspd_en:1;
		uint64_t xmit_en:1;
		uint64_t an_err_en:1;
		uint64_t txfifu_en:1;
		uint64_t txfifo_en:1;
		uint64_t txbad_en:1;
		uint64_t rxerr_en:1;
		uint64_t rxbad_en:1;
		uint64_t rxlock_en:1;
		uint64_t an_bad_en:1;
		uint64_t sync_bad_en:1;
		uint64_t dup:1;
		uint64_t dbg_sync_en:1;
		uint64_t reserved_13_63:51;
#endif
	} s;
	struct cvmx_pcsx_intx_en_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_12_63:52;
		uint64_t dup:1;
		uint64_t sync_bad_en:1;
		uint64_t an_bad_en:1;
		uint64_t rxlock_en:1;
		uint64_t rxbad_en:1;
		uint64_t rxerr_en:1;
		uint64_t txbad_en:1;
		uint64_t txfifo_en:1;
		uint64_t txfifu_en:1;
		uint64_t an_err_en:1;
		uint64_t xmit_en:1;
		uint64_t lnkspd_en:1;
#else
		uint64_t lnkspd_en:1;
		uint64_t xmit_en:1;
		uint64_t an_err_en:1;
		uint64_t txfifu_en:1;
		uint64_t txfifo_en:1;
		uint64_t txbad_en:1;
		uint64_t rxerr_en:1;
		uint64_t rxbad_en:1;
		uint64_t rxlock_en:1;
		uint64_t an_bad_en:1;
		uint64_t sync_bad_en:1;
		uint64_t dup:1;
		uint64_t reserved_12_63:52;
#endif
	} cn52xx;
	struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1;
	struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx;
	struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1;
	struct cvmx_pcsx_intx_en_reg_s cn61xx;
	struct cvmx_pcsx_intx_en_reg_s cn63xx;
	struct cvmx_pcsx_intx_en_reg_s cn63xxp1;
	struct cvmx_pcsx_intx_en_reg_s cn66xx;
	struct cvmx_pcsx_intx_en_reg_s cn68xx;
	struct cvmx_pcsx_intx_en_reg_s cn68xxp1;
	struct cvmx_pcsx_intx_en_reg_s cnf71xx;
};

union cvmx_pcsx_intx_reg {
	uint64_t u64;
	struct cvmx_pcsx_intx_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_13_63:51;
		uint64_t dbg_sync:1;
		uint64_t dup:1;
		uint64_t sync_bad:1;
		uint64_t an_bad:1;
		uint64_t rxlock:1;
		uint64_t rxbad:1;
		uint64_t rxerr:1;
		uint64_t txbad:1;
		uint64_t txfifo:1;
		uint64_t txfifu:1;
		uint64_t an_err:1;
		uint64_t xmit:1;
		uint64_t lnkspd:1;
#else
		uint64_t lnkspd:1;
		uint64_t xmit:1;
		uint64_t an_err:1;
		uint64_t txfifu:1;
		uint64_t txfifo:1;
		uint64_t txbad:1;
		uint64_t rxerr:1;
		uint64_t rxbad:1;
		uint64_t rxlock:1;
		uint64_t an_bad:1;
		uint64_t sync_bad:1;
		uint64_t dup:1;
		uint64_t dbg_sync:1;
		uint64_t reserved_13_63:51;
#endif
	} s;
	struct cvmx_pcsx_intx_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_12_63:52;
		uint64_t dup:1;
		uint64_t sync_bad:1;
		uint64_t an_bad:1;
		uint64_t rxlock:1;
		uint64_t rxbad:1;
		uint64_t rxerr:1;
		uint64_t txbad:1;
		uint64_t txfifo:1;
		uint64_t txfifu:1;
		uint64_t an_err:1;
		uint64_t xmit:1;
		uint64_t lnkspd:1;
#else
		uint64_t lnkspd:1;
		uint64_t xmit:1;
		uint64_t an_err:1;
		uint64_t txfifu:1;
		uint64_t txfifo:1;
		uint64_t txbad:1;
		uint64_t rxerr:1;
		uint64_t rxbad:1;
		uint64_t rxlock:1;
		uint64_t an_bad:1;
		uint64_t sync_bad:1;
		uint64_t dup:1;
		uint64_t reserved_12_63:52;
#endif
	} cn52xx;
	struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1;
	struct cvmx_pcsx_intx_reg_cn52xx cn56xx;
	struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1;
	struct cvmx_pcsx_intx_reg_s cn61xx;
	struct cvmx_pcsx_intx_reg_s cn63xx;
	struct cvmx_pcsx_intx_reg_s cn63xxp1;
	struct cvmx_pcsx_intx_reg_s cn66xx;
	struct cvmx_pcsx_intx_reg_s cn68xx;
	struct cvmx_pcsx_intx_reg_s cn68xxp1;
	struct cvmx_pcsx_intx_reg_s cnf71xx;
};

union cvmx_pcsx_linkx_timer_count_reg {
	uint64_t u64;
	struct cvmx_pcsx_linkx_timer_count_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t count:16;
#else
		uint64_t count:16;
		uint64_t reserved_16_63:48;
#endif
	} s;
	struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
	struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
	struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
	struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
	struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx;
	struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx;
	struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1;
	struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx;
	struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx;
	struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1;
	struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx;
};

union cvmx_pcsx_log_anlx_reg {
	uint64_t u64;
	struct cvmx_pcsx_log_anlx_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_4_63:60;
		uint64_t lafifovfl:1;
		uint64_t la_en:1;
		uint64_t pkt_sz:2;
#else
		uint64_t pkt_sz:2;
		uint64_t la_en:1;
		uint64_t lafifovfl:1;
		uint64_t reserved_4_63:60;
#endif
	} s;
	struct cvmx_pcsx_log_anlx_reg_s cn52xx;
	struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
	struct cvmx_pcsx_log_anlx_reg_s cn56xx;
	struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
	struct cvmx_pcsx_log_anlx_reg_s cn61xx;
	struct cvmx_pcsx_log_anlx_reg_s cn63xx;
	struct cvmx_pcsx_log_anlx_reg_s cn63xxp1;
	struct cvmx_pcsx_log_anlx_reg_s cn66xx;
	struct cvmx_pcsx_log_anlx_reg_s cn68xx;
	struct cvmx_pcsx_log_anlx_reg_s cn68xxp1;
	struct cvmx_pcsx_log_anlx_reg_s cnf71xx;
};

union cvmx_pcsx_miscx_ctl_reg {
	uint64_t u64;
	struct cvmx_pcsx_miscx_ctl_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_13_63:51;
		uint64_t sgmii:1;
		uint64_t gmxeno:1;
		uint64_t loopbck2:1;
		uint64_t mac_phy:1;
		uint64_t mode:1;
		uint64_t an_ovrd:1;
		uint64_t samp_pt:7;
#else
		uint64_t samp_pt:7;
		uint64_t an_ovrd:1;
		uint64_t mode:1;
		uint64_t mac_phy:1;
		uint64_t loopbck2:1;
		uint64_t gmxeno:1;
		uint64_t sgmii:1;
		uint64_t reserved_13_63:51;
#endif
	} s;
	struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
	struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
	struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
	struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
	struct cvmx_pcsx_miscx_ctl_reg_s cn61xx;
	struct cvmx_pcsx_miscx_ctl_reg_s cn63xx;
	struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1;
	struct cvmx_pcsx_miscx_ctl_reg_s cn66xx;
	struct cvmx_pcsx_miscx_ctl_reg_s cn68xx;
	struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1;
	struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx;
};

union cvmx_pcsx_mrx_control_reg {
	uint64_t u64;
	struct cvmx_pcsx_mrx_control_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t reset:1;
		uint64_t loopbck1:1;
		uint64_t spdlsb:1;
		uint64_t an_en:1;
		uint64_t pwr_dn:1;
		uint64_t reserved_10_10:1;
		uint64_t rst_an:1;
		uint64_t dup:1;
		uint64_t coltst:1;
		uint64_t spdmsb:1;
		uint64_t uni:1;
		uint64_t reserved_0_4:5;
#else
		uint64_t reserved_0_4:5;
		uint64_t uni:1;
		uint64_t spdmsb:1;
		uint64_t coltst:1;
		uint64_t dup:1;
		uint64_t rst_an:1;
		uint64_t reserved_10_10:1;
		uint64_t pwr_dn:1;
		uint64_t an_en:1;
		uint64_t spdlsb:1;
		uint64_t loopbck1:1;
		uint64_t reset:1;
		uint64_t reserved_16_63:48;
#endif
	} s;
	struct cvmx_pcsx_mrx_control_reg_s cn52xx;
	struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
	struct cvmx_pcsx_mrx_control_reg_s cn56xx;
	struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
	struct cvmx_pcsx_mrx_control_reg_s cn61xx;
	struct cvmx_pcsx_mrx_control_reg_s cn63xx;
	struct cvmx_pcsx_mrx_control_reg_s cn63xxp1;
	struct cvmx_pcsx_mrx_control_reg_s cn66xx;
	struct cvmx_pcsx_mrx_control_reg_s cn68xx;
	struct cvmx_pcsx_mrx_control_reg_s cn68xxp1;
	struct cvmx_pcsx_mrx_control_reg_s cnf71xx;
};

union cvmx_pcsx_mrx_status_reg {
	uint64_t u64;
	struct cvmx_pcsx_mrx_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t hun_t4:1;
		uint64_t hun_xfd:1;
		uint64_t hun_xhd:1;
		uint64_t ten_fd:1;
		uint64_t ten_hd:1;
		uint64_t hun_t2fd:1;
		uint64_t hun_t2hd:1;
		uint64_t ext_st:1;
		uint64_t reserved_7_7:1;
		uint64_t prb_sup:1;
		uint64_t an_cpt:1;
		uint64_t rm_flt:1;
		uint64_t an_abil:1;
		uint64_t lnk_st:1;
		uint64_t reserved_1_1:1;
		uint64_t extnd:1;
#else
		uint64_t extnd:1;
		uint64_t reserved_1_1:1;
		uint64_t lnk_st:1;
		uint64_t an_abil:1;
		uint64_t rm_flt:1;
		uint64_t an_cpt:1;
		uint64_t prb_sup:1;
		uint64_t reserved_7_7:1;
		uint64_t ext_st:1;
		uint64_t hun_t2hd:1;
		uint64_t hun_t2fd:1;
		uint64_t ten_hd:1;
		uint64_t ten_fd:1;
		uint64_t hun_xhd:1;
		uint64_t hun_xfd:1;
		uint64_t hun_t4:1;
		uint64_t reserved_16_63:48;
#endif
	} s;
	struct cvmx_pcsx_mrx_status_reg_s cn52xx;
	struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
	struct cvmx_pcsx_mrx_status_reg_s cn56xx;
	struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
	struct cvmx_pcsx_mrx_status_reg_s cn61xx;
	struct cvmx_pcsx_mrx_status_reg_s cn63xx;
	struct cvmx_pcsx_mrx_status_reg_s cn63xxp1;
	struct cvmx_pcsx_mrx_status_reg_s cn66xx;
	struct cvmx_pcsx_mrx_status_reg_s cn68xx;
	struct cvmx_pcsx_mrx_status_reg_s cn68xxp1;
	struct cvmx_pcsx_mrx_status_reg_s cnf71xx;
};

union cvmx_pcsx_rxx_states_reg {
	uint64_t u64;
	struct cvmx_pcsx_rxx_states_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t rx_bad:1;
		uint64_t rx_st:5;
		uint64_t sync_bad:1;
		uint64_t sync:4;
		uint64_t an_bad:1;
		uint64_t an_st:4;
#else
		uint64_t an_st:4;
		uint64_t an_bad:1;
		uint64_t sync:4;
		uint64_t sync_bad:1;
		uint64_t rx_st:5;
		uint64_t rx_bad:1;
		uint64_t reserved_16_63:48;
#endif
	} s;
	struct cvmx_pcsx_rxx_states_reg_s cn52xx;
	struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
	struct cvmx_pcsx_rxx_states_reg_s cn56xx;
	struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
	struct cvmx_pcsx_rxx_states_reg_s cn61xx;
	struct cvmx_pcsx_rxx_states_reg_s cn63xx;
	struct cvmx_pcsx_rxx_states_reg_s cn63xxp1;
	struct cvmx_pcsx_rxx_states_reg_s cn66xx;
	struct cvmx_pcsx_rxx_states_reg_s cn68xx;
	struct cvmx_pcsx_rxx_states_reg_s cn68xxp1;
	struct cvmx_pcsx_rxx_states_reg_s cnf71xx;
};

union cvmx_pcsx_rxx_sync_reg {
	uint64_t u64;
	struct cvmx_pcsx_rxx_sync_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_2_63:62;
		uint64_t sync:1;
		uint64_t bit_lock:1;
#else
		uint64_t bit_lock:1;
		uint64_t sync:1;
		uint64_t reserved_2_63:62;
#endif
	} s;
	struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
	struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
	struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
	struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
	struct cvmx_pcsx_rxx_sync_reg_s cn61xx;
	struct cvmx_pcsx_rxx_sync_reg_s cn63xx;
	struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1;
	struct cvmx_pcsx_rxx_sync_reg_s cn66xx;
	struct cvmx_pcsx_rxx_sync_reg_s cn68xx;
	struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1;
	struct cvmx_pcsx_rxx_sync_reg_s cnf71xx;
};

union cvmx_pcsx_sgmx_an_adv_reg {
	uint64_t u64;
	struct cvmx_pcsx_sgmx_an_adv_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t link:1;
		uint64_t ack:1;
		uint64_t reserved_13_13:1;
		uint64_t dup:1;
		uint64_t speed:2;
		uint64_t reserved_1_9:9;
		uint64_t one:1;
#else
		uint64_t one:1;
		uint64_t reserved_1_9:9;
		uint64_t speed:2;
		uint64_t dup:1;
		uint64_t reserved_13_13:1;
		uint64_t ack:1;
		uint64_t link:1;
		uint64_t reserved_16_63:48;
#endif
	} s;
	struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
	struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
	struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
	struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
	struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx;
	struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx;
	struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1;
	struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx;
	struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx;
	struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1;
	struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx;
};

union cvmx_pcsx_sgmx_lp_adv_reg {
	uint64_t u64;
	struct cvmx_pcsx_sgmx_lp_adv_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t link:1;
		uint64_t reserved_13_14:2;
		uint64_t dup:1;
		uint64_t speed:2;
		uint64_t reserved_1_9:9;
		uint64_t one:1;
#else
		uint64_t one:1;
		uint64_t reserved_1_9:9;
		uint64_t speed:2;
		uint64_t dup:1;
		uint64_t reserved_13_14:2;
		uint64_t link:1;
		uint64_t reserved_16_63:48;
#endif
	} s;
	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx;
	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx;
	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1;
	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx;
	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx;
	struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1;
	struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx;
};

union cvmx_pcsx_txx_states_reg {
	uint64_t u64;
	struct cvmx_pcsx_txx_states_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_7_63:57;
		uint64_t xmit:2;
		uint64_t tx_bad:1;
		uint64_t ord_st:4;
#else
		uint64_t ord_st:4;
		uint64_t tx_bad:1;
		uint64_t xmit:2;
		uint64_t reserved_7_63:57;
#endif
	} s;
	struct cvmx_pcsx_txx_states_reg_s cn52xx;
	struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
	struct cvmx_pcsx_txx_states_reg_s cn56xx;
	struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
	struct cvmx_pcsx_txx_states_reg_s cn61xx;
	struct cvmx_pcsx_txx_states_reg_s cn63xx;
	struct cvmx_pcsx_txx_states_reg_s cn63xxp1;
	struct cvmx_pcsx_txx_states_reg_s cn66xx;
	struct cvmx_pcsx_txx_states_reg_s cn68xx;
	struct cvmx_pcsx_txx_states_reg_s cn68xxp1;
	struct cvmx_pcsx_txx_states_reg_s cnf71xx;
};

union cvmx_pcsx_tx_rxx_polarity_reg {
	uint64_t u64;
	struct cvmx_pcsx_tx_rxx_polarity_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_4_63:60;
		uint64_t rxovrd:1;
		uint64_t autorxpl:1;
		uint64_t rxplrt:1;
		uint64_t txplrt:1;
#else
		uint64_t txplrt:1;
		uint64_t rxplrt:1;
		uint64_t autorxpl:1;
		uint64_t rxovrd:1;
		uint64_t reserved_4_63:60;
#endif
	} s;
	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx;
	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx;
	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1;
	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx;
	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx;
	struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1;
	struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx;
};

#endif