summaryrefslogtreecommitdiffstats
path: root/kernel/arch/arm64/boot/dts/apm/apm-storm.dtsi
blob: 6c5ed119934f5cec0afeafedda99856d639ba391 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
/*
 * dts file for AppliedMicro (APM) X-Gene Storm SOC
 *
 * Copyright (C) 2013, Applied Micro Circuits Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

/ {
	compatible = "apm,xgene-storm";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@000 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x000>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@001 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x001>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@100 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@101 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x101>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@200 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@201 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x201>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@300 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
		cpu@301 {
			device_type = "cpu";
			compatible = "apm,potenza", "arm,armv8";
			reg = <0x0 0x301>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
		};
	};

	gic: interrupt-controller@78010000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x78010000 0x0 0x1000>,	/* GIC Dist */
		      <0x0 0x78020000 0x0 0x1000>,	/* GIC CPU */
		      <0x0 0x78040000 0x0 0x2000>,	/* GIC VCPU Control */
		      <0x0 0x78060000 0x0 0x2000>;	/* GIC VCPU */
		interrupts = <1 9 0xf04>;	/* GIC Maintenence IRQ */
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 0 0xff01>,	/* Secure Phys IRQ */
			     <1 13 0xff01>,	/* Non-secure Phys IRQ */
			     <1 14 0xff01>,	/* Virt IRQ */
			     <1 15 0xff01>;	/* Hyp IRQ */
		clock-frequency = <50000000>;
	};

	pmu {
		compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
		interrupts = <1 12 0xff04>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;

		clocks {
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			refclk: refclk {
				compatible = "fixed-clock";
				#clock-cells = <1>;
				clock-frequency = <100000000>;
				clock-output-names = "refclk";
			};

			pcppll: pcppll@17000100 {
				compatible = "apm,xgene-pcppll-clock";
				#clock-cells = <1>;
				clocks = <&refclk 0>;
				clock-names = "pcppll";
				reg = <0x0 0x17000100 0x0 0x1000>;
				clock-output-names = "pcppll";
				type = <0>;
			};

			socpll: socpll@17000120 {
				compatible = "apm,xgene-socpll-clock";
				#clock-cells = <1>;
				clocks = <&refclk 0>;
				clock-names = "socpll";
				reg = <0x0 0x17000120 0x0 0x1000>;
				clock-output-names = "socpll";
				type = <1>;
			};

			socplldiv2: socplldiv2  {
				compatible = "fixed-factor-clock";
				#clock-cells = <1>;
				clocks = <&socpll 0>;
				clock-names = "socplldiv2";
				clock-mult = <1>;
				clock-div = <2>;
				clock-output-names = "socplldiv2";
			};

			qmlclk: qmlclk {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				clock-names = "qmlclk";
				reg = <0x0 0x1703C000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "qmlclk";
			};

			ethclk: ethclk {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				clock-names = "ethclk";
				reg = <0x0 0x17000000 0x0 0x1000>;
				reg-names = "div-reg";
				divider-offset = <0x238>;
				divider-width = <0x9>;
				divider-shift = <0x0>;
				clock-output-names = "ethclk";
			};

			menetclk: menetclk {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&ethclk 0>;
				reg = <0x0 0x1702C000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "menetclk";
			};

			sge0clk: sge0clk@1f21c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				reg-names = "csr-reg";
				csr-mask = <0x3>;
				clock-output-names = "sge0clk";
			};

			sge1clk: sge1clk@1f21c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				reg-names = "csr-reg";
				csr-mask = <0xc>;
				clock-output-names = "sge1clk";
			};

			xge0clk: xge0clk@1f61c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f61c000 0x0 0x1000>;
				reg-names = "csr-reg";
				csr-mask = <0x3>;
				clock-output-names = "xge0clk";
			};

			xge1clk: xge1clk@1f62c000 {
				compatible = "apm,xgene-device-clock";
				status = "disabled";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f62c000 0x0 0x1000>;
				reg-names = "csr-reg";
				csr-mask = <0x3>;
				clock-output-names = "xge1clk";
			};

			sataphy1clk: sataphy1clk@1f21c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sataphy1clk";
				status = "disabled";
				csr-offset = <0x4>;
				csr-mask = <0x00>;
				enable-offset = <0x0>;
				enable-mask = <0x06>;
			};

			sataphy2clk: sataphy1clk@1f22c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f22c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sataphy2clk";
				status = "ok";
				csr-offset = <0x4>;
				csr-mask = <0x3a>;
				enable-offset = <0x0>;
				enable-mask = <0x06>;
			};

			sataphy3clk: sataphy1clk@1f23c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f23c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sataphy3clk";
				status = "ok";
				csr-offset = <0x4>;
				csr-mask = <0x3a>;
				enable-offset = <0x0>;
				enable-mask = <0x06>;
			};

			sata01clk: sata01clk@1f21c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sata01clk";
				csr-offset = <0x4>;
				csr-mask = <0x05>;
				enable-offset = <0x0>;
				enable-mask = <0x39>;
			};

			sata23clk: sata23clk@1f22c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f22c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sata23clk";
				csr-offset = <0x4>;
				csr-mask = <0x05>;
				enable-offset = <0x0>;
				enable-mask = <0x39>;
			};

			sata45clk: sata45clk@1f23c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f23c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sata45clk";
				csr-offset = <0x4>;
				csr-mask = <0x05>;
				enable-offset = <0x0>;
				enable-mask = <0x39>;
			};

			rtcclk: rtcclk@17000000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x17000000 0x0 0x2000>;
				reg-names = "csr-reg";
				csr-offset = <0xc>;
				csr-mask = <0x2>;
				enable-offset = <0x10>;
				enable-mask = <0x2>;
				clock-output-names = "rtcclk";
			};

			rngpkaclk: rngpkaclk@17000000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x17000000 0x0 0x2000>;
				reg-names = "csr-reg";
				csr-offset = <0xc>;
				csr-mask = <0x10>;
				enable-offset = <0x10>;
				enable-mask = <0x10>;
				clock-output-names = "rngpkaclk";
			};

			pcie0clk: pcie0clk@1f2bc000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2bc000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie0clk";
			};

			pcie1clk: pcie1clk@1f2cc000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2cc000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie1clk";
			};

			pcie2clk: pcie2clk@1f2dc000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2dc000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie2clk";
			};

			pcie3clk: pcie3clk@1f50c000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f50c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie3clk";
			};

			pcie4clk: pcie4clk@1f51c000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f51c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie4clk";
			};

			dmaclk: dmaclk@1f27c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f27c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "dmaclk";
			};
		};

		msi: msi@79000000 {
			compatible = "apm,xgene1-msi";
			msi-controller;
			reg = <0x00 0x79000000 0x0 0x900000>;
			interrupts = <  0x0 0x10 0x4
					0x0 0x11 0x4
					0x0 0x12 0x4
					0x0 0x13 0x4
					0x0 0x14 0x4
					0x0 0x15 0x4
					0x0 0x16 0x4
					0x0 0x17 0x4
					0x0 0x18 0x4
					0x0 0x19 0x4
					0x0 0x1a 0x4
					0x0 0x1b 0x4
					0x0 0x1c 0x4
					0x0 0x1d 0x4
					0x0 0x1e 0x4
					0x0 0x1f 0x4>;
		};

		scu: system-clk-controller@17000000 {
			compatible = "apm,xgene-scu","syscon";
			reg = <0x0 0x17000000 0x0 0x400>;
		};

		reboot: reboot@17000014 {
			compatible = "syscon-reboot";
			regmap = <&scu>;
			offset = <0x14>;
			mask = <0x1>;
		};

		csw: csw@7e200000 {
			compatible = "apm,xgene-csw", "syscon";
			reg = <0x0 0x7e200000 0x0 0x1000>;
		};

		mcba: mcba@7e700000 {
			compatible = "apm,xgene-mcb", "syscon";
			reg = <0x0 0x7e700000 0x0 0x1000>;
		};

		mcbb: mcbb@7e720000 {
			compatible = "apm,xgene-mcb", "syscon";
			reg = <0x0 0x7e720000 0x0 0x1000>;
		};

		efuse: efuse@1054a000 {
			compatible = "apm,xgene-efuse", "syscon";
			reg = <0x0 0x1054a000 0x0 0x20>;
		};

		edac@78800000 {
			compatible = "apm,xgene-edac";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			regmap-csw = <&csw>;
			regmap-mcba = <&mcba>;
			regmap-mcbb = <&mcbb>;
			regmap-efuse = <&efuse>;
			reg = <0x0 0x78800000 0x0 0x100>;
			interrupts = <0x0 0x20 0x4>,
				     <0x0 0x21 0x4>,
				     <0x0 0x27 0x4>;

			edacmc@7e800000 {
				compatible = "apm,xgene-edac-mc";
				reg = <0x0 0x7e800000 0x0 0x1000>;
				memory-controller = <0>;
			};

			edacmc@7e840000 {
				compatible = "apm,xgene-edac-mc";
				reg = <0x0 0x7e840000 0x0 0x1000>;
				memory-controller = <1>;
			};

			edacmc@7e880000 {
				compatible = "apm,xgene-edac-mc";
				reg = <0x0 0x7e880000 0x0 0x1000>;
				memory-controller = <2>;
			};

			edacmc@7e8c0000 {
				compatible = "apm,xgene-edac-mc";
				reg = <0x0 0x7e8c0000 0x0 0x1000>;
				memory-controller = <3>;
			};

			edacpmd@7c000000 {
				compatible = "apm,xgene-edac-pmd";
				reg = <0x0 0x7c000000 0x0 0x200000>;
				pmd-controller = <0>;
			};

			edacpmd@7c200000 {
				compatible = "apm,xgene-edac-pmd";
				reg = <0x0 0x7c200000 0x0 0x200000>;
				pmd-controller = <1>;
			};

			edacpmd@7c400000 {
				compatible = "apm,xgene-edac-pmd";
				reg = <0x0 0x7c400000 0x0 0x200000>;
				pmd-controller = <2>;
			};

			edacpmd@7c600000 {
				compatible = "apm,xgene-edac-pmd";
				reg = <0x0 0x7c600000 0x0 0x200000>;
				pmd-controller = <3>;
			};

			edacl3@7e600000 {
				compatible = "apm,xgene-edac-l3";
				reg = <0x0 0x7e600000 0x0 0x1000>;
			};

			edacsoc@7e930000 {
				compatible = "apm,xgene-edac-soc-v1";
				reg = <0x0 0x7e930000 0x0 0x1000>;
			};
		};

		pcie0: pcie@1f2b0000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
				0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
				  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
				  0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
					 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
					 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
					 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
			dma-coherent;
			clocks = <&pcie0clk 0>;
			msi-parent = <&msi>;
		};

		pcie1: pcie@1f2c0000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
				0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
				  0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
				  0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
					 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
					 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
					 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
			dma-coherent;
			clocks = <&pcie1clk 0>;
			msi-parent = <&msi>;
		};

		pcie2: pcie@1f2d0000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
				 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
				  0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
				  0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
					 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
					 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
					 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
			dma-coherent;
			clocks = <&pcie2clk 0>;
			msi-parent = <&msi>;
		};

		pcie3: pcie@1f500000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
				0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
				  0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
				  0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
					 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
					 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
					 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
			dma-coherent;
			clocks = <&pcie3clk 0>;
			msi-parent = <&msi>;
		};

		pcie4: pcie@1f510000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
				0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
				  0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
				  0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
					 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
					 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
					 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
			dma-coherent;
			clocks = <&pcie4clk 0>;
			msi-parent = <&msi>;
		};

		serial0: serial@1c020000 {
			status = "disabled";
			device_type = "serial";
			compatible = "ns16550a";
			reg = <0 0x1c020000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>; /* Updated by bootloader */
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4c 0x4>;
		};

		serial1: serial@1c021000 {
			status = "disabled";
			device_type = "serial";
			compatible = "ns16550a";
			reg = <0 0x1c021000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>; /* Updated by bootloader */
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4d 0x4>;
		};

		serial2: serial@1c022000 {
			status = "disabled";
			device_type = "serial";
			compatible = "ns16550a";
			reg = <0 0x1c022000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>; /* Updated by bootloader */
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4e 0x4>;
		};

		serial3: serial@1c023000 {
			status = "disabled";
			device_type = "serial";
			compatible = "ns16550a";
			reg = <0 0x1c023000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>; /* Updated by bootloader */
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4f 0x4>;
		};

		phy1: phy@1f21a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f21a000 0x0 0x100>;
			#phy-cells = <1>;
			clocks = <&sataphy1clk 0>;
			status = "disabled";
			apm,tx-boost-gain = <30 30 30 30 30 30>;
			apm,tx-eye-tuning = <2 10 10 2 10 10>;
		};

		phy2: phy@1f22a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f22a000 0x0 0x100>;
			#phy-cells = <1>;
			clocks = <&sataphy2clk 0>;
			status = "ok";
			apm,tx-boost-gain = <30 30 30 30 30 30>;
			apm,tx-eye-tuning = <1 10 10 2 10 10>;
		};

		phy3: phy@1f23a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f23a000 0x0 0x100>;
			#phy-cells = <1>;
			clocks = <&sataphy3clk 0>;
			status = "ok";
			apm,tx-boost-gain = <31 31 31 31 31 31>;
			apm,tx-eye-tuning = <2 10 10 2 10 10>;
		};

		sata1: sata@1a000000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a000000 0x0 0x1000>,
			      <0x0 0x1f210000 0x0 0x1000>,
			      <0x0 0x1f21d000 0x0 0x1000>,
			      <0x0 0x1f21e000 0x0 0x1000>,
			      <0x0 0x1f217000 0x0 0x1000>;
			interrupts = <0x0 0x86 0x4>;
			dma-coherent;
			status = "disabled";
			clocks = <&sata01clk 0>;
			phys = <&phy1 0>;
			phy-names = "sata-phy";
		};

		sata2: sata@1a400000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a400000 0x0 0x1000>,
			      <0x0 0x1f220000 0x0 0x1000>,
			      <0x0 0x1f22d000 0x0 0x1000>,
			      <0x0 0x1f22e000 0x0 0x1000>,
			      <0x0 0x1f227000 0x0 0x1000>;
			interrupts = <0x0 0x87 0x4>;
			dma-coherent;
			status = "ok";
			clocks = <&sata23clk 0>;
			phys = <&phy2 0>;
			phy-names = "sata-phy";
		};

		sata3: sata@1a800000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a800000 0x0 0x1000>,
			      <0x0 0x1f230000 0x0 0x1000>,
			      <0x0 0x1f23d000 0x0 0x1000>,
			      <0x0 0x1f23e000 0x0 0x1000>;
			interrupts = <0x0 0x88 0x4>;
			dma-coherent;
			status = "ok";
			clocks = <&sata45clk 0>;
			phys = <&phy3 0>;
			phy-names = "sata-phy";
		};

		sbgpio: sbgpio@17001000{
			compatible = "apm,xgene-gpio-sb";
			reg = <0x0 0x17001000 0x0 0x400>;
			#gpio-cells = <2>;
			gpio-controller;
			interrupts = 	<0x0 0x28 0x1>,
					<0x0 0x29 0x1>,
					<0x0 0x2a 0x1>,
					<0x0 0x2b 0x1>,
					<0x0 0x2c 0x1>,
					<0x0 0x2d 0x1>;
		};

		rtc: rtc@10510000 {
			compatible = "apm,xgene-rtc";
			reg = <0x0 0x10510000 0x0 0x400>;
			interrupts = <0x0 0x46 0x4>;
			#clock-cells = <1>;
			clocks = <&rtcclk 0>;
		};

		menet: ethernet@17020000 {
			compatible = "apm,xgene-enet";
			status = "disabled";
			reg = <0x0 0x17020000 0x0 0xd100>,
			      <0x0 0X17030000 0x0 0Xc300>,
			      <0x0 0X10000000 0x0 0X200>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0x3c 0x4>;
			dma-coherent;
			clocks = <&menetclk 0>;
			/* mac address will be overwritten by the bootloader */
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "rgmii";
			phy-handle = <&menetphy>;
			mdio {
				compatible = "apm,xgene-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
				menetphy: menetphy@3 {
					compatible = "ethernet-phy-id001c.c915";
					reg = <0x3>;
				};

			};
		};

		sgenet0: ethernet@1f210000 {
			compatible = "apm,xgene1-sgenet";
			status = "disabled";
			reg = <0x0 0x1f210000 0x0 0xd100>,
			      <0x0 0x1f200000 0x0 0Xc300>,
			      <0x0 0x1B000000 0x0 0X200>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0xA0 0x4>,
				     <0x0 0xA1 0x4>;
			dma-coherent;
			clocks = <&sge0clk 0>;
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "sgmii";
		};

		sgenet1: ethernet@1f210030 {
			compatible = "apm,xgene1-sgenet";
			status = "disabled";
			reg = <0x0 0x1f210030 0x0 0xd100>,
			      <0x0 0x1f200000 0x0 0Xc300>,
			      <0x0 0x1B000000 0x0 0X8000>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0xAC 0x4>,
				     <0x0 0xAD 0x4>;
			port-id = <1>;
			dma-coherent;
			clocks = <&sge1clk 0>;
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "sgmii";
		};

		xgenet: ethernet@1f610000 {
			compatible = "apm,xgene1-xgenet";
			status = "disabled";
			reg = <0x0 0x1f610000 0x0 0xd100>,
			      <0x0 0x1f600000 0x0 0Xc300>,
			      <0x0 0x18000000 0x0 0X200>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0x60 0x4>,
				     <0x0 0x61 0x4>;
			dma-coherent;
			clocks = <&xge0clk 0>;
			/* mac address will be overwritten by the bootloader */
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "xgmii";
		};

		xgenet1: ethernet@1f620000 {
			compatible = "apm,xgene1-xgenet";
			status = "disabled";
			reg = <0x0 0x1f620000 0x0 0xd100>,
			      <0x0 0x1f600000 0x0 0Xc300>,
			      <0x0 0x18000000 0x0 0X8000>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0x6C 0x4>,
				     <0x0 0x6D 0x4>;
			port-id = <1>;
			dma-coherent;
			clocks = <&xge1clk 0>;
			/* mac address will be overwritten by the bootloader */
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "xgmii";
		};

		rng: rng@10520000 {
			compatible = "apm,xgene-rng";
			reg = <0x0 0x10520000 0x0 0x100>;
			interrupts = <0x0 0x41 0x4>;
			clocks = <&rngpkaclk 0>;
		};

		dma: dma@1f270000 {
			compatible = "apm,xgene-storm-dma";
			device_type = "dma";
			reg = <0x0 0x1f270000 0x0 0x10000>,
			      <0x0 0x1f200000 0x0 0x10000>,
			      <0x0 0x1b000000 0x0 0x400000>,
			      <0x0 0x1054a000 0x0 0x100>;
			interrupts = <0x0 0x82 0x4>,
				     <0x0 0xb8 0x4>,
				     <0x0 0xb9 0x4>,
				     <0x0 0xba 0x4>,
				     <0x0 0xbb 0x4>;
			dma-coherent;
			clocks = <&dmaclk 0>;
		};
	};
};