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/*
* Device Tree Source for OMAP2420 SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "omap2.dtsi"
/ {
compatible = "ti,omap2420", "ti,omap2";
ocp {
l4: l4@48000000 {
compatible = "ti,omap2-l4", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x100000>;
prcm: prcm@8000 {
compatible = "ti,omap2-prcm";
reg = <0x8000 0x1000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scm: scm@0 {
compatible = "ti,omap2-scm", "simple-bus";
reg = <0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x1000>;
omap2420_pmx: pinmux@30 {
compatible = "ti,omap2420-padconf",
"pinctrl-single";
reg = <0x30 0x0113>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
};
scm_conf: scm_conf@270 {
compatible = "syscon";
reg = <0x270 0x100>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
scm_clockdomains: clockdomains {
};
};
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x20>;
ti,hwmods = "counter_32k";
};
};
gpio1: gpio@48018000 {
compatible = "ti,omap2-gpio";
reg = <0x48018000 0x200>;
interrupts = <29>;
ti,hwmods = "gpio1";
ti,gpio-always-on;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpio2: gpio@4801a000 {
compatible = "ti,omap2-gpio";
reg = <0x4801a000 0x200>;
interrupts = <30>;
ti,hwmods = "gpio2";
ti,gpio-always-on;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpio3: gpio@4801c000 {
compatible = "ti,omap2-gpio";
reg = <0x4801c000 0x200>;
interrupts = <31>;
ti,hwmods = "gpio3";
ti,gpio-always-on;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpio4: gpio@4801e000 {
compatible = "ti,omap2-gpio";
reg = <0x4801e000 0x200>;
interrupts = <32>;
ti,hwmods = "gpio4";
ti,gpio-always-on;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpmc: gpmc@6800a000 {
compatible = "ti,omap2420-gpmc";
reg = <0x6800a000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
};
mcbsp1: mcbsp@48074000 {
compatible = "ti,omap2420-mcbsp";
reg = <0x48074000 0xff>;
reg-names = "mpu";
interrupts = <59>, /* TX interrupt */
<60>; /* RX interrupt */
interrupt-names = "tx", "rx";
ti,hwmods = "mcbsp1";
dmas = <&sdma 31>,
<&sdma 32>;
dma-names = "tx", "rx";
status = "disabled";
};
mcbsp2: mcbsp@48076000 {
compatible = "ti,omap2420-mcbsp";
reg = <0x48076000 0xff>;
reg-names = "mpu";
interrupts = <62>, /* TX interrupt */
<63>; /* RX interrupt */
interrupt-names = "tx", "rx";
ti,hwmods = "mcbsp2";
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
status = "disabled";
};
msdi1: mmc@4809c000 {
compatible = "ti,omap2420-mmc";
ti,hwmods = "msdi1";
reg = <0x4809c000 0x80>;
interrupts = <83>;
dmas = <&sdma 61 &sdma 62>;
dma-names = "tx", "rx";
};
mailbox: mailbox@48094000 {
compatible = "ti,omap2-mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>, <34>;
interrupt-names = "dsp", "iva";
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <6>;
mbox_dsp: dsp {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
mbox_iva: iva {
ti,mbox-tx = <2 1 3>;
ti,mbox-rx = <3 1 3>;
};
};
timer1: timer@48028000 {
compatible = "ti,omap2420-timer";
reg = <0x48028000 0x400>;
interrupts = <37>;
ti,hwmods = "timer1";
ti,timer-alwon;
};
wd_timer2: wdt@48022000 {
compatible = "ti,omap2-wdt";
ti,hwmods = "wd_timer2";
reg = <0x48022000 0x80>;
};
};
};
&i2c1 {
compatible = "ti,omap2420-i2c";
};
&i2c2 {
compatible = "ti,omap2420-i2c";
};
/include/ "omap24xx-clocks.dtsi"
/include/ "omap2420-clocks.dtsi"
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