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/*
 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "imx28.dtsi"

/ {
	model = "DENX M28";
	compatible = "denx,m28", "fsl,imx28";

	memory {
		reg = <0x40000000 0x08000000>;
	};

	apb@80000000 {
		apbh@80000000 {
			gpmi-nand@8000c000 {
				#address-cells = <1>;
				#size-cells = <1>;
				pinctrl-names = "default";
				pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
				status = "okay";

				partition@0 {
					label = "bootloader";
					reg = <0x00000000 0x00300000>;
					read-only;
				};

				partition@1 {
					label = "environment";
					reg = <0x00300000 0x00080000>;
				};

				partition@2 {
					label = "redundant-environment";
					reg = <0x00380000 0x00080000>;
				};

				partition@3 {
					label = "kernel";
					reg = <0x00400000 0x00400000>;
				};

				partition@4 {
					label = "filesystem";
					reg = <0x00800000 0x0f800000>;
				};
			};
		};

		apbx@80040000 {
			i2c0: i2c@80058000 {
				pinctrl-names = "default";
				pinctrl-0 = <&i2c0_pins_a>;
				status = "okay";

				rtc: rtc@68 {
					compatible = "stm,m41t62";
					reg = <0x68>;
				};
			};
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_3p3v: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};
};
an> /* for DM365 only */ VPSS_CCDCPG /* for DM365 only */ }; struct vpss_sync_pol { unsigned int ccdpg_hdpol:1; unsigned int ccdpg_vdpol:1; }; struct vpss_pg_frame_size { short hlpfr; short pplen; }; /* Used for enable/disable VPSS Clock */ enum vpss_clock_sel { /* DM355/DM365 */ VPSS_CCDC_CLOCK, VPSS_IPIPE_CLOCK, VPSS_H3A_CLOCK, VPSS_CFALD_CLOCK, /* * When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api * following applies:- * en = 0 selects ENC_CLK * en = 1 selects ENC_CLK/2 */ VPSS_VENC_CLOCK_SEL, VPSS_VPBE_CLOCK, /* DM365 only clocks */ VPSS_IPIPEIF_CLOCK, VPSS_RSZ_CLOCK, VPSS_BL_CLOCK, /* * When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api * following applies:- * en = 0 disable internal PCLK * en = 1 enables internal PCLK */ VPSS_PCLK_INTERNAL, /* * When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api * following applies:- * en = 0 enables MMR clock * en = 1 enables VPSS clock */ VPSS_PSYNC_CLOCK_SEL, VPSS_LDC_CLOCK_SEL, VPSS_OSD_CLOCK_SEL, VPSS_FDIF_CLOCK, VPSS_LDC_CLOCK }; /* select input to ccdc on dm355 */ int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel); /* enable/disable a vpss clock, 0 - success, -1 - failure */ int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en); /* set sync polarity, only for DM365*/ void dm365_vpss_set_sync_pol(struct vpss_sync_pol); /* set the PG_FRAME_SIZE register, only for DM365 */ void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size); /* wbl reset for dm644x */ enum vpss_wbl_sel { VPSS_PCR_AEW_WBL_0 = 16, VPSS_PCR_AF_WBL_0, VPSS_PCR_RSZ4_WBL_0, VPSS_PCR_RSZ3_WBL_0, VPSS_PCR_RSZ2_WBL_0, VPSS_PCR_RSZ1_WBL_0, VPSS_PCR_PREV_WBL_0, VPSS_PCR_CCDC_WBL_O, }; /* clear wbl overflow flag for DM6446 */ int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel); /* set sync polarity*/ void vpss_set_sync_pol(struct vpss_sync_pol sync); /* set the PG_FRAME_SIZE register */ void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size); /* * vpss_check_and_clear_interrupt - check and clear interrupt * @irq - common enumerator for IRQ * * Following return values used:- * 0 - interrupt occurred and cleared * 1 - interrupt not occurred * 2 - interrupt status not available */ int vpss_dma_complete_interrupt(void); #endif