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/*
 * at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board
 *
 *  Copyright (C) 2015 Atmel,
 *                2015 Nicolas Ferre <nicolas.ferre@atmel.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */
/dts-v1/;
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
#include <dt-bindings/mfd/atmel-flexcom.h>

/ {
	model = "Atmel SAMA5D2 Xplained";
	compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		reg = <0x20000000 0x80000>;
	};

	clocks {
		slow_xtal {
			clock-frequency = <32768>;
		};

		main_xtal {
			clock-frequency = <12000000>;
		};
	};

	ahb {
		usb0: gadget@00300000 {
			status = "okay";
		};

		usb1: ohci@00400000 {
			num-ports = <3>;
			status = "okay";
		};

		usb2: ehci@00500000 {
			status = "okay";
		};

		sdmmc0: sdio-host@a0000000 {
			bus-width = <8>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sdmmc0_default>;
			non-removable;
			mmc-ddr-1_8v;
			status = "okay";
		};

		sdmmc1: sdio-host@b0000000 {
			bus-width = <4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sdmmc1_default>;
			status = "okay"; /* conflict with qspi0 */
		};

		apb {
			spi0: spi@f8000000 {
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi0_default>;
				status = "okay";

				m25p80@0 {
					compatible = "atmel,at25df321a";
					reg = <0>;
					spi-max-frequency = <50000000>;
				};
			};

			macb0: ethernet@f8008000 {
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_macb0_default>;
				phy-mode = "rmii";
				status = "okay";
			};

			uart1: serial@f8020000 {
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_uart1_default>;
				status = "okay";
			};

			i2c0: i2c@f8028000 {
				dmas = <0>, <0>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_i2c0_default>;
				status = "okay";

				pmic: act8865@5b {
					compatible = "active-semi,act8865";
					reg = <0x5b>;
					active-semi,vsel-high;
					status = "okay";

					regulators {
						vdd_1v35_reg: DCDC_REG1 {
							regulator-name = "VDD_1V35";
							regulator-min-microvolt = <1350000>;
							regulator-max-microvolt = <1350000>;
							regulator-always-on;
						};

						vdd_1v2_reg: DCDC_REG2 {
							regulator-name = "VDD_1V2";
							regulator-min-microvolt = <1100000>;
							regulator-max-microvolt = <1300000>;
							regulator-always-on;
						};

						vdd_3v3_reg: DCDC_REG3 {
							regulator-name = "VDD_3V3";
							regulator-min-microvolt = <3300000>;
							regulator-max-microvolt = <3300000>;
							regulator-always-on;
						};

						vdd_fuse_reg: LDO_REG1 {
							regulator-name = "VDD_FUSE";
							regulator-min-microvolt = <2500000>;
							regulator-max-microvolt = <2500000>;
							regulator-always-on;
						};

						vdd_3v3_lp_reg: LDO_REG2 {
							regulator-name = "VDD_3V3_LP";
							regulator-min-microvolt = <3300000>;
							regulator-max-microvolt = <3300000>;
							regulator-always-on;
						};

						vdd_led_reg: LDO_REG3 {
							regulator-name = "VDD_LED";
							regulator-min-microvolt = <3300000>;
							regulator-max-microvolt = <3300000>;
							regulator-always-on;
						};

						vdd_sdhc_1v8_reg: LDO_REG4 {
							regulator-name = "VDD_SDHC_1V8";
							regulator-min-microvolt = <1800000>;
							regulator-max-microvolt = <1800000>;
							regulator-always-on;
						};
					};
				};
			};

			flx0: flexcom@f8034000 {
				atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
				status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */

				uart5: serial@200 {
					compatible = "atmel,at91sam9260-usart";
					reg = <0x200 0x200>;
					interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
					clocks = <&flx0_clk>;
					clock-names = "usart";
					pinctrl-names = "default";
					pinctrl-0 = <&pinctrl_flx0_default>;
					atmel,fifo-size = <32>;
					status = "okay";
				};
			};

			uart3: serial@fc008000 {
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_uart3_default>;
				status = "okay";
			};

			flx4: flexcom@fc018000 {
				atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
				status = "okay";

				i2c2: i2c@600 {
					compatible = "atmel,sama5d2-i2c";
					reg = <0x600 0x200>;
					interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
					dmas = <0>, <0>;
					dma-names = "tx", "rx";
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&flx4_clk>;
					pinctrl-names = "default";
					pinctrl-0 = <&pinctrl_flx4_default>;
					atmel,fifo-size = <16>;
					status = "okay";
				};
			};

			i2c1: i2c@fc028000 {
				dmas = <0>, <0>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_i2c1_default>;
				status = "okay";

				at24@54 {
					compatible = "atmel,24c02";
					reg = <0x54>;
					pagesize = <16>;
				};
			};

			pinctrl@fc038000 {
				pinctrl_flx0_default: flx0_default {
					pinmux = <PIN_PB28__FLEXCOM0_IO0>,
						 <PIN_PB29__FLEXCOM0_IO1>;
					bias-disable;
				};

				pinctrl_flx4_default: flx4_default {
					pinmux = <PIN_PD12__FLEXCOM4_IO0>,
						 <PIN_PD13__FLEXCOM4_IO1>;
					bias-disable;
				};

				pinctrl_i2c0_default: i2c0_default {
					pinmux = <PIN_PD21__TWD0>,
						 <PIN_PD22__TWCK0>;
					bias-disable;
				};

				pinctrl_i2c1_default: i2c1_default {
					pinmux = <PIN_PD4__TWD1>,
						 <PIN_PD5__TWCK1>;
					bias-disable;
				};

				pinctrl_macb0_default: macb0_default {
					pinmux = <PIN_PB14__GTXCK>,
						 <PIN_PB15__GTXEN>,
						 <PIN_PB16__GRXDV>,
						 <PIN_PB17__GRXER>,
						 <PIN_PB18__GRX0>,
						 <PIN_PB19__GRX1>,
						 <PIN_PB20__GTX0>,
						 <PIN_PB21__GTX1>,
						 <PIN_PB22__GMDC>,
						 <PIN_PB23__GMDIO>;
					bias-disable;
				};

				pinctrl_sdmmc0_default: sdmmc0_default {
					cmd_data {
						pinmux = <PIN_PA1__SDMMC0_CMD>,
							 <PIN_PA2__SDMMC0_DAT0>,
							 <PIN_PA3__SDMMC0_DAT1>,
							 <PIN_PA4__SDMMC0_DAT2>,
							 <PIN_PA5__SDMMC0_DAT3>,
							 <PIN_PA6__SDMMC0_DAT4>,
							 <PIN_PA7__SDMMC0_DAT5>,
							 <PIN_PA8__SDMMC0_DAT6>,
							 <PIN_PA9__SDMMC0_DAT7>;
						bias-pull-up;
					};

					ck_cd_rstn_vddsel {
						pinmux = <PIN_PA0__SDMMC0_CK>,
							 <PIN_PA10__SDMMC0_RSTN>,
							 <PIN_PA11__SDMMC0_VDDSEL>,
							 <PIN_PA13__SDMMC0_CD>;
						bias-disable;
					};
				};

				pinctrl_sdmmc1_default: sdmmc1_default {
					cmd_data {
						pinmux = <PIN_PA28__SDMMC1_CMD>,
							 <PIN_PA18__SDMMC1_DAT0>,
							 <PIN_PA19__SDMMC1_DAT1>,
							 <PIN_PA20__SDMMC1_DAT2>,
							 <PIN_PA21__SDMMC1_DAT3>;
						bias-pull-up;
					};

					conf-ck_cd {
						pinmux = <PIN_PA22__SDMMC1_CK>,
							 <PIN_PA30__SDMMC1_CD>;
						bias-disable;
					};
				};

				pinctrl_spi0_default: spi0_default {
					pinmux = <PIN_PA14__SPI0_SPCK>,
						 <PIN_PA15__SPI0_MOSI>,
						 <PIN_PA16__SPI0_MISO>,
						 <PIN_PA17__SPI0_NPCS0>;
					bias-disable;
				};

				pinctrl_uart1_default: uart1_default {
					pinmux = <PIN_PD2__URXD1>,
						 <PIN_PD3__UTXD1>;
					bias-disable;
				};

				pinctrl_uart3_default: uart3_default {
					pinmux = <PIN_PB11__URXD3>,
						 <PIN_PB12__UTXD3>;
					bias-disable;
				};
			};
		};
	};
};
n">mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b tst r2, #VM_EXEC mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer ret lr /* * flush_kern_dcache_area(void *addr, size_t size) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * * - addr - kernel address * - size - region size */ ENTRY(v4wb_flush_kern_dcache_area) add r1, r0, r1 /* fall through */ /* * coherent_kern_range(start, end) * * Ensure coherency between the Icache and the Dcache in the * region described by start. If you have non-snooping * Harvard caches, you need to implement this function. * * - start - virtual start address * - end - virtual end address */ ENTRY(v4wb_coherent_kern_range) /* fall through */ /* * coherent_user_range(start, end) * * Ensure coherency between the Icache and the Dcache in the * region described by start. If you have non-snooping * Harvard caches, you need to implement this function. * * - start - virtual start address * - end - virtual end address */ ENTRY(v4wb_coherent_user_range) bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b mov r0, #0 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache mcr p15, 0, r0, c7, c10, 4 @ drain WB ret lr /* * dma_inv_range(start, end) * * Invalidate (discard) the specified virtual address range. * May not write back any entries. If 'start' or 'end' * are not cache line aligned, those lines must be written * back. * * - start - virtual start address * - end - virtual end address */ v4wb_dma_inv_range: tst r0, #CACHE_DLINESIZE - 1 bic r0, r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry tst r1, #CACHE_DLINESIZE - 1 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain write buffer ret lr /* * dma_clean_range(start, end) * * Clean (write back) the specified virtual address range. * * - start - virtual start address * - end - virtual end address */ v4wb_dma_clean_range: bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b mcr p15, 0, r0, c7, c10, 4 @ drain write buffer ret lr /* * dma_flush_range(start, end) * * Clean and invalidate the specified virtual address range. * * - start - virtual start address * - end - virtual end address * * This is actually the same as v4wb_coherent_kern_range() */ .globl v4wb_dma_flush_range .set v4wb_dma_flush_range, v4wb_coherent_kern_range /* * dma_map_area(start, size, dir) * - start - kernel virtual start address * - size - size of region * - dir - DMA direction */ ENTRY(v4wb_dma_map_area) add r1, r1, r0 cmp r2, #DMA_TO_DEVICE beq v4wb_dma_clean_range bcs v4wb_dma_inv_range b v4wb_dma_flush_range ENDPROC(v4wb_dma_map_area) /* * dma_unmap_area(start, size, dir) * - start - kernel virtual start address * - size - size of region * - dir - DMA direction */ ENTRY(v4wb_dma_unmap_area) ret lr ENDPROC(v4wb_dma_unmap_area) .globl v4wb_flush_kern_cache_louis .equ v4wb_flush_kern_cache_louis, v4wb_flush_kern_cache_all __INITDATA @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions v4wb